2.7 nand and nor logic networks

2.7 NAND and NOR logic networks

• Introduce the use of NAND and NOR gates in the synthesis of logic circuits– Attractive due to their simpler electronic circuits

implementation than AND and OR functions– Q: Can be used directly in the synthesis of logic

circuits? And how?

1

x 1 x 2

x n

x 1 x 2 x n + + + x 1 x 2

x 1 x 2 +

x 1 x 2

x n

x 1 x 2

x 1 x 2 x 1 x 2 x n

(a) NAND gates

(b) NOR gates

A bubble at the output side of the gate symbols represents the complemented output signal.

Graphical symbols for NAND and NOR gates (Figure 2.20)

2

x 1 x 2

x 1

x 2

x 1 x 2

x 1 x 2

x 1

x 2

x 1 x 2

DeMorgan’s theorem in terms of logic gates

3

(a)

(b)

A NAND gate is equivalent to the OR gate with inversions at its inputs.

A NOR gate is equivalent to the AND gate with inversions at its inputs

Figure 2.22. Using NAND gates to implement a sum-of-products.

x 1 x 2 x 3 x 4 x 5

x 1 x 2 x 3 x 4 x 5

x 1 x 2 x 3 x 4 x 5

Transform a AND-OR networks into a network of NAND gates1. Replace each connection

between AND and OR gate by inversions of signals.

2. Replace OR gate with inverted inputs by a NAND gate.

4

Double inversion hasno effect on the network behavior.

Same topology!

1

2

Figure 2.23. Using NOR gates to implement a product-of sums.

x 1 x 2

x 3 x 4 x 5

x 1 x 2

x 3 x 4 x 5

x 1 x 2

x 3 x 4 x 5

5

• Can implement any OR-AND network as a NOR-NOR network having the same topology with the similar transformation procedure.

Example 2.6

• Let us implement the function using NOR gates only

=

• The POS expression (x1 + x2 + x3) (x1+x2+)(+x2+) // apply combining property 14b to // M0 and M1; M1 and M5 = ()

6

x1 x2 x3 F0 0 0 00 0 1 00 1 0 10 1 1 11 0 0 11 0 1 01 1 0 11 1 1 1

Combining property 14b. (x + y) (x + ) = x

Figure 2.24 NOR-gate realization of the function in Example 2.4.

x1

f

(a) POS implementation in Example 2.4

(b) NOR implementation

f

x3

x2

x1

x3

x2

7

=

Example 2.7

• Let us implement the function using NAND gates only

• The SOP expression

// merge m2, m3, m6, and m7 using P12a; // merge m4 and m6

= = x2 +

8

x1 x2 x3 F0 0 0 00 0 1 00 1 0 10 1 1 11 0 0 11 0 1 01 1 0 11 1 1 1

All 4 combinations = 1

Distributive property12a. x (y + z) = xy + xz

Figure 2.25. NAND-gate realization of the function in Example 2.3.

f

f

(a) SOP implementation

(b) NAND implementation

x1

x3

x2

x3

x2

x1

9

f x1

x3

x2

x2= x2+x2

=

2.8 Design Examples

• Basic issues that a designer is always confronted with– Necessary to specify the desired behavior of the

circuit.– The circuit has to be synthesized and

implemented.

10

Figure 2.26. Truth table for a three-way light control.

Three-way light control

11

Let x1, x2, and x3 be the input variables that denote the state of each switch.Assume that• the light is off if all switches are

open• Closing any one of the switches will turn the light on.• Closing a second switch will have

to turn off the light, that is to say, light will be off if two (or no) switches are closed.

• Turn the light on by closing the third switch if two switches are closed.

Canonical SOP and POS

• SOP expression for the specified function

• POS expression for the specified function

12

f

x1

x3 x2

f

x3

x1 x2

(a) Sum-of-products realization

(a) Product-of-sums realization 13

x1 x2 x3 f1 f2 f3 f4 f0 0 0 0 1 1 1 00 0 1 1 1 1 1 10 1 0 1 1 1 1 10 1 1 1 1 1 0 01 0 0 1 1 1 1 11 0 1 1 1 0 1 01 1 0 1 0 1 1 01 1 1 1 1 1 1 1

f1

f2

f3

f4

Multiplexer

• A circuit that generates an output that exactly reflects the state of one of a number of data inputs, based on the value of one or more selection control inputs.

14

0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1

s x1 x2 f (s, x1, x2)

f(s, x1, x2) = //12a

= = =

Distributive property12a. x (y + z) = xy + xz

Implementation of a 2-to-1 multiplexer

0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1

(a) Truth table

s x1 x2 f (s, x1, x2)f

x 1

x 2 s

(b) Circuit

f

s

x 1 x 2

0 1

(c) Graphical symbol

0 1

(d) More compact truth-table representation

f (s, x1, x2)sx1

x2

15

=

More about complex multiplexer

• A 4-to-1 multiplexer has four data inputs and one output– Two selection control inputs are needed

• A 8-to-1 multiplexer needs eight data inputs and three selection control inputs

• Same circuit structure can be used to implement multiplexer using NAND gates.

• More discussions on multiplexer are in Chapter 3 and 6.

16

2.12 EXAMPLES OF SOLVED PROBLEMS

17

Example 2.8

Determine if the following equation is valid

Solution: Derive a canonical SOP form for each expression (an algebraic approach)LHS = =

( 2 0 7 3 5 4 )

= RHS = = =

18

Example 2.9

Determine the minimum-cost POS expression for the function f(x1,x2,x3,x4) = Solution: To find a POS expression we should start with the definition in terms of maxiterms, which is f = f = = (x1+x2+x3+) (x1+x2++) (+x2+x3+)

(+x2++) (++x3+) = x1 + x2 + // combining property 14b = + x2 + = + x3 + f = (x1+x2+) (+x2+) (+x3+) = (x2+) (+x3+)

19

Combining property 14b. (x + y) (x + ) = x

Example 2.12

Derive the simplest SOP expression for the function

Solution:f = //consensus

= // combining = = // absorption =

20

Absorption13a. x+xy = x

Combining14a. xy+x = x

Consensus17a. xy + = xy+

Figure P2.3. A timing diagram representing a logic function.

Synthesize the function in the simplest SOP form

1 0 1 0 1 0 1 0

x 1

x 2

Time

x 3

f

Problem 2.31

21

0

0

1

0

0

1

0

0

0

0

0

1

0

1

1

1

1

0

0

0

1

0

1

1

1

1

0

1

1

1

1

0

The simplest SOP expression isx3+x1x2

1 0 1 0 1 0 1 0

x 1

x 2

Time

x 3

f

Problem 2.31

22

x1 x2 x3 f0 0 0 10 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 11 1 1 0

0

0

1

0

0

1

0

0

0

0

0

1

0

1

1

1

1

0

0

0

1

0

1

1

1

1

0

1

1

1

1

0