2. super kekb meeting, 17-19.3.2009 depfet electronics depfet readout and control electronics ivan...

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

DEPFET Readout and Control Electronics

Ivan Peric, Peter Fischer, Christian Kreidl Heidelberg University

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

Outline

- Module Electronics - Introduction- Principle of DEPFET readout- Switcher with LV transistors (Switcher 3)- Switcher with HV transistors- DCD Chip- Bumping technologies

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

DEPFET readout and control-ASICS

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

DEPFET readout and control-ASICS

DCD#0 – DCD#5Switcher#0

Switcher#4

ACTIVE AREA

Sensor – active area

Sensor balcony

Chip

Switcher – row control chip with high voltage line drivers

0.35 μm technology

DCD – DEPFET current receiver and digitizer chip

0.18 μm technology

DHP – Digital data handling and readout control chip

0.09 μm technology

960X512

(160 channels each)

(32 channels each)

Bump bonding

Fan-out

Switcher

DCD

DHP

DHP

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

Layout (Preliminary)

DCDs

Switcher

Width =1.6mm!

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

Principle of DEPFET readout

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

Readout principle 1 – signal collection – internal gate

p+ p+

Internal gate (n+)

PMOS

n+

DEPFET pixeln-(depleted)

G

DS Clr

DHP

DCD#0 – DCD#5SWITCHER#0

SWITCHER#4

ACTIVE AREA

Signal generation

Signal collection

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

Readout principle – start of the readout

p+ p+

Internal gate (n+)

PMOS

n+

DEPFET pixeln-(depleted)

G

DS Clr

DHP

DCD#0 – DCD#5SWITCHER#0

SWITCHER#4

ACTIVE AREA

Signal collection

Signal generation

Read out

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

G

DHP

DCD#0 – DCD#5SWITCHER#0

SWITCHER#4

ACTIVE AREA

Readout principle – switcher generates high voltage – row on

p+ p+

Internal gate (n+)

PMOS

n+

DEPFET pixeln-(depleted)

DS Clr

Signal collection

Signal generation

Read out

Row on

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

Readout principle – drain current is stored in DCD

DHP

DCD#0 – DCD#5SWITCHER#0

SWITCHER#4

ACTIVE AREA

p+ p+

Internal gate (n+)

PMOS

n+

DEPFET pixeln-(depleted)

DS Clr

Signal collection

Signal generation

Read out

Row on

Signal memorizing

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

Readout principle – start of clearing

DHP

DCD#0 – DCD#5SWITCHER#0

SWITCHER#4

ACTIVE AREA

p+ p+

Internal gate (n+)

PMOS

n+

DEPFET pixeln-(depleted)

DS Clr

Signal collection

Signal generation

Read out

Row on

Signal memorizing

Clearing

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

Readout principle – clearing, offset current subtracted in DCD

DHP

DCD#0 – DCD#5SWITCHER#0

SWITCHER#4

ACTIVE AREA

p+ p+

Internal gate (n+)

PMOS

n+

DEPFET pixeln-(depleted)

DS Clr

Signal collection

Signal generation

Read out

Row on

Signal memorizing

Clearing

Signal – offest subtraction

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

Readout principle – A/D conversion

p+ p+

Internal gate (n+)

PMOS

n+

DEPFET pixeln-(depleted)

G

DS Clr

DHP

DCD#0 – DCD#5SWITCHER#0

SWITCHER#4

ACTIVE AREA

00110

Signal collection

Signal generation

Read out

Row on

Signal memorizing

Clearing

Signal – offest subtractionA/D conversion

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

Row control “Switcher” chip

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

Switcher with LV transistors – Switcher 3

Switcher 3

Radiation tolerant layout in 0.35 μm technology

128 channels

+ Very fast

- Operation up to 11.5 V

Novel design: Uses stacked LV transistors, HV twin-wells and capacitors as level-shifters

+ No DC power consumption

HV channel with 3+3 Switch transistors and 4 AC coupling stages (180x180µm, M4 not shown)

interdigitatedAC coupling caps

Ivan Peric, Mannheim

80µmopenin

g

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

Switcher 3 – output driver

Use an SRAM cell flipped by a transient voltageNo dc power consumption!

9V

out

‘SRAM’

3V

‘SRAM’

6V

‘SRAM’

‘SRAM’

0V

3V

6V

ResetReset

~200 fF

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

Switcher with LV transistors – Switcher 3

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

Rising/Falling Edge vs. Cload

2ns !

9V !

0pF (1.8ns

)

10pF (4ns)

22pF (8ns)

47pF (18ns)

0pF (1.5ns)

10pF (3.8ns

)

22pF (6.5ns)

47pF (14ns)

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

Switcher 3 chip irradiation up to 22 MRad

Only degradation in speed which can be avoided using larger transistors

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

Switcher 4

Switcher 3

Uses radiation tolerant high voltage transistors in HV 0.35 μm technology

64 channels

+ fast enough

+ Possible operation up to 50 V (30V tested)

+ low DC power consumption

Enclosed design of NMOS HV transistors

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

Switcher 4 chip – high voltage transistors

Hi voltage Hi voltage Hi voltage Hi voltage

20V 0V17-20V 0-3V0-20VThin oxide

Thick oxide

n-

p-

p-

n-

Vertical NMOSPMOS

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

D

S

D

S

Thick oxid Leakage current

Standard NMOSAnnular gate NMOS

G

G

Annular gate vertical NMOS

S

B

G

D

Difefrent types of radiation-soft and -hard NMOS transistors

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

logic out

20V

17V

3V

0V

in

Switcher 4 chip output driver

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

logic out

20V

17V

3V

0V

in

Switcher 4 chip output driver

30V amplitude

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

Irradiation of NMOS transistors

0,0 0,1 0,2 0,3 0,4 0,50

20

40

60

80

100

120

140

160

Cu

rre

nt [

µA

]

Gate Voltage [V]

X-ray irradiation up to ~600 kradNo threshold shift or leakage current for annular structures

0,0 0,1 0,2 0,3 0,4 0,50

10

20

30

40

50

60

70

80

90

100

Cu

rre

nt [

µA

]

Gate Voltage [V]0,0 0,1 0,2 0,3 0,4 0,5

0

10

20

30

40

50

Cur

rent

[µA

]

Gate Voltage [V]

600 krad

before

stacked ‘normal’annular NMOS

‘HV’ NMOS: thin gate oxide,

extended thick drain, enclosed gate

‘HV’ NMOS, normal layout

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

DEPFET signal digitizer chip - DCD

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

DCD3 chip

- Technology 0.18 μm- 72 Channels - 2 ADCs and regulated

cascode/channel- 6 channels multiplexed to one digital

LVDS output- ADC sampling period 160 ns (8 bits)- Channel sampling period 80 ns - LVDS output: 600 M bits/s- Chip: 7.2 G bits/s (12 outputs)- Radiation tolerant design- ~ 1mW/ADC

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

DCD3 chip

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

DCD3 ADC

Reg. cascode

Double sampling

DEPFET

W

NC

R

R

R

R

L

L

NC

R

R

W R

R

L

L

W

R

1234567

1234567

7 7

7

7 76 65 5

543

543

6 67 7

3

Gate On

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

DCD 3 measurements

-8 -6 -4 -2 0 2 4 6 8

0

50

100

150

200

250

300Mean value for 62 measurements

ADC outputDeviation from fit

AD

C o

utp

ut

Input current/mA

-1,5

-1,0

-0,5

0,0

0,5

1,0

1,5

De

viatio

n fro

m line

ar fit

-2 -1 0 1 20

2000

4000

6000

8000

10000

12000slow cellsigma noise = 0,60

Num

ber

of m

eas

ure

men

tsDeviation from mean/LSB

ADC characteristic Noise

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

DCD 3 irradiation up to 7 MRad

No significant changes after 7 Mrad and 6 days of annealing

ADC characteristic Analog characteristic of CSC

Noise – channel 1 Noise – channel 2

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

Chip Geometry: 1525 µm x 5000 µmTechnology 0.18 μmAnalog circuits in upper pixelsDigital circuits on the bottom

10 x 16 ANALOG parts(bump + cascode +

current memory + ADC)

AnalogPowerpads

DigitalPowerPads

DigitalOutputsControl

DIGITAL

10 x 4 outputs+ control

Pitch = 150µm

Chip architecture – (proposed for SBelle prototype)

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

Channel layout – (proposed for SBelle prototype)

A AAA AA

Bump-bond pad(Analog In)

Cell1 Cell2

A A

h, l

CmpHi CmpLo Cell3 Cell4CmpHi CmpLo

A

TC TC

MM cap

TCTCTC TC TC TCTC

(Receiver)

Digital output

ADC1ADC2

Sampling cell 1

Sampling cell 2

Reg. cascode

IO line

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

Data handling processor - DHP

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

DHP architecture

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

DHP - block diagram of the data processing block

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

Bumping

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

Base technology – chip with gold stuts

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

1. Gold Studs2. Buy chips with PbSn bumps or similar

(possible for UMC via SPIL wafer bumping service, IBM,…)3. Get everything done by company

Techno Min.pitch

Bumppad

Max.bumps

Pressure / bump

UBMSensor

WafersNeeded

Rework Cost Who

Au Stud

100 70 (60) 600 >25g no no No LowHD,

(BN, HLL)

BumpedChips

150-200

50 (?) 0 yes No Yes MedHD,

(BN, HLL)

DepositPbSn

~100 70(?) 0 yes No Yes LowPACTEC(HD ?)

Byvendor

50 15 0 yes yes Yes High IZM,…

Bumping possibilities

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

Conclusions

- DCD prototype chip has been tested with test signals that correspond to DEPFET currents and irradiated up to 7 Mrad.

The chip works fine and has high enough conversion speed. Operation with matrices still to be tested – we do not expect problems. Only „fine tuning“ of the design for the super KEKB operation is necessary.- Switcher prototype with LV transistors has been tested and irradiated up to 22 MRad. The chip works fine and has adequate speed for SBelle operation.- Another prototype with HV transistors has been designed and tested.- The irradiation of the chip still has to be done but the basic and most critical part (high-

voltage NMOS) has been irradiated up to 600 KRad and no damage has been observed.- DHP chip will be designed using digital design tools in intrinsically radiation hard 90 nm

technology.

- Choice between 4 different bumping technologies – advantages and disadvantages still to be evaluated…

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

Thank you

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

DCD2 (CNT = 2)

Reg. cascode

Double sampling

DEPFET

W

NC

R

R

R

R

L

L

NC

R

R

W R

R

L

L

W

R

1234567

1234567

7 7

7

7 76 65 5

543

543

6 67 7

3

Gate On

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

DCD2 (CNT = 3)

01234567

01234567

Reg. cascode

Double sampling

DEPFET

NC

W

R

R

C

C

L

L

W

R

R

NC C

C

L

L

W

R

Z

7 76 65 54 4

54

54

6 67 7

4

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

DCD2 (CNT = 4)

Reg. cascode

Double sampling

DEPFET

R

R

W

NC

L

L

R

R

R

W

NC

R L

L

R

R

W

R

01234567

01234567

C

7 76 65 54 4

54

54

6 67 7

4

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

Clear On

DCD2 (CNT = 5)

7 7

Reg. cascode

Double sampling

DEPFET

R

R

NC

W

L

L

C

C

R

NC

W

R L

L

C

C

R

W

54321

54321

6 67 7

Z

7 76 65 54 43 3

5 56 67 7

5

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

DCD2 (CNT = 6)

Reg. cascode

Double sampling

DEPFET

W

NC

R

R

R

R

L

L

NC

R

R

W R

R

L

L

R

W

7 7

54321

54321

6 67 7

1

7 76 65 54 43 3

5 56 67 7

5

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

DCD2 (CNT = 7)

Double sampling

NC

W

R

R

C

C

L

L

W

R

R

NC C

C

L

L

Reg. cascode

DEPFET

R

W

7 76 6

5432

5432

6 67 7

2

7 76 65 54 43 32 2

6 67 7

6

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

DCD2 (CNT = 8)

Double sampling

R

R

W

NC

L

L

R

R

R

W

NC

R L

L

R

R

Reg. cascode

DEPFET

R

W

7 76 6

5432

5432

6 67 7

2

7 76 65 54 43 32 2

6 67 7

6

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

DCD2 (CNT = 9)

Double sampling

R

R

NC

W

L

L

C

C

R

NC

W

R L

L

C

C

Reg. cascode

DEPFET

R

W

7 76 65 5

543

543

6 67 7

3

7 76 65 54 43 32 21 1

7 7

7

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

DCD2 (CNT = 10)

Reg. cascode

Double sampling

DEPFET

W

NC

R

R

R

R

L

L

NC

R

R

W R

R

L

L

W

R

7 76 65 5

543

543

6 67 7

1234567

1234567

7 7

3

7

Gate On

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

DCD2 (CNT = 11)

Reg. cascode

Double sampling

DEPFET

NC

W

R

R

C

C

L

L

W

R

R

NC C

C

L

L

W

R

7 76 65 54 4

54

54

6 67 7

4

01234567

01234567

Z

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

DCD2 (CNT = 12)

Reg. cascode

Double sampling

DEPFET

R

R

W

NC

L

L

R

R

R

W

NC

R L

L

R

R

W

R

7 76 65 54 4

54

54

6 67 7

4

01234567

01234567

C

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

DCD2 (CNT = 13)

Reg. cascode

Double sampling

DEPFET

R

R

NC

W

L

L

C

C

R

NC

W

R L

L

C

C

R

W

7 76 65 54 43 3

5 56 67 7

5

7 7

54321

54321

6 67 7

Z

Clear On

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

DCD2 (CNT = 14)

Reg. cascode

Double sampling

DEPFET

W

NC

R

R

R

R

L

L

NC

R

R

W R

R

L

L

R

W

7 76 65 54 43 3

5 56 67 7

5

7 7

54321

54321

6 67 7

1

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

DCD2 (CNT = 15)

Double sampling

NC

W

R

R

C

C

L

L

W

R

R

NC C

C

L

L

Reg. cascode

DEPFET

R

W

7 76 65 54 43 32 2

6 67 7

6

7 76 6

5432

5432

6 67 7

2

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

DCD2 (CNT = 0)

Double sampling

R

R

W

NC

L

L

R

R

R

W

NC

R L

L

R

R

Reg. cascode

DEPFET

R

W

7 76 65 54 43 32 2

6 67 7

6

7 76 6

5432

5432

6 67 7

2

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

DCD2 (CNT = 1)

Double sampling

R

R

NC

W

L

L

C

C

R

NC

W

R L

L

C

C

Reg. cascode

DEPFET

R

W

7 76 65 54 43 32 21 1

7 7

7

7 76 65 5

543

543

6 67 7

3

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

DCD2 (CNT = 2)

Reg. cascode

Double sampling

DEPFET

W

NC

R

R

R

R

L

L

NC

R

R

W R

R

L

L

W

R

1234567

1234567

7 7

7

7 76 65 5

543

543

6 67 7

3

Gate On

2. Super KEKB Meeting, 17-19.3.2009 DEPFET Electronics

DCD2 (CNT = 3)

01234567

01234567

Reg. cascode

Double sampling

DEPFET

NC

W

R

R

C

C

L

L

W

R

R

NC C

C

L

L

W

R

Z

7 76 65 54 4

54

54

6 67 7

4