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A Bit-Serial Message-PassingLow-Density Parity-Check Decoder

Ahmad Darabiha

Supervisors:

Prof. A. Chan CarusoneProf. F. R. Kschischang

June 2007

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A Generic Communication Channel

• Channel coding: • Adding redundancy

• Detecting and correcting errors

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History

• 1948: Claude Shannon • Fundamental theorem in information theory

• 1960: Reed-Solomon codes • CD, DVD, wireless and optical communications

• 1967: Viterbi decoding (convolutional codes) • Magnetic recording, space communications

• 1993: Turbo codes • 3G-wireless, satellite communication

• 1995 (1963): Low-density parity-check (LDPC) codes • Digital Video Broadcast (DVB-S2)

• 10 Gigabit Ethernet (IEEE802.3an)

• Mobile WiMax (IEEE802.16)

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LDPC Codes: Structure

• Decoding LDPC codes: • An iterative message-passing algorithm

• Provides Fine-scale parallelism

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Min-Sum LDPC Decoding

• A form of iterative soft-decision decoding1 2

• Min functions for check node update

• Sum functions for variable node update

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Decoder Architecture• Fully parallel architecture• Advantage:

• High decoding throughput

• Major problem:• Each edge requires multiple wires to carry multi-bit messages

• Routing congestion

• Proposed Solution:• Bit-serial message passing

• Multi-bit messages are transferred over a single wire

• Reduced number of wires => Reduce routing congestion

• Min and Sum operations are both naturally bit-serial

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Implementations

• ASIC: A (660, 484) regular LDPC decoder fabricated in a 0.13um CMOS process

• FPGA: A (480, 360) LDPC decoder implemented on Transmogrifier-4 (TM4) prototyping system

FPGA device Stratix EP1S80

Logic 66,000 LUTs

Code rate 0.74

Code length 480

Iterations per frame 15

Clock frequency 61 MHz

Throughput 650 Mbit/sec