1 hardware synthesis 2.0 byron cook and satnam singh with ashutosh gupta, stephen magill, andrey...
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1
Hardware synthesis 2.0
Byron Cook and Satnam Singhwith Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis
2
Explosion of advances in program verification
Impossible 10 years ago, standard today SLAM, SpaceInvader, ARMC, Thor, RGSep, TERMINATOR, etc WP synthesis, WLP synthesis,
Challenges in automatic program verification Concurrency Data structures Scalability/precision Productization New applications
3
Beyond proving correctness
Can we use these techniques elsewhere? Compilers ? Operating systems? Language runtimes?
Current focus: hardware synthesis Synthesis for heap-based programs using techniques from
termination provers Automatically parallelize circuits, and localize memories on
chip using techniques from heap analysis Aggressive unrolling of loops during synthesis using
complexity analysis
Can we use these tools elsewhere? Compilers ? Operating systems? Language runtimes?
Current focus: hardware synthesis Synthesis for heap-based programs using techniques from
termination provers Automatically parallelize circuits, and localize memories on
chip using techniques from heap analysis Aggressive unrolling of loops during synthesis using
complexity analysis
4
Beyond proving correctness
Can we use these tools elsewhere? Compilers ? Operating systems? Language runtimes?
Current focus: hardware synthesis Synthesis for heap-based programs using techniques from
termination provers Automatically parallelize circuits, and localize memories on
chip using techniques from heap analysis Aggressive unrolling of loops during synthesis using
complexity analysis
5
Beyond proving correctness
Can we use these tools elsewhere? Compilers ? Operating systems? Language runtimes?
Current focus: hardware synthesis Synthesis for heap-based programs using techniques from
termination provers Automatically parallelize circuits, and localize memories on
chip using techniques from heap analysis Aggressive unrolling of loops during synthesis using
complexity analysis
6
Beyond proving correctness
Can we use these techniques elsewhere? Compilers ? Operating systems? Language runtimes?
Current focus: hardware synthesis Synthesis for heap-based programs using techniques from
termination provers Automatically parallelize circuits, and localize memories on
chip using techniques from heap analysis Aggressive unrolling of loops during synthesis using
complexity analysis
7
Beyond proving correctness
8
Hardware synthesis
Cfile
HardwareSynthesis
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Hardware synthesis
Cfile
HardwareSynthesis
10
Hardware synthesis
Cfile
HardwareSynthesis
11
Hardware synthesis
Cfile
HardwareSynthesis
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Hardware synthesis
HardwareSynthesis
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Hardware synthesis
HardwareSynthesis
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Hardware synthesis
HardwareSynthesis
15
Hardware synthesis
Cfile
ShapeAnalysis α filepass Termination
Analysis
error
pass
XX
error
XX
BoundsSynthesis
XXfailure
HardwareSynthesis
16
Hardware synthesis
Cfile
17
Hardware synthesis
Cfile
ShapeAnalysis α filepass
error
XX
18
Hardware synthesis
Cfile
ShapeAnalysis α filepass
error
XX
19
Hardware synthesisXX
20
Hardware synthesis
Cfile
ShapeAnalysis α filepass Termination
Analysis
error
pass
XX
error
XX
21
Hardware synthesis
Cfile
ShapeAnalysis α filepass Termination
Analysis
error
pass
XX
error
XX
BoundsSynthesis
XXfailure
pass
22
Hardware synthesis
Cfile
ShapeAnalysis α filepass Termination
Analysis
error
pass
XX
error
XX
BoundsSynthesis
XXfailure
pass
23
Hardware synthesis
Cfile
ShapeAnalysis α filepass Termination
Analysis
error
pass
XX
error
XX
BoundsSynthesis
XXfailure
pass
24
Hardware synthesis
Cfile
ShapeAnalysis α filepass Termination
Analysis
error
pass
XX
error
XX
BoundsSynthesis
XXfailure
pass
25
Hardware synthesis
Cfile
ShapeAnalysis α filepass Termination
Analysis
error
pass
XX
error
XX
BoundsSynthesis
XXfailure
pass
26
Hardware synthesis
Cfile
ShapeAnalysis α filepass Termination
Analysis
error
pass
XX
error
XX
BoundsSynthesis
XXfailure
pass
27
Hardware synthesis
Cfile
ShapeAnalysis α filepass Termination
Analysis
error
pass
XX
error
XX
BoundsSynthesis
XXfailure
pass
28
Hardware synthesis
Cfile
ShapeAnalysis α filepass Termination
Analysis
error
pass
XX
error
XX
BoundsSynthesis
XXfailure
HardwareSynthesis
29
Hardware synthesis
Cfile
ShapeAnalysis α filepass Termination
Analysis
error
pass
XX
error
XX
BoundsSynthesis
XXfailure
HardwareSynthesis
30
Hardware synthesis
pass
error
pass
XX
error
XX
XXfailure
α fileShapeAnalysis
TerminationAnalysis
BoundsSynthesis
HardwareSynthesis
Cfile
31
α file
failure
Hardware synthesis
ShapeAnalysis
pass TerminationAnalysis
error
pass
error
BoundsSynthesis
XX
XX
Cfile
PreconditionSynthesis
XX
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α file
failure
Hardware synthesis
ShapeAnalysis
pass TerminationAnalysis
error
pass
error
BoundsSynthesis
XX
XX
Cfile
PreconditionSynthesis
XX
Altera DE2 FPGA Board
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Altera synthesis/implementation tools
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Synthesized logic
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VHDL simulation of prio netlist
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Logic analyzer output
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Conclusion
Big advances in formal verification, analysis, understanding
Alternative uses for these new techniques? Compiling for embedded systems or hardware? Automatic parallelization? Speculative execution and rollback? Mixed static/dynamic property checking in runtimes? Runtime verification of progress (i.e. termination)?
Current project Solving open problems in hardware synthesis Further blurring the line between hardware and software Demo: first-known synthesis tool supporting dynamic heap
39
Conclusion
Big advances in formal verification, analysis, understanding
Alternative uses for these new techniques? Compiling for embedded systems or hardware? Automatic parallelization? Speculative execution and rollback? Mixed static/dynamic property checking in runtimes? Runtime verification of progress (i.e. termination)?
Current project Solving open problems in hardware synthesis Further blurring the line between hardware and software Demo: first-known synthesis tool supporting dynamic heap
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