1 60-265: computer architecture 1: digital design simplification and implementation f =...
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60-265: Computer Architecture 1: Digital Design
SIMPLIFICATION and IMPLEMENTATION F = ∑m(1,4,5,6,7) F = A’B’C+ (AB’C’+AB’C) + (ABC’+ABC) Use X’ +
X = 1. = A’B’C + (AB’ + AB) Again use X’ +
X = 1. = A’B’C + A Use X + X’.Y = X + Y.
= A + B’C
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Implementation of Inverter/AND/OR using NAND gates only
Inverter using NAND
AND using NAND
OR using NAND
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IMPLEMENTATION of F = A + B’C using NAND gates only
To implement the previous simplified function by using NAND gates only:
X NAND Y = (X.Y)’F = (A + B’.C)’’ = ( (A + B’.C)’ )’ = (A’.(B’.C)’)’
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Implementation of Inverter/AND/OR using NOR gates only
Inverter using NOR
AND using NOR
OR using NOR
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IMPLEMENTATION of F = A + B’C using NOR gates onlyTo implement the same function by using
NOR gates only: X NOR Y = (X + Y)’
F = (A + B’C)’’ = ((A + (B’C)’’)’)’ = ((A + (B+C’)’ )’)’ = ((A + P)’)’
Variables, Literals and mintermsVariables: A, B or C; # of Variables = n Literals: A, A’, B, B’, C or C’# of literals = 2n minterm: ANDing of n literals such that if
a literal x is present, its complement will not be present
A minterm is equal to 1 for only one set of values of the variables. For all other sets of values of the variables, the minterm is equal to 0.
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Maxterms
Maxterm: ORing of n literals such that if a literal x is present, its complement will not be present
A Maxterm is equal to 0 for only one set of values of the variables. For all other sets of values of the variables, the Maxterm is equal to 1.
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Examples: minterm and Maxterms for a Function of 3 variables:
A B C minterm F Maxterm0 0 0 A’.B’.C’ 0 A + B + C
0 0 1 A’.B’.C 1 A + B + C’0 1 0 A’.B.C’ 0 A + B’ + C0 1 1 A’.B.C 0 A + B’ + C’1 0 0 A.B’.C’ 1 A’ + B + C1 0 1 A.B’.C 1 A’ + B + C’1 1 0 A.B.C’ 1 A’ + B’ + C1 1 1 A.B.C 1 A’ + B’ + C’
Defining a Function in terms of minterms and Maxterms
Definition: F = ∑ m(1,4,5,6,7) = M(0, 2, 3) F represents an output function, which is
equal to 1 for the rows with equivalent decimal value of 1, 4, 5, 6 and 7 and which is equal to 0 for the rows with equivalent decimal value of 0, 2 and 3.
F =A’.B’.C +A.B’.C’ +A.B’.C +A.B.C’ +A.B.C = (A + B + C).(A + B’ + C).(A + B’ + C’)
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Ex. 2: SIMPLIFICATION and IMPLEMENTATION
F = X.Y’.Z + X.Y.Z + X’.Y’.Z = (X+X’).Y’.Z +X.Y.Z Use X’ + X =
1.= Y’.Z + X.Y.Z = (Y’ +Y.X).Z = (Y’+X).Z Use X + X’.Y = X + Y.
To implement using NAND gates only: F = (Y’.Z+X.Z)’’F =( (Y’.Z)’ . (X.Z)’ )’ = (A.B)’
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Combinatorial Circuits
Combinatorial Circuit: A circuit, the outputs of which depend upon only the present values of the inputs only ( and not on the history of the past values of the inputs or outputs.)
Characteristic Table: shows the binary relationship between the n input variables and m output variables. For n variables, the Characteristic Table has 2n entries.
Half-adder
1
n
1m
HA
FA
A
B
S
C
XYZ
SC
Full-adder
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Combinatorial circuit: Half-Adder
Half Adder: It performs the arithmetic addition of two bits.
Symbols: A and B for two input variables , S for sum and C for carry.
A B S C0 0 0 00 1 1 01 0 1 01 1 0 1
C = A .B
S= A’B + AB’ = A B
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Combinatorial circuit: Full-Adder
Full Adder: x
yCin
CoutS
Cout =x’.y.Cin + x.y’.Cin + x.y.Cin’ + x.y.Cin =(x’.y + x.y’).Cin + (Cin’+Cin)x.y =( x’.y + x.y’ ). Cin + x.y = (x y).Cin + x.y
X Y Cin S Cout0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1
Truth Table for Full-Adder
It performs the arithmetic addition of three input bits.
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Combinatorial circuit: Full-Adder S =x’.y’.Cin + x’.y. Cin’ + x.y’. Cin’ + x.y. Cin = (x’.y’ + x.y). Cin + (x’.y +x.y’). Cin’ = (x’.y+x.y)’. Cin + (x y). Cin’ = Q.Cin + P.Cin’
If Q were equal to P’ S = P’.Cin + P.Cin’ = P Cin = (x y) Cin
To see if it is so : P = x’.y + x.y’ P’ = (x +y’).(x’ + y) Use De’ Morgan’s
Theorem = x.x’ + x.y + x’.y’ + y.y’ =x.y + x’.y’ = Q
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Combinatorial circuit: Full-Adder circuit
Full-adder circuit :
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Combinatorial circuit: continued .
0
N-1
F1
F2outputsBoolean inputs
The input set has 2n distinct terms. For each output, find F1 = fn1(I0 ....In-1.)
F2 = fn2(I0 ....In-1.)
For implementing the logic functions, the basic issue is of simplification. No specific rules for determining the sequence of steps or the specific theorems that may be used.
Karnaugh Map ----- graphical methodThe number of cells = 2n --- Each cell corresponds to a minterm.
Adjacent cells: differ by only one bit.
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