1 4-bit arithmetic logic unit motorola sn54/74ls181 arora shalini guttal pratibha modgi chaitali...

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4-BIT ARITHMETIC LOGIC UNIT

MOTOROLA SN54/74LS181

Arora ShaliniGuttal PratibhaModgi Chaitali

Shanmugam Ramya

Advisor: Dave ParentDate: 05 -11- 05

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ABSTRACT• The SN54/74LS181 is a 4-bit Arithmetic Logic Unit

(ALU) which can perform all the possible functions.Provides 16 Arithmetic Operations Provides all 16 Logic Operations

• Operating Clock Frequency = 200MHz• Area = (446 X 219)µm• Power = 12.26 mW

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INTRODUCTION Now the current trend in the semiconductor

industry is towards high speed and high density .CMOS Technology provides this to support the market needs.

In the project, we designed 4 bit ALU using static CMOS technology which Introduced us to Cadence Software tools.Taught us design techniques to meet the

specification. Improved our Debugging and testing skill.Enhanced our team spirit.

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Design FlowDesign Flow

Specification

Logic Verification

Transistor sizing

Spice Simulation

Cell based layout

Power and Routing

Post Extraction

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Logic Circuit 4-Bit ALU [ Motorola SN54/74LS181 ]

LONG PATH

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Logic And Arithmetic Function Table

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Logic Verification in NC Verilog

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Long Path Sizing:

Cell WN (µM)WP (µM)

Cg (fF)Tphl (ns)

Targeted

Tphl (ns)

SchematicTphl (ns) Extracted

Inv 3.35 5.55 95.97 0.15 0.15 0.14

AOI33 5.85 8.4 245.73 1 1 0.901

AOI5432Decomposed into

Nand5, nand4, nand3, nand2, inv.

41.53 0.9 0.74 0.68

EX-OR2 3.3 4.35 75.46 0.5 0.49 0.46

Nand4 3.45 2.4 34.8 0.5 0.49 0.45

INV 2.95 4.9 50 0.15 0.15 0.14

Long Path through logic= 3.2 ns

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DFF Sizing:

CellWN (µM)

WP (µM)

Cg (fF)Tphl (ns)

Targeted

Tphl (ns)

SchematicTphl (ns) Extracted

Nand (slave) 3.0 2.55

50 0.7 0.69 0.66

Keeper Mux 1.5 1.5

Driver Mux 5.7 9.45

Master Nand 3.3 5.4

Keeper Mux 1.5 1.5

Driver Mux 4.65 9.3

Total time= Time through logic+ Time through DFF

Total time: 3.2ns+ 1.4ns=4.6ns

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Schematic

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Overall schematic with DFF

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Layout

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DRC and Extraction

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LVS REPORT

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ALU Test Bench for Logic function

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Logic outputInput A3A2A1A0 = 1010B3B2B1B0 = 1001M=1Cn=0

S3S2 S1 S0 = 0000 Logic function¯¯_ =A

F3F2 F1 F0 = 0101

S3S2 S1 S0 = 1111 Logic function =A

F3F2 F1 F0 = 1010

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ALU test bench for Arithmetic function

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Arithmetic function outputInput A3A2A1A0 = 1010B3B2B1B0 = 1001M=0Cn=1

S3S2 S1 S0 = 0000 Arithmetic function =A

F3F2 F1 F0 = 1010

S3S2 S1 S0 = 1111 Arithmetic function =A minus 1

F3F2 F1 F0 = 1001

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Power waveform

Power = 61.34 mW / 5 clocks = 12.26 mW

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Summary

• Our design met all the specification, speed 263 MHz, area (446 X 219)µm, Power 12.26 mW, Power density 12.55 W/cm2

• We verified all 16 logic and arithmetic functions.

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Lesson Learned• Understand the design flow.

• Use cell based design.

• Do DRC and LVS for each cell.

• Have a rough sketch of the overall floor plan before you layout.

• Keep track of timing.

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Thanks to…

• Prof. Dave Parent for all his help.

• Cadence Lab and Humming bird software.

• Classmates for their input.

• Burger King.

• AT&T and Cellular services.