AMITH BHONSLE#318-A, 2nd Main, 2nd floor, Srinidhi residency, Amruthahalli, Bangalore-560092, KarnatakaContact: +91 8861454248; Email: amitb4jobs@gmail.com

OBJECTIVESeeking a challenging and rewarding opportunity with an organization of repute which recognizes and utilizes my true potential in the field of ASIC/FPGA Design & Verification.

PROFILE

Accented with the latest trends and techniques of the field, qualified M. Tech (VLSI Design & Embedded Systems) from Visvesvaraya Technological University, and determined to carve a niche in the industry.

Possess deep knowledge of CMOS Technology, Embedded Systems, Digital Electronics Design, Analog Design, Operating Systems, Microprocessor and Microcontroller.

Possess training and experience in VLSI Design, synthesis and verification, Verilog and VHDL Programming and System Verilog and UVM Hardware verification languages for ASIC’s.

Various communication protocols for high performance SoC’s. Conceptually strong in Assembly level programming languages for system design &

development. Knowledge of scripting language PERL. Expertise in Verilog/VHDL and ASIC/FPGS design flows including simulators, function and

code coverage tools, synthesis, stating timing analysis, power estimation and related tools.

Technical Skill Set Languages : C and C++, Core java, FPGA Design, SoC architecture, System Verilog, UVM. Scripting Language : PERL. Hardware Definition Language : VHDL, VERILOG HDL 2001, 8051 assembly Hardware Verification Languages : System Verilog , Universal verification

methodology[UVM]. Protocols : AMBA AHB, AMBA APB, USB 3.0, UART. Micro controllers/processors : 8051, 8086, ARM and ATMEL. HDL Simulators : Pspice, MATLAB 7.0, Xilinx ISE 14.4, PlanAhead, Vivado 2014.1 and

Mentor Graphics Questa Sim 10.1d.

EDUCATIONAL CREDENTIALS

M. Tech (VLSI Design & Embedded Systems), 2013; Visvesvaraya Technological University, CGPA-7.81/10

B.E (Electrical and Electronics), 2011; PES Institute of Technology, CGPA-5.72/10

12th, 2007; Bellary Independent PU College, 75.83%

10th, 2005; St. Anns High School, Hutti, 82.88%

Projects UndertakenTitlePeriod

Design and Verification of AMBA APB communication protocol.4 months

LocationTechnologiesAbstract

BangaloreVerilog, System Verilog, UVMProject aimed to implement the communication protocol of AMBA APB master and slave in Verilog and verification of the same in UVM. This configurable verification IP can be integrated into any SOC verification environment. The

master VIP interoperability has been tested with a slave VIP.

Title Design of an Arithmetic Logic Unit Based on Reversible Logic Gates.PeriodLocationTechnologiesDescription

6 monthsBangaloreVerilogProject aimed to create design for the Arithmetic Logic Unit (ALU) based on reversible logic gates as logic components is proposed. This design is implemented on Verilog and depicts the dramatic increase in performance of Reversible logic gates over classical gates.

TitlePeriodLocationTechnologies

A Cost-Effective Design of Reversible Programmable Logic Array.4 monthsBangaloreVerilog

Description

Project entailed architecture of cost- effective Reversible PLA (RPLA) which does not lose information and dissipates less heat (Ideally no heat).

TitlePeriodLocationTechnologiesDescription

TitlePeriodLocationTechnologiesDescription

Design of AMBA AHB Interrupt controller. 3 monthsBangaloreVerilogProject entailed designing of the AMBA AHB Interrupt controller protocol address/control, data phases and the modes of transactions.

Physical Layer implementation of USB 3.06 monthsBangaloreVerilogProject entailed design of the working of Physical layer of USB 3.0. It implements the transfer of scrambled and encoded data in the DC balanced values from the transmitter and unscrambling and decoding in the receiver end.

TOTAL WORK EXPERIENCE1. Job Title: VLSI Design Intern.

Company: GRID INDIA IT INNOVATIONS, Bangalore.Duration: 6 months internship.

2. Job Title: VLSI Design Engineer.Company: GRID INDIA IT INNOVATIONS, Bangalore.Duration: Feb 2014 to July 2014.Responsibilities: Development of projects, RTL coding, simulating and Synthesizing,

Verification of RTL codes, Conduct corporate training sessions and seminars.Responsible for providing technical leadership to medium size enterprise projects.

Seminars and Project Paper Presented Bio-Technology applied in Electronics [NEMS] Grid Power Storage CMOS Low Power Nora Circuits Presented a paper on Vectored interrupt controller with AHB slave interface. Presented a paper on physical layer implementation of USB 3.0

Date of Birth: 2nd July, 1989Languages Known: English, Hindi, Marathi, Telugu and KannadaReference: Can be provided on request