Division of Electronics and Informatics, Gunma University

Semiconductor Technology Academic Research Center (STARC) Hikari Science

Intro

du

ctio

n

Pro

po

se

d C

ircu

it

Exp

erim

en

t

Summary

Analog FPGA Implementation of Multi-bit Delta-Sigma TDC Takuya Arafune, Takeshi Chujo, Daiki Hirabayashi, Masanobu Tsuji , Koshi Sato, Haruo Kobayashi

Research Motivation Research Objective Our Approach

Single-bit ΔΣ TDC Multi-bit ΔΣ TDC DWA Algorithm

[1] S. Uemori, M. Ishii, H. Kobayashi, et. al.,

“Multi-bit Sigma-Delta TDC Architecture with Improved Linearity,”

J. of Electronic Testing, Springer, vo. 29, no. 6, pp.879-892 (Dec. 2013).

[2] Y. Osawa, D. Hirabayashi, N. Harigai , H. Kobayashi, et. al.,

“Phase Noise Measurement Techniques Using Delta-Sigma TDC”,

IMS3TW'14, Porto Alegre, Brazil (Sept.2014).

Multi-bit ΔΣTDC Design Analog FPGA Implementation

Measurement results INL

AMDE Poster No.99

facing difficulties

due to reduced supply voltage

Voltage Resolution

Voltage

CMOS

Scaling

Time Resolution

Time

CMOS

ScalingTime

Voltage

becoming superior

Time-to-Digital Converter (TDC) measures

time interval between two signal transitions, into digital signal.

(2) Analog circuit design in nano-CMOS SoC

(1)High speed and high frequency signal testing circuit

● Timing testing of data and clock in DDR memory

● Phase noise testing Timing difference

ΔT

Development of timing measurement & testing circuit

- short measurement time

- fine time resolution

- high linearity

- digital output

ΔT ΔT ΔT

CLK1

CLK2

Small

CircuitryDout

CLK1

CLK2

Multi-bit ΔΣ TDC with DWA Algorithm

● ΔΣ TDC

Fine time resolution

Small circuit

Digital output

● Multi-bit

Short measurement time

● Data Weighted Averaging (DWA)

Algorithm

High linearity

Advantages

● Fine time resolution

● High linearity

● Simple circuit

Problem

● Long measurement time

MUX

t

MUX

Dout

Delay Line

CLK1

CLK2

Phase

De

tecto

r

Inte

gra

tor

+

−

INTout < 0 : Dout = 0

INTout > 0 : Dout = 1

CLKin+CLK1a

CLK2a

0MUX

1

0

1

0

1

CLKin-

Time resolution: 2τ / N

N: Number of output data Dout

Input timing range: – τ< ΔT < τ

1

MUX

tMUX

MUX

Flash

ADC

MUX

tMUX

MUX

MUX

tMUX

MUX

Dout

Delay Line 1 Delay Line 2 Delay Line 2n-1

CLK1

CLK2

2n-1

Phase

Detecto

r

Integrator

2n-1DWA

1 1 1

Advantage

Short measurement time

by 1/2n

Problem

Nonlinearity

due to delay mismatches

Solution DWA algorithm

+Δτ1 +Δτ2 +Δτ7

R=1kΩ

C=0.1μF

Vdd=5V

Ic=720μA

Phase detector

Integrator

Differential ADC

Digital to Time Converter

MUX

MUX

MUX

MUX

MUX

MUX

MUX

MUX

MUX

Delay 1 Delay 2 Delay 7

CLK1

CLK2

111 DWA

logic

CLK1`

CLK2`

7

ττ τ

PSoC5LP(Programmable System-on-Chip, Cypress Semiconductor）External board （Delay line, Differential ADC ）

Analog FPGA (PSoC)External board

Without DWA With DWA

very linear

-0.022

0.005

Without DWA

With DWA

DWA improves TDC linearity.

● We have implemented a multi-bit ΔΣ TDC

employing DWA algorithm with analog FPGA .

● We have confirmed its operation,

and DWA effectiveness.

● It can be timing testing BOST

- fine time resolution

- short testing time

- high linearity

- small circuit.

References

Delay mismatch time-average

by equal usage of all delays.

DWA Circuit Implementation

0 1 2 3 4 5 6 74322571548

Time

)Z1/(1)z(H 1

Inpu

t of

DAC

Delay Elements

Inp

ut to

De

lay C

ells

(F

lash

AD

C O

utp

ut)