MAIN PROGRAM

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ALU4b isport(A,B:in std_logic_vector(3 downto 0);

Op:in std_logic_vector(2 downto 0);Y0,Y1:out std_logic_vector(3 downto 0));

end ALU4b;

architecture Structural of ALU4b iscomponent PA

port(a,b:in std_logic_vector(3 downto 0);cin:in std_logic;cout:out std_logic;sum:out std_logic_vector(3 downto 0));

end component;

component sub4port(a,b:in std_logic_vector(3 downto 0);d:out std_logic_vector(3 downto 0);bo:out std_logic);

end component;

component logic4port(a,b:in std_logic_vector(3 downto 0);yand,yor,yxor,abar,bbar:out std_logic_vector(3 downto 0));

end component;

component mul4port(A,B:in std_logic_vector(3 downto 0);Y:out std_logic_vector(7 downto 0));

end component;

component supermuxport(yadd,ysub,yand,yor,yxor,abar,bbar:in

std_logic_vector(3 downto 0);ymul:in std_logic_vector(7 downto 0);sl:in std_logic_vector(2 downto 0);cy,br:in std_logic;yl,yh:out std_logic_vector(3 downto 0));

end component;

signal yadd,ysub,yand,yor,yxor,abar,bbar:std_logic_vector(3 downto 0);

signal ymul:std_logic_vector(7 downto 0);signal cy,br:std_logic;

beginl1:PA port map(A,B,'0',cy,yadd);l2:sub4 port map(A,B,ysub,br);l3:mul4 port map(A,B,ymul);l4:logic4 port map(A,B,yand,yor,yxor,abar,bbar);l5:supermux port map(yadd,ysub,yand,yor,yxor,abar,bbar,ymul,Op,cy,br,Y0,Y1);

end Structural;

COMPONENTS

1. PA (Behavioral Parallel Adder)2. SUB4 (Behavioral 4-bit subtractor)3. Logic4 (Behavioral design to calculate AND, OR, Ex-OR and NOT)4. Mul4 (Structural 4 bit Multiplier): sub-components are

a. add4 (4-bit parallel adder)b. and4 (4-bit parallel AND gate)

5. supermux (Multiplexer-type device to direct particular output to port according to opcode)

PARALLEL ADDER:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity PA isport(a,b:in std_logic_vector(3 downto 0);

cin:in std_logic;cout:out std_logic;sum:out std_logic_vector(3 downto 0));

end PA;

architecture Behavioral of PA is

signal c:std_logic_vector(1 to 3);

beginsum(0)<=a(0) xor b(0) xor cin;c(1)<=(a(0) and b(0)) or (a(0) and cin) or (b(0) and cin);sum(1)<=a(1) xor b(1) xor c(1);c(2)<=(a(1) and b(1)) or (a(1) and c(1)) or (b(1) and c(1));

sum(2)<=a(2) xor b(2) xor c(2);c(3)<=(a(2) and b(2)) or (a(2) and c(2)) or (b(2) and c(2));sum(3)<=a(3) xor b(3) xor c(3);cout<=(a(3) and b(3)) or (a(3) and c(3)) or (b(3) and c(3));

end Behavioral;

sub4

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sub4 isport(a,b:in std_logic_vector(3 downto 0);d:out std_logic_vector(3 downto 0);bo:out std_logic);

end sub4;

architecture Behavioral of sub4 issignal abar,s,sbar:std_logic_vector(3 downto 0);signal br1,br2,br3:std_logic;begin

abar<=not a;s<=a xor b;sbar<=not s;d(0)<=s(0);br1<=abar(0) and b(0);d(1)<=s(1) xor br1;br2<=(abar(1) and b(1)) or (sbar(1) and br1);d(2)<=s(2) xor br2;br3<=(abar(2) and b(2)) or (sbar(2) and br2);d(3)<=s(3) xor br3;bo<=(abar(3) and b(3)) or (sbar(3) and br3);

end Behavioral;

Logic4

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity logic4 isport(a,b:in std_logic_vector(3 downto 0);

yand,yor,yxor,abar,bbar:out std_logic_vector(3 downto 0));end logic4;

architecture Behavioral of logic4 issignal i:natural;beginprocess(a,b)beginfor i in 0 to 3 loop

yand(i)<=a(i) and b(i);yor(i)<=a(i) or b(i);yxor(i)<=a(i) xor b(i);abar(i)<=not a(i);bbar(i)<=not b(i);

end loop;end process;end Behavioral;

mul4

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mul4 isport(A,B:in std_logic_vector(3 downto 0);Y:out std_logic_vector(7 downto 0));

end mul4;

architecture Structural of mul4 iscomponent add4

port(a3,a2,a1,a0,b3,b2,b1,b0,cin:in std_logic;s3,s2,s1,s0,co:out std_logic);

end component;component and4s

port(a3,a2,a1,a0,b3,b2,b1,b0:in std_logic;y3,y2,y1,y0:out std_logic);

end component;signal m3,m2,m1,m0,f1,f2:std_logic_vector(3 downto 0);

beginl1:and4s port map (B(0),B(0),B(0),B(0),A(3),A(2),A(1),A(0),m0(3),m0(2),m0(1),Y(0));

l2:and4s port map (B(1),B(1),B(1),B(1),A(3),A(2),A(1),A(0),m1(3),m1(2),m1(1),m1(0));l3:and4s port map (B(2),B(2),B(2),B(2),A(3),A(2),A(1),A(0),m2(3),m2(2),m2(1),m2(0));l4:and4s port map (B(3),B(3),B(3),B(3),A(3),A(2),A(1),A(0),m3(3),m3(2),m3(1),m3(0));l5:add4 port map ('0',m0(3),m0(2),m0(1),m1(3),m1(2),m1(1),m1(0),'0',f1(2),f1(1),f1(0),Y(1),f1(3));l6:add4 port map (f1(3),f1(2),f1(1),f1(0),m2(3),m2(2),m2(1),m2(0),'0',f2(2),f2(1),f2(0),Y(2),f2(3));l7:add4 port map (f2(3),f2(2),f2(1),f2(0),m3(3),m3(2),m3(1),m3(0),'0',Y(6),Y(5),Y(4),Y(3),Y(7));

end Structural;

add4

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity add4 isport(a3,a2,a1,a0,b3,b2,b1,b0,cin:in std_logic;

s3,s2,s1,s0,co:out std_logic);end add4;

architecture Behavioral of add4 issignal c,c1:std_logic_vector(0 to 3);beginc(0)<=(a0 and b0) or ((a0 or b0) and cin);c(1)<=(a1 and b1) or ((a1 or b1) and c(0));c(2)<=(a2 and b2) or ((a2 or b2) and c(1));c(3)<=(a3 and b3) or ((a3 or b3) and c(2));c1(0)<=not c(0);c1(1)<=not c(1);c1(2)<=not c(2);c1(3)<=not c(3);s0<=(c1(0)and(a0 or b0 or cin)) or (a0 and b0 and cin);s1<=(c1(1)and(a1 or b1 or c(0))) or (a1 and b1 and c(0));s2<=(c1(2)and(a2 or b2 or c(1))) or (a2 and b2 and c(1));

s3<=(c1(3)and(a3 or b3 or c(2))) or (a3 and b3 and c(2));co<=c(3);

end Behavioral;

and4

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity and4s isport(a3,a2,a1,a0,b3,b2,b1,b0:in std_logic;y3,y2,y1,y0:out std_logic);

end and4s;

architecture Behavioral of and4 is

beginy3<=a3 and b3;y2<=a2 and b2;y1<=a1 and b1;y0<=a0 and b0;

end Behavioral;

Supermux

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity supermux is

port(yadd,ysub,yand,yor,yxor,abar,bbar:in std_logic_vector(3 downto 0);

ymul:in std_logic_vector(7 downto 0);

sl:in std_logic_vector(2 downto 0);

cy,br:in std_logic;

yl,yh:out std_logic_vector(3 downto 0));

end supermux;

architecture Behavioral of supermux is

begin

process(yadd,ysub,yand,yor,yxor,abar,bbar,ymul,sl,cy,br)

begin

yh<="0000";

if sl="000" then

yl<=yadd;

yh(0)<=cy;

elsif sl="001" then

yl<=ysub;

yh(0)<=br;

elsif sl="010" then

yl<=ymul(3 downto 0);

yh<=ymul(7 downto 4);

elsif sl="011" then

yl<=yand;

elsif sl="100" then

yl<=yor;

elsif sl="101" then

yl<=yxor;

elsif sl="110" then

yl<=abar;

elsif sl="111" then

yl<=bbar;

end if;

end process;

end Behavioral;

RTL Schematics:

1. Entity

2. Circuit

3. Multiplier Block

4. Super-mux

Simulated Testbench-1 (for LOGICAL Operation)

Simulated Testbench-2 (for ARITHMETIC Operation)