altium schematic translator - capture

14
Altium Schematic Translator - Capture April 2018

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Page 1: Altium Schematic Translator - Capture

Altium Schematic Translator - Capture

April 2018

Page 2: Altium Schematic Translator - Capture

2 Cadence Design Systems, Inc. , Cadence Confidential

Altium Schematic Translator – Capture

Translates Altium schematics to OrCAD Capture

Page 3: Altium Schematic Translator - Capture

3 Cadence Design Systems, Inc. , Cadence Confidential

Prerequisites: ASCII Schematic

Schematic has to be saved to ASCII format within Altium.

This will replace the original binary file by its ASCII

equivalent. Location and file extension is the same.

Page 4: Altium Schematic Translator - Capture

4 Cadence Design Systems, Inc. , Cadence Confidential

Prerequisites: Imperial Unit System

Due to the fact Capture supports only Imperial Units AND

finest resolution of 10 mils ONLY Altium schematic elements

which NOT exceeds this 10 mil finest resolution restriction will

be correctly mapped to Capture.

In Order to avoid false Graphical and

Logical representation after translation it

is highly recommended to setup Altium

Unit System accordingly bevor starting

the translation:

Cadence recommends for pin spacing

a grid of 100 mil at least 50 mil space.

Other graphic elements have to stay

in the limits of 10 mil resolution.

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5 Cadence Design Systems, Inc. , Cadence Confidential

Prerequisites: Project structure

Schematics can be translated only if they are embedded in a PCB project (*.PrjPCB) which manages the design

documents needed to manufacture a PCB design.

Furthermore a valid structure file (*.PrjPCBStructure) is

needed. It will be generated after compiling the PCB project and references the individual schematic pages (*.SchDoc).

If the project file does not exist:

− Select File » New » Project from the menus, the New Project dialog will

open. From the list of available project types, choose PCB Project

− Add the schematic documents *.SchDoc to the project

− Compile the project (e.g. RMB » Compile PCB Project)

− For more documentation about setting up PCB projects refer to Altium

documentation.

Page 6: Altium Schematic Translator - Capture

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Project structure example

Each schematic page *.SchDoc is saved in ASCII format.

Project file *.PrjPCB acts as project master.

File *.PrjPCBStructure has references to schematic.

pages (relative path).

File *.PcbDoc is only needed when PCB has to be

translated.

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7 Cadence Design Systems, Inc. , Cadence Confidential

Running the translator

Launch Altium-Capture translator

− Select Altium project file .prjPCB

− Specify output directory for OrCAD project

− Translate

Once finished open the project and check schematic for

translation errors

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8 Cadence Design Systems, Inc. , Cadence Confidential

Running the translator cont.

Altium-Capture translator support all three

Design Modes

− Single Page Design: instead .prjPCB select

.SchDoc File.

− Multipage Flat Design: Now Translator will

recognize a flat schematic structure with or

without a structure file given.

− Hierarchical Design: Altium Schematic with this

kind of design methodology will need a structure

file in order to figure out the root drawing.

Page 9: Altium Schematic Translator - Capture

9 Cadence Design Systems, Inc. , Cadence Confidential

Synchronize with PCB

If you plan to translate a complete project including PCB

− Run Tools – Create Netlist and specify an empty database

− Open this database with PCB Editor

− Within PCB Editor run Altium-PCB translator and navigate again to .prjPCB file. The translator will retain netlist and device logic and

translate only the remaining data in order to complete the board.

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10 Cadence Design Systems, Inc. , Cadence Confidential

Notes:

In order to get right design hierarchy structure in translated designs, it is mandatory to provide file

along with .

Otherwise translator couldn’t figure out which is the top / root

drawing in cadence project. In case structure file is not

present, set the root drawing in the translated schematic

before creating a netlist.

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Limitations:

1. Harness is currently NOT supported. Implementation will

follow in one of the next releases.

2. A block references several schematic documents. We have

never seen this before. Short term solution: add additional

block.

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Limitations:

1. ASCII does not contain full information about used frame

sizes.

Only Custom style information will be included into the ASCII file for frame sizes.

Press „Use Custom style“ checkbox to update frame size

information.

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13 Cadence Design Systems, Inc. , Cadence Confidential

Limitations:

1. ASCII does not contain full information about used frame

sizes.

Custom and User selected Default Pages Sizes are alternative

Frame Size setting methods

Selected Frame Size shell be valid for all Pages of a Design

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14 Cadence Design Systems, Inc. , Cadence Confidential