1528 IEEE ELECTRON DEVICE LETTERS, VOL. 41, NO. 10, OCTOBER 2020

Alternating Current-Based Technique forSeparate Extraction of Parasitic Resistances in

MISFETs With or Without the Body ContactHaesung Kim, Han Bin Yoo, Jin-Tae Yu, Ji Hee Ryu, Sung-Jin Choi ,

Dae Hwan Kim , Senior Member, IEEE, and Dong Myong Kim , Member, IEEE

Abstract— We report a novel technique for separating theparasitic source (RS) and drain (RD) resistances in MISFETsusing the open drain and the open source configurationsbased on an alternating-current(AC) signal. We conductedimpedance analysis for the AC signal in the open drain forRS and the open source configuration for RD. The proposedtechnique is independent of the I-V equation of MISFETswith various influencing parameters for separate extractionof RS and RD through the physics-based equivalent circuitof MISFETs. So the proposed technique is applicable toevery single device as long as the device is an insulated gateMISFET structure, regardless of the presence or absenceof the body terminal. This technique is applied to amor-phous oxide semiconductor thin-film transistors with thegate length =10μm without the body contact. As a result,parasitic resistances were separately extracted to be RS =2.1 k�, RD = 1.7 k� for W = 600μm, RS = RD =1.1 k�for W = 1000μm, and RS = RD = 0.6 k� for W = 2000μmindependent of gate bias.

Index Terms— Parasitic resistance, separate extraction,alternating current, source resistance, drain resistance,body contact, MISFET, MOSFET, TFT.

I. INTRODUCTION

SEPARATE extraction of parasitic resistances becomesincreasingly important for device performance and

integrity as devices are scaled down [1], [2]. Parasiticresistances are inevitable results of the limited electricalconductivity (σ) of materials, structures, and their lay-out of the metal-insulator-semiconductor field effect transis-tors(MISFETs) with or without the body contact. The parasiticresistances of the source (RS) and drain (RD) cause thedegradation of a device’s operating parameters including the

Manuscript received July 31, 2020; revised August 24, 2020; acceptedAugust 26, 2020. Date of publication August 31, 2020; date of currentversion September 25, 2020. This work was supported by the KoreaFoundation for Advancement of Science and Creativity (KOFAC), KoreanGovernment, under Grant SBJ000032307, Grant 2017R1A2B4007820,and Grant 2016R1A5A1012966. The review of this letter was arranged byEditor L. K. Nanver. (Haesung Kim and Han Bin Yoo contributed equallyto this work.) (Corresponding author: Dong Myong Kim.)

The authors are with the School of Electrical Engineering, KookminUniversity, Seoul 02707, South Korea (e-mail: dmkim@kookmin.ac.kr).

Color versions of one or more of the figures in this letter are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/LED.2020.3020405

Fig. 1. (a) Schematic and equivalent circuit of MISFETs and opendrain measurement configuration. (b) Schematic and equivalent circuit ofMISFETs and open drain configuration at V G � V T. (c) Equivalent circuitof MISFETs with RS and RD at open drain configuration. (d) ACODMmodel for the open drain configuration.

transconductance (gm), the current gain cut-off frequency ( fT),and the maximum frequency of oscillation ( fmax) becausethey cause voltage drops during the operation of devices andintegrated circuits [3]–[5]. In addition, RS and RD, whetherintended or not, can be asymmetrical caused by the electricalstress, the fabrication process, and/or the layout of the device[6], [7]. Therefore, it is necessary to separate the parasiticresistances in the source and the drain to properly characterizethe fabrication process, the layout defects, and the electricalstress effect on the source and the drain in MISFETs.

In addition, despite various previously reported studies,they require complex processes, multiple devices, or bodyterminals in MISFET with an insulated gate structure [8]–[19].Therefore, a more advanced method for separate extraction ofparasitic resistances is needed to overcome these restrictions.

In this work, we propose an alternating current-based opendrain method (ACODM) for separate extraction of the parasiticsource and drain resistances in single MISFETs with and with-out the body contact. In the proposed ACODM, we applied

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KIM et al.: AC-BASED TECHNIQUE FOR SEPARATE EXTRACTION OF PARASITIC RESISTANCES IN MISFETs 1529

the distributed-element model [20] to insulated gate MISFETsas shown in Fig. 1. The analysis was carried out with a gatevoltage (VG) sufficiently greater than the threshold voltage(VT). The ACODM model was created by applying an AC sig-nal to the gate with the open drain/open source configuration[21]. In this model, the impedance analysis was performed inboth the open drain and open source configurations. Throughthis impedance analysis, we successfully conducted separateextraction of RS and RD in MISFETs both with and withoutthe body contact. This allows the proposed technique to beavailable for both FinFETs and thin film transistors (TFTs)without the body contact as well as conventional MOSFETswith the body contact even with the insulated gate structure.

II. AC-BASED OPEN DRAIN METHOD

A schematic of MISFET with its distributed-element modelincluding the parasitic source and drain resistances is shown inFig. 1(a). As the VG increases sufficiently above the thresholdvoltage (VT), the electrical conductivity (σch) of the channelincreases due to fully inverted channel carriers. This increasein σch causes a decrease in the gate bias-dependent channelresistance (Rch(VG)). Therefore, it can be assumed that theeffect of the channel resistance can be ignored (Rch ∼= 0) underhigh gate bias(VG � VT). Under VG � VT, the substratecapacitance (CS) will have a much greater value than theoxide capacitance (Cox) because of the large amount ofthe conductive substrate charge (QS). Therefore, the gatecapacitance (Cg) becomes approximately equal to Cox (Cg ≈Cox). A schematic and equivalent circuit of the MISFETunder characterization under VG � VT is shown in Fig. 1(b)and (c). The parameter Vm, which is the measured voltagebetween the drain and the source terminals through the voltagemeasurement unit, can be expressed as

Vm = VM + υm = Vd + Vs + Vch,eff(VG) (1)

Vd = VD + υd = Id RD = (ID + id) RD (2)

Vs = VS + υs = Is RS = (ID + id) RS (3)

Vch,eff = Ich Rch(VG) = (IDC + ich) Rch(VG) ∝ (VG − VT)−1

(4)

where Vch,eff is the gate bias-dependent effective voltageacross the channel with a negligible channel resistance(Rch) under VG � VT, Vd is the voltage drop(Vd =VD(DC)+υd(AC)) across the parasitic drain resistance (RD),and Vs is the voltage drop (Vs = VS(DC)+υs(AC)) across theparasitic source resistance (RS) in MISFETs under character-ization. However, Vch,eff can be negligible due to the smallchannel resistance at VG � VT. We also note that no draincurrent (id) flows for the open drain configuration. Therefore,there is no voltage drop across the parasitic drain resistance(Vd = 0). We also note that there is no voltage drop across theparasitic source resistance in the open the source configuration(Vs = 0). Therefore, the measured voltage(Vm) in each openconfiguration can be re-expressed as

Vm∣∣ ODVG�VT

= Vd + Vs + Vch,eff∣∣ ODVG�VT

∼= Vs = υs = is RS

(5)

Fig. 2. (a) Schematic of the measurement setup for a-IGZO TFTs withthe voltage measurement unit(VMU) at the open drain configuration forthe ACODM. (b) output curves. (c) transfer curves (measured V T = 1.2V) (d) C-V characteristics of a-IGZO TFTs (measured Cox = 1.5 pF).

Vm∣∣ OSVG�VT

= Vd + Vs + Vch,eff∣∣ OSVG�VT

∼= Vd = υd = id RD.

(6)

The equivalent circuit for the open drain is shown in Fig. 1(d),and we define this as the ACODM model. In this model,the voltage distribution ratio (rOD|OS) of the AC signal withrespect to the gate(υin) can be defined as

υm

υin

∣∣∣∣OD|OS

≡ rOD|OS = RS| D{RS|D + ( jφCox)

−1} (7)

with φ as the angular frequency of the applied AC signal(υin). If rOD is calculated as a magnitude, it can be expressedas follows:∣∣υm,OD

∣∣∣∣υin∣∣ =

∣∣υd∣∣∣∣υin∣∣ = ∣∣rOD

∣∣ =√(

rOD∣∣Re

)2 + (rOD

∣∣Im

)2

= φCox RS√1 + (φCox RS)2

(8)

where |υm| and |υin| are the peak-to-peak voltages of υm andυin, and rOD|Re and rOD|Im are the real and imaginary partsof rOD, respectively. By rearranging Eq. (4) to extract theparasitic source and drain resistances in MISFETs with andwithout the body contact, we obtain following result for theACODM√∣∣rOD

∣∣2/(

1 − ∣∣rOD∣∣2

)= Cox RSφ ≡ αOD : open drain (9)

Finally, through the ACODM, RS and RD can be separatelyobtained from the slope of the αOD and αOS curves as afunction of the angular frequency (φ) in Eqs. (5-a) and (5-b) through

RS = 1

Cox

dαOD

dφ: open drain configuration (10)

RD = 1

Cox

dαOS

dφ: open source configuration. (11)

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1530 IEEE ELECTRON DEVICE LETTERS, VOL. 41, NO. 10, OCTOBER 2020

TABLE IEXTRACTED PARASITIC SOURCE(RS) AND DRAIN(RD) RESISTANCES

BY VOLTAGE VARIATION IN A-IGZO TFTS WITH W = 600, 1000 AND

2000 μm AND L = 10 μm

Fig. 3. (a) V G − |υm| graph of open drain configuration in a-IGZOTFT with W/L = 1000 μm /10 μm. (b) V G − |υm| graph of open sourceconfiguration in a-IGZO TFT with W/L = 1000 μm /10 μm.

III. EXPERIMENTAL RESULTS AND DISCUSSION

A schematic of the amorphous indium–gallium–zinc–oxide(a-IGZO) TFTs(no body contact) with the oxide thicknesstox = 200 nm used for experimental verification is shownin Fig. 2(a). We used a-IGZO TFTs with the gate lengthL =10 μm and the gate width W = 600, 1000, 2000 μm.The experimentally obtained I–V characteristics are shown inFig. 2(b) and (c), and the C–V characteristics are shown inFig. 2(d).

The threshold voltage(VT) extracted using the I–V charac-teristics was 1.2 V, and the oxide capacitance(Cox) extractedusing the C–V characteristics was 1.5 pF. The VG above VTwas applied to the gate terminal to sufficiently reduce thechannel resistance(Rch). To verify the effect of the channelresistance, we took measurements using the VG in the rangeabove VT. To measure Vm in the open drain/source configu-ration, the drain or source must be virtually open. Therefore,in the open drain configuration, a high external resistance wasconnected to the drain terminal to guarantee a virtual openstate. In the open source configuration, as in the open drainconfiguration, a high resistance was connected to the sourceterminal to guarantee a virtual open state.

The experimental results of |Vm| for the separate extractionof RS and RD through the ACODM are shown in Fig. 3(a) and(b). These results show that VPP is constant despite the increasein the VG with sufficiently above the VT. This is because VGis so large that the channel resistance is sufficiently reduced tobe negligible, thereby eliminating the voltage drop along thechannel resistance(Rch).

Fig. 4. (a) f -αOD graph of open drain configuration in a-IGZO TFT withW/L = 1000 μm /10 μm. (b) f -αOS graph of open source configurationin a-IGZO TFT with W/L = 1000 μm /10 μm.

αOD and αOS as a function of φ extracted through themeasured values of VPP and Eqs. (5-a) and (5-b) are shownin Fig. 4(a) and (b). Using these φ − αOD and αOS graphsand Eqs. (6-a) and (6-b), the VG-independent parasitic sourceand drain resistances were extracted to be RS = 2.1 k� andRD = 1.7 k�, for W = 600 μm, RS = RD = 1.1 k�, forW = 1000 μm, RS = RD = 0.6 k� for W = 2000 μm underlarge the gate voltage. The extracted parasitic source and drainresistances through the ACODM are shown in Table I.

IV. CONCLUSION

We proposed the ACODM as a simple technique for sep-arate extraction of parasitic source and drain resistances ininsulated-gate MISFETs independent of the body contact. Theproposed ACODM was applied to a-IGZO TFTs with W/L =600 μm/10 μm, 1000 μm/10 μm and 2000 μm/10 μm toextract the parasitic resistances. We confirmed the ACODMmodel for the VG-dependence of the parasitic resistances inthe a-IGZO TFTs. As a result, RS = 2.1 k� and RD =1.7 k� for W = 600 μm, RS = RD = 1.1 k� for W =1000 μm, RS = RD = 0.6 k� for W = 2000 μm wereextracted without the body contact under a high gate bias.This confirmed that the channel resistance(Rch) was reducedto such a degree that it could be ignored. We expect thatthe proposed ACODM would be useful and advanced wayto separate the parasitic resistances of the source and thedrain in insulated-gate MISFETs, regardless of the presence orabsence of the body contact and while excluding the channelresistance. This also allows a useful characterization of eachsingle insulated gate FETs for the process-, structure-, andstress-induced asymmetry effects.

REFERENCES

[1] B. Davari, R. H. Dennard, and G. G. Shahidi, “CMOS scaling for highperformance and low power—The next ten years,” Proc. IEEE, vol. 83,no. 4, pp. 595–606, Apr. 1995, doi: 10.1109/5.371968.

[2] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices.Cambridge, U.K.: Cambridge Univ. Press, 2009.

[3] K. K. Ng and W. T. Lynch, “The impact of intrinsic series resistanceon MOSFET scaling,” IEEE Trans. Electron Devices, vol. ED-34, no. 3,pp. 503–511, Mar. 1987, doi: 10.1109/T-ED.1987.22956.

[4] H. Shichijo, “A re-examination of practical performance limits of scaledn-channel and �-channel MOS devices for VLSI,” Solid-State Electron.,vol. 26, no. 10, pp. 969–986, 1983, doi: 10.1016/0038-1101(83)90072-2.

[5] J.-P. Raskin, R. Gillon, J. Chen, D. Vanhoenacker-Janvier, andJ.-P. Colinge, “Accurate SOI MOSFET characterization at microwavefrequencies for device performance optimization and analog modeling,”IEEE Trans. Electron Devices, vol. 45, no. 5, pp. 1017–1025, May 1998,doi: 10.1109/16.669514.

Authorized licensed use limited to: Kookmin University. Downloaded on September 28,2020 at 06:54:01 UTC from IEEE Xplore. Restrictions apply.

KIM et al.: AC-BASED TECHNIQUE FOR SEPARATE EXTRACTION OF PARASITIC RESISTANCES IN MISFETs 1531

[6] R. J. Baker, CMOS Circuit Design, Layout and Simulation. Hoboken,NJ, USA: Wiley, 2005.

[7] T. Kuroda, K. Suzuki, S. Mita, T. Fujita, F. Yamane, F. Sano, A. Chiba,Y. Watanabe, K. Matsuda, T. Maeda, T. Sakurai, and T. Furuyama,“Variable supply-voltage scheme for low-power high-speed CMOSdigital design,” IEEE J. Solid-State Circuits, vol. 33, no. 3, pp. 454–462,Mar. 1998, doi: 10.1109/4.661211.

[8] A. Ortiz-Conde, A. Sucre-González, F. Zárate-Rincón, R. Torres-Torres,R. S. Murphy-Arteaga, J. J. Liou, and F. J. García-Sánchez, “A reviewof DC extraction methods for MOSFET series resistance and mobilitydegradation model parameters,” Microelectron. Rel., vol. 69, pp. 1–16,Feb. 2017, doi: 10.1016/j.microrel.2016.12.016.

[9] J. P. Campbell, K. P. Cheung, J. S. Suehle, and A. Oates, “A simpleseries resistance extraction methodology for advanced CMOS devices,”IEEE Electron Device Lett., vol. 32, no. 8, pp. 1047–1049, Aug. 2011,doi: 10.1109/LED.2011.2158183.

[10] J. Kim, H. Yoo, H. Lee, S. K. Kim, S. Choi, S.-J. Choi, D. H. Kim, andD. M. Kim, “Comprehensive separate extraction of parasitic resistancesin MOSFETs considering the gate bias-dependence and the asymmetricoverlap length,” Microelectron. Rel., vol. 85, pp. 66–70, Jun. 2018, doi:10.1016/j.microrel.2018.04.011.

[11] H. Bae, S. C. Baek, S. Lee, J. Jang, J. S. Shin, D. Yun, H. Kim,D. H. Kim, and D. M. Kim, “Separate extraction of source, drain,and substrate resistances in MOSFETs with parasitic junction currentmethod,” IEEE Electron Device Lett., pp. 1190–1192, Nov. 2010, doi:10.1109/LED.2010.2066257.

[12] S. Jun, H. Bae, H. Kim, J. Lee, S.-J. Choi, D. H. Kim, and D. M. Kim,“Dual-sweep combinational transconductance technique for separateextraction of parasitic resistances in amorphous thin-film transistors,”IEEE Electron Device Lett., vol. 36, no. 2, pp. 144–146, Feb. 2015, doi:10.1109/LED.2014.2384504.

[13] H. Bae, J. Jang, J. S. Shin, D. Yun, J. Lee, T. W. Kim,D. H. Kim, and D. M. Kim, “Modeling and separate extractionof gate-bias- and channel-length-dependent intrinsic and extrinsicsource–drain resistances in MOSFETs,” IEEE Electron Device Lett.,vol. 32, no. 6, pp. 722–724, Jun. 2011, doi: 10.1109/LED.2011.2131116.

[14] S.-C. Baek, H.-Y. Bae, D.-H. Kim, and D.-M. Kim, “Avalanche hotsource method for separated extraction of parasitic source and drainresistances in single metal-oxide-semiconductor field effect transistors,”J. Semicond. Technol. Sci., vol. 12, no. 1, pp. 46–52, Mar. 2012, doi:10.5573/JSTS.2012.12.1.46.

[15] R. Rodriguez-Davila, A. Ortiz-Conde, C. Avila-Avendano, Z. Shamsi,and M. A. Quevedo-Lopez, “On the DC extraction of the asym-metric parasitic source and drain resistances for MOSFETs,”Solid-State Electron., vol. 164, Feb. 2020, Art. no. 107700, doi:10.1016/j.sse.2019.107700.

[16] A. Ortiz-Conde, W. Wong, J. J. Liou, and F. J. G. Sánchez, “Simplemethod for extracting the difference between the drain and sourceseries resistances in MOSFETs,” Electron. Lett., vol. 30, no. 12,pp. 1013–1015, Jun. 1994, doi: 10.1049/el:19940681.

[17] A. Ortiz-Conde, F. J. G. Sánchez, and J. J. Liou, “An improved methodfor extracting the difference between drain and source resistancesin MOSFETs,” Solid-State Electron., vol. 39, no. 3, pp. 419–421,Mar. 1996, doi: 10.1016/0038-1101(95)00072-0.

[18] A. Ortiz-Conde, J. J. Liou, R. Narayanan, and F. J. G. Sánchez, “Deter-mination of physical mechanisms contributing to the difference betweendrain and source resistances in short-channel MOSFETs,” Solid-StateElectron., vol. 39, no. 2, pp. 211–215, Feb. 1996, doi: 10.1016/0038-1101(95)00125-5.

[19] A. Raychaudhuri, M. J. Deen, M. I. H. King, and J. Kolk, “Findingthe asymmetric parasitic source and drain resistance from the a.c.conductances of a single MOS transistor,” Solid-State Electron., vol. 39,no. 6, pp. 909–913, Jun. 1996, doi: 10.1016/0038-1101(95)00269-3.

[20] H. Choi, J. Lee, H. Bae, S.-J. Choi, D. H. Kim, and D. M. Kim, “Bias-dependent effective channel length for extraction of subgap DOS bycapacitance–voltage characteristics in amorphous semiconductor TFTs,”IEEE Trans. Electron Devices, vol. 62, no. 8, pp. 2689–2694, Aug. 2015,doi: 10.1109/TED.2015.2443492.

[21] J. Kim, H. Lee, S. K. Kim, J. Kim, J. Park, S.-J. Choi, D. H. Kim,and D. M. Kim, “Hybrid open drain method and fully current-basedcharacterization of asymmetric resistance components in a single MOS-FET,” IEEE Trans. Electron Devices, vol. 63, no. 11, pp. 4196–4200,Nov. 2016, doi: 10.1109/TED.2016.2607721.

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