alice si-fmd 10/09 2003jens jørgen gaardhøje, nbi, [email protected] forward multiplicity detector...
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10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected] 1
ALICE Si-FMDForward Multiplicity Detector (status and
progress)Si-FMD (Forward Multiplicity Detector)
o Si-strip Ring counters (5) with 50.000 channels o -5.1< < -1.7; 1.7< < 3.4o Off-line charged particle multiplicity for A+A, p+p o Fluctuations event-by-event, flow analysis
o Geometry and integration defined.Prototyping of mech. Supports.
o Final Si-sensor design ongoing.o Read out chain (FEE-BEE-DAQ) defined.Prototyping
ongoing.o Performance/simulationso TDR in preparation.
o Concerns: ’ambient’ temperature, material
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected] 2
ALICE Si-FMDSi-FMD
5 Si-strip rings segmented into 50.000 channels
Rapidity coverage from ITS (1.7) to 5.1.
Segmentation sufficient for ‘Poisson’ analysis
• Main Off-line charged particle multiplicity studies
• Average multiplicity (entropy, stopping)
• Fluctuations (phase transitions)
• Flow (thermalisation, hydrodynamics)
Si3 Si2Si1
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected] 3
ALICE Si-FMDForward rapidity physics at LHC
pp
BRAHMS@ RHIC snn= 200AGeV
Plateau at LHC –6<<+6 ?
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected] 4
ALICE Si-FMDCERN Maquette 1:1
Si1 (inner)Si1(outer)
V0-R T0-R
Absorber
ITS-pixels
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected] 6
ALICE Si-FMDFMD Cabling on muon side
Digitized signals , HV and control
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected] 7
ALICE Si-FMDSi1 mechanics model 1:1
Si detectors
Support plate
Digitizer card
Beam pipe support ringOuter ring not shown
Engineering study in progress to minimize material, maximize rigidity
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected] 8
ALICE Si-FMDHeat dissipation
Heat dissipated by FE electronics of one Si detector ring:
VA1’’ preamp chip (128 channels): 235 mW 80 chips = 19 W / ring
Read-out electronics and power distribution: 5 W/ring
Cooling: air flow between Si detector and support plate radiation from VA chips to support.
active (water) cooling of support plate is considered
Detailed cooling studies (simulations of heat profile) need to be done.
Presently, the temperature at the FMD, T0, V0 location is >70 deg. due to ITS heat dissipation.
Effective general cooling of this region required !
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected] 9
ALICE Si-FMDLeft Side: Si2 & Si3
Details of mounting to be finalized
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected] 10
ALICE Si-FMDSi rings
manufactured of 6” wafers
512
Inner:
Rin=4.2 cm
Rout=17.2 cm
Outer:
Rin=15.4 cm
Rout=28.4 cm
10x2x512=10240
20x2x256=10240
256
Possible suppliers:
Micron, UK
Hamamatsu, JP
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected] 11
ALICE Si-FMDCoverage in pseudorapidity
Constraints:
Vacuum tube outer envelope: 42 mm,
Outer radius, ITS, Absorber, cables
Background from secondaries(small angles)
Design criteria:
Largest possible coverage
Largest symmetry left and right
Overlap between systems
Si1:
Out: 1.70< <2.29 In: 2.01< <3.40
Si2:
Out: -2.29<<-1.7 In: -3.68< <-2.28
Si3:
In: -5.09< <-3.68
Vertex shift (10cm): |d| 0.1
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected] 12
ALICE Si-FMDDetails of Si sensors
Hamamatsu, Micron
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected] 14
ALICE Si-FMDHybrid with Viking PA chips
VA preamp+shaper: 128 ch
Connector(s) forpower, control, read-out
Other components
Other components
Hybrid cards contain: FE–Preampl. chips Bias voltages distribution Gate/strobe distribution Read-out clock distribution Detector bias connection
Si detector
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected] 15
ALICE Si-FMDFMD RO strategy
FMD Segment
ON DETECTOR
Digital serial links
(15-20 m)
Digital serial links
(15-20 m)
Trigger & Slow Ctrl
Trigger & Slow Ctrl
IN CAVERN INCOUNTING
ROOM
Slow control& Trigger
Slow control& Trigger
Detector Data Link(50-60 m)
Detector Data Link(50-60 m)
FMD RCU
VA
1 ring: 10/20 segments 2 Digitizers 1 RCU per side 1 DDL per sideFull FMD: 70 segments 10 Digitizers 2 RCU’s 2 DDL’s
FMD Read-Out and Control Electronics
Analog serial link(10 MHz) 0.5 m
Analog serial link(10 MHz) 0.5 m
VA read-outcontrol
VA read-outcontrol
Loc
al
Con
trol
ler
DD
L - IN
TSlow
-Control
Interface
TTC-RX
BOARDCTRL
Datareceiver
FMD Digitizer
ALTROALTRO
ALTROALTRO
ALTROALTRO
CTRLCTRL
Read-out CTRLRead-out CTRL
CTRLCTRL
CTRLCTRL
BSN, 21 Nov 2002
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected] 16
ALICE Si-FMDSi-FMD electronics overview
SI-FMD channel count
Note: We have increased the number of strips, but use more integrated FE chips – red values are changed.
Segments (wafers)
Phi sectors
Radial strips
FE channelsVA chips
(128 ch/chip)
ALTRO chips
FMD
Digitizers
FMD
RCU
Si1 inner 10 20 512 10,240 80 6 2 1
Si1 outer 20 40 256 10,240 80 6 2
Si2 inner 10 20 512 10,240 80 6 2
Si2 outer 20 40 256 10,240 80 6 2 1
Si3 10 20 512 10,240 80 6 2
Total system
70 140 51,200 400 30 10 2
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected] 17
ALICE Si-FMDFMD FEE test setup
BSN, 21 Nov 2002
FMD FEE test
CTRLCTRL
PowerBiasesPowerBiases
Clock10 MHzClock10 MHz
Trig in
ALTRO tester
ALTROALTRO
CTRLCTRL
Ext clock
Ext trigger
Sidetector
VA
Labview
DAQ
NBI test board:- generates trigger + pulse on Si det- level adaption of VA-to-ALTRO- VA read-out clock + controls- ALTRO digitization clock (sync.)
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected] 18
ALICE Si-FMDSi-FEE-Digitizer prototyping at NBI
ALTRO tester
Si-strip detector+ VA’’ preamp
VA’’ read-out controller
DAQ/
Labview
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected] 19
ALICE Si-FMDFirst prototype test results
Trigger Si+
Preamp Out
Altro Out
Output from VA chip: (128 channels multiplexed
into serial read-out)
Note: 3 bad Si/VA channels
Output from ALTRO: (128 time bins are digitized)
Note: general shape + 3 bad channels repeated
Noise still too highTiming still not stable
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected] 20
ALICE Si-FMDSlow ControlsFollow main strategy
DCS
Detector
CAEN ?
PVSS II PVSS II
Preamps
CAEN ?
Ethernet
Database(s)
OPCclient
DIMclient
14070
1 1
High Voltage
Preamps
User interface
PVSS II
HV LV
FMD
Co
ntr
ol
roo
m (
AC
R)
[FSM?]
Crate Control
PCI-CAN?CAEN OPCserver
PVSS IIOPS client
PCI-CAN?CAEN OPCserver
PVSS IIOPC client
DIMserver
Digitizers
FMD Digitizers
PCI-CAN??
PVSS IIOPC client
C2
28/02/03
E E
FMD-RCU(PCI? VME?)
20LV
P
2
DD
L
PCI-Profibus
Ethernet is considered
as alternative
P?
10
300?
10
LVL0
trig
TTC
Countin
g ro
om
Cavern
In m
agnet
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected] 21
ALICE Si-FMDCharged particle
occupancy including secondaries
20 sectors
512 strips each
10240 channels
20 sectors
512 strips each
10240 channels
40 sectors
256 strips each
10240 channelsHave increased number of strips by factor of 2 using ’128 ch VA-prime’
PA chip at practically same cost => average occupancy <1 for most strips!
x 2 x 2x 2
1
1 1
Si-1 innerSi-3 Si-1 outer
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected] 22
ALICE Si-FMD Background from Secondaries
Si1 outer
Si1 inner Si2 inner
Si3
Primaries
Beam pipe
ITS
T0,V0,Abs, frames
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected] 23
ALICE Si-FMDReconstruction of ’true’ multiplicity
10 HIJING events 1 HIJING event
Primaries+secondaries
Primaries
Input dist and reconstructed
HijingGeant= R * Hijing
R = R() response matrix
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected] 24
ALICE Si-FMDIterative convolution of trial spectrum
O = R * TrueSpec
O(0)= R(0)* H
TrueSpec(1)=O/O(1)*H
O(1)= R(1)* TrueSpec(1)
…Continue until O(n)O
Test of flat input distribution
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected] 25
ALICE Si-FMDSi-FMD timetable (1)
A FRONT END (FE) READ OUT ELECTRONICS Completed
1 Demonstrate functionality of conceptual layout of FEE(Viking PA chip, control system, interface to ALTRO test board)
August 2003
2 Final choice of VA pre-ampl. chip. RO test
3 Test FEE system coupled to sample Si detector. Source and electron beam tests.
4 Design, construction and test of prototype FMD digitizer card (FMDD), RO test with ’mini’ FMD-RCU
5 Full Si detector element + electronics chain RO with realistic RCU and DDL link to DAQ.
June 1 , 2004
B MECHANICS AND INTEGRATION Completed
1 Full scale model manufactured (Si1) February 1, 2003
2 Cabling and Cooling issues resolved June 1, 2003
3 Full integration sequence decided June 1, 2003
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected] 26
ALICE Si-FMDSi-FMD timetable (2)
C. SILICON DETECTOR Completed by
1 Complete market survey May, 2003
2 Define final specs October 2003
3 Place order for prototype with industry November 2003
4 Delivery Si-wafer prototype February 2004
5 Start production of Si-hybrid FEE card December 2003
6 Delivery prototype hybrid March 2004
7 Si prototype test with FEE and BEE test RO setup April 2004
8 Place final order for Si with industry October 2004
Pre-assembly test July-Nov 2004
Construction, assembly , test at RHIC 2005
Installation June-Sept 2006
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected] 27
ALICE Si-FMDSi-FMD, TO,VOTDR time table.
Fair amount of written material exists already (T0 100 pgs, Si-FMD 50 pgs, V0 20 pgs)
April 15. Collect first detector chapters. June ’03. Editorial meeting. 1rst draft. Summer ’03 Si-FMD electronics chain test. June ’03 T0 test beam August ’03 V0 test beam
TDR writing: fall 2003
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected] 28
ALICE Si-FMDTechical Design Report
Alice collab list. (5pgs)Summary of contents (2pgs)Table of contents. List of tables and figs. (4pgs)Color pictures of selected det. elements etc. (6pgs)1. Physics objectives and design considerations
T0, V0, Si-FMD trigger, timing, on-line mult, off-line mult, fluct, bgd rejection, overall performance, coverage etc ... (10
pgs) 2. Design objectives, mechanical structure, Integration
T0, V0, Si-FMD mounting, tolerances, clearances, inst. seq., cooling, cabling ... (10pgs)3. T0 (40 pgs)4. V0 (40 pgs)5. Si-FMD (40 pgs)6. Installation, slow control, DAQ, safety. (10 pgs)7. Organization (5 pgs) Group org., construction, installation, cost 8. References. (4pgs)9. Index (2 pgs) (approx. 180
pgs)
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected] 29
ALICE Si-FMDTasks and decisionsfor Weekly meetings
(1)1) Si sensors:
- define final specs of sensor properties - negotiate price again with Hamamatsu and Micron - choose company - order prototype
2) Voltage supplies - define Voltage requirements (Volt, current, remote control and DCS) - investigate market (check out ITS or other Si systems in ALICE)
3) Bonding - decide on bonding strategy (CERN or other) - make arrangement with bonder
4) FEE-preamplifier card. - define final specs of FEE hybrid card - define interface to ALTRO-digitizer card and other slow controls. - define strategy: home built hybrid card with VA-prime from IDEAS or design and production by IDEAS and production for card?
-updated cost estimate for industrial design and production (IDEAS)
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected] 30
ALICE Si-FMDTasks and decisions
for Weekly meetings(2)
5) Digitizer card (ALTRO board) -define interface to FEE and RCU - define necessary modifications to standard ALTRO boards
6) RCU card. - define interface to digitizer card (ALTRO board) - define necesary modifications to RCU
7) DDL and connection to DAQ -define modifications needed, if any
8) cabling and services, cooling - define cable types and length. - define connectors - define own cooling needs - define placement of cards/DDL etc in ALICE
9) Mechanical - define mechanical mounts for Si1, Si2, Si3.
10) Slow Control and DAQ communication - define tasks to be done -collect information and establish contact with DCS and DAQ groups.
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected] 32
ALICE Si-FMDFront end electronics
REQUIREMENTS: Adapted for 5-25pF
capacitance(300m Si, 0.5 cm2: 25pF,
1MIP: 22.400 e-)Dynamic range: 0-20 MIPSRadiation hardness:
>200kRadPeaking time: 1-2 sLow noise (good S/N)High integrationSample/hold and serial read-
out, 10 MHz clockModerate power consumptionSimple slow controls and
power reg.Affordable cost
VA1 prime 2 (Viking-IDEAS):Input capacitance: < 30 pF
0-20 MIPs>1MRad (0.35 m tech.)1-3 s475 e- at 25 pF => S/N 20:112810 Mhz clock
1.3 mW/chTest system available
OK
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected] 34
ALICE Si-FMDReconstructed
multiplicity.Average and width
Background Subtracted
All hits reconstructed
1.7
3.4
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected] 35
ALICE Si-FMDBackground
=2.4=1.31=1.73
Si3
Si2outerSi2inner Si1outer
Si1inner