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eEPAD TM

®

NABLED

E

ADVANCED

LINEAR

DEVICES, INC.

GENERAL DESCRIPTION

The ALD212900A/ALD212900 precision N-Channel EPAD® MOSFET array isprecision matched at the factory using ALD’s proven EPAD® CMOS technology.These dual monolithic devices are enhanced additions to the ALD110900A/ALD110900 EPAD® MOSFET Family, with increased forward transconductanceand output conductance, particularly at very low supply voltages.

Intended for low voltage, low power small signal applications, the ALD212900A/ALD212900 features Zero-Threshold™ voltage, which enables circuit designswith input/output signals referenced to GND at enhanced operating voltageranges. With these devices, a circuit with multiple cascading stages can bebuilt to operate at extremely low supply/bias voltage levels. For example, ananopower input amplifier stage operating at less than 0.2V supply voltage hasbeen successfully built with these devices.

ALD212900A EPAD MOSFETs feature exceptional matched pair device electri-cal characteristics of Gate Threshold Voltage VGS(th) set precisely at 0.00V+0.01V, IDS = +20µA @ VDS = 0.1V, with a typical offset voltage of only +0.001V(1mV). Built on a single monolithic chip, they also exhibit excellent temperaturetracking characteristics. These precision devices are versatile as design com-ponents for a broad range of analog small signal applications such as basicbuilding blocks for current mirrors, matching circuits, current sources, differen-tial amplifier input stages, transmission gates, and multiplexers. They also ex-cel in limited operating voltage applications, such as very low level voltage-clamps and nano-power normally-on circuits.

In addition to precision matched-pair electrical characteristics, each individualEPAD MOSFET also exhibits well controlled manufacturing characteristics, en-abling the user to depend on tight design limits from different production batches.These devices are built for minimum offset voltage and differential thermal re-sponse, and they can be used for switching and amplifying applications in +0.1Vto +10V (+0.05V to +5V) powered systems where low input bias current, lowinput capacitance, and fast switching speed are desired. At VGS > 0.00V, thedevice exhibits enhancement mode characteristics whereas at VGS < 0.00V thedevice operates in the subthreshold voltage region and exhibits conventionaldepletion mode characteristics, with well controlled turn-off and sub-thresholdlevels that operate the same as standard enhancement mode MOSFETs.

The ALD212900A/ALD212900 features high input impedance (2.5 x 1010Ω) andhigh DC current gain (>108). A sample calculation of the DC current gain at adrain output current of 30mA and input current of 300pA at 25°C is 30mA/300pA= 100,000,000, which translates into a dynamic operating current range of abouteight orders of magnitude. A series of four graphs titled “Forward Transfer Char-acteristics”, with the 2nd and 3rd sub-titled “expanded (subthreshold)” and “fur-ther expanded (subthreshold)”, and the 4th sub-titled “low voltage”, illustratesthe wide dynamic operating range of these devices.

Generally it is recommended that the V+ pin be connected to the most positivevoltage and the V- and IC (internally-connected) pins to the most negative volt-age in the system. All other pins must have voltages within these voltage limitsat all times. Standard ESD protection facilities and handling procedures for staticsensitive devices are highly recommended when using these devices.

PRECISION N-CHANNEL EPAD® MOSFET ARRAYDUAL HIGH DRIVE ZERO THRESHOLD™ MATCHED PAIR

FEATURES & BENEFITS

• Zero Threshold™ VGS(th) = 0.00V +0.01V• VOS (VGS(th) match) to 2mV/10mV max.• Sub-threshold voltage ( nano-power) operation• < 100mV min. operating voltage• < 1nA min. operating current• < 1nW min. operating power• > 100,000,000:1 operating current ranges• High transconductance and output conductance• Low RDS(ON) of 14Ω• Output current >50mA• Matched and tracked tempco• Tight lot-to-lot parametric control• Positive, zero, and negative VGS(th) tempco• Low input capacitance and leakage currents

APPLICATIONS

• Low overhead current mirrors and current sources• Zero Power Normally-On circuits• Energy harvesting circuits• Very low voltage analog and digital circuits• Zero power fail-safe circuits• Backup battery circuits & power failure detector• Extremely low level voltage-clamps• Extremely low level zero-crossing detector• Matched source followers and buffers• Precision current mirrors and current sources• Matched capacitive probes and sensor interfaces• Charge detectors and charge integrators• High gain differential amplifier input stage• Matched peak-detectors and level-shifters• Multiple Channel Sample-and-Hold switches• Precision Current multipliers• Discrete matched analog switches/multiplexers• Nanopower discrete voltage comparators

ALD212900A/ALD212900

VGS(th)= +0.00V

*IC pins are internally connected, connect to V-

SAL, PAL PACKAGES

PIN CONFIGURATION

ALD212900

V-

GN1

DN1

S12

DN2

GN2

1

2

3 6

7

8

4 5

M 1 M 2

V-

V-V-IC* V+

ORDERING INFORMATION (“L” suffix denotes lead-free (RoHS))

*Contact factory for industrial temp. range or user-specified threshold voltage values.

Operating Temperature Range *0°C to +70°C

8-Pin SOIC Package 8-Pin Plastic Dip Package

ALD212900ASAL ALD212900APAL ALD212900SAL ALD212900PAL

ALD212900A/ALD212900 Advanced Linear Devices 2 of 12

Notes: 1 Consists of junction leakage currents

OPERATING ELECTRICAL CHARACTERISTICSV+ = +5V V- = GND TA = 25°C unless otherwise specified

ALD212900A ALD212900

Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions

Gate Threshold Voltage VGS(th) -0.02 0.00 0.02 -0.02 0.00 0.02 V IDS = 20µA, VDS = 0.1V

Offset Voltage VOS 1 2 2 10 mV VGS(th)M1 - VGS(th)M2

Offset Voltage Tempco TCVOS 5 5 µV/°C VDS1 = VDS2

GateThreshold Voltage Tempco TCVGS(th) -1.7 -1.7 mV/°C ID = 20µA, VDS = 0.1V0.0 0.0 ID = 760µA, VDS = 0.1V

+0.6 +1.6 ID = 1.5mA, VDS = 0.1V

On Drain Current IDS(ON) 79 79 mA VGS = +3.0V, VDS = +3V

85 85 µA VGS = +0.1V, VDS = +0.1V

Forward Transconductance GFS 38 38 mmho VGS = +3.0VVDS = +3.0V

Transconductance Mismatch ∆GFS 1.8 1.8 %

Output Conductance GOS 2.3 2.3 mmho VGS = +3.0VVDS = +3.0V

Drain Source On Resistance RDS(ON) 14 14 Ω VGS = +5.0VVDS = +0.1V

Drain Source On Resistance RDS(ON) 5 5 KΩ VGS = +0.0V, VDS = +0.1V1.18 1.18 VGS = +0.1V, VDS = +0.1V

Drain Source On Resistance ∆RDS(ON) 1.8 1.8 % VGS = +5.0VTolerance VDS = +0.1V

Drain Source On Resistance ∆RDS(ON) 0.6 0.6 %Mismatch

Drain Source Breakdown BVDSX 10 10 V V- = VGS = -1.0VVoltage IDS = 10µA

Drain Source Leakage Current1 IDS(OFF) 10 400 10 400 pA VGS = -1.0V, VDS = +5VV- = -5V

4 4 nA TA = 125°C

Gate Leakage Current1 IGSS 5 200 5 200 pA VGS = +5V, VDS = 0V1 1 nA TA = 125°C

Input Capacitance CISS 30 30 pF

Transfer Reverse Capacitance CRSS 2 2 pF

Turn-on Delay Time ton 10 10 ns V+ = 5V, RL = 5KΩ

Turn-off Delay Time toff 10 10 ns V+ = 5V, RL = 5KΩ

Crosstalk 60 60 dB f = 100KHz

ABSOLUTE MAXIMUM RATINGSDrain-Source voltage, VDS 10.6VGate-Source voltage, VGS 10.6VOperating Current 80mAPower dissipation 500mWOperating temperature range SAL, PAL 0°C to +70°CStorage temperature range -65°C to +150°CLead temperature, 10 seconds +260°CCAUTION: ESD Sensitive Device. Use static control procedures in ESD controlled environment.


PERFORMANCE CHARACTERISTICS OF EPAD®

PRECISION MATCHED PAIR MOSFET FAMILY

ALD2108xx/ALD2129xx/ALD2148xx/ALD2169xx high precisionmonolithic quad/dual N-Channel MOSFET arrays are enhancedversions of the ALD1108xx/ALD1109xx EPAD® MOSFET family, withincreased forward transconductance and output conductance, in-tended for operation at very low power supply voltages. These de-vices are also capable of sub-threshold operation with less than1nA of operating supply currents and at the same time deliveringhigher output drive currents (typ. > 50mA). They feature precisionGate Offset Voltages, VOS , defined as the difference in VGS(th)between MOSFET pairs M1 and M2 or M3 and M4.

ALD's Electrically Programmable Analog Device (EPAD®) technol-ogy provides the industry's only family of matched MOSFET tran-sistors with a range of precision gate-threshold voltage values. Allmembers of this family are designed and actively programmed forexceptional matching of device electrical and temperature charac-teristics. Gate Threshold Voltage VGS(th) values range from -3.50VDepletion Mode to +3.50V Enhancement Mode devices, includingstandard products with VGS(th) specified at -3.50V, -1.30V, -0.40V,+0.00V, +0.20V, +0.40V, +0.80V, +1.40V, and +3.30V. ALD canalso provide any customer-desired VGS(th) between -3.50V and+3.50V on a special order basis. For all these devices ALD EPADtechnology enables excellent well-controlled gate threshold volt-age, subthreshold voltage, and low leakage characteristics. Withwell matched design and precision programming, units from differ-ent production lots provide the user with exceptional matching anduniformity characteristics. Built on the same monolithic IC chip, theunits also have excellent temperature tracking characteristics.

This ALD2108xx/ALD2129xx/ALD2148xx/ALD2169xx EPADMOSFET Array product family (EPAD MOSFET) is available in threeseparate categories, each providing a distinctly different set of elec-trical specifications and characteristics. The first category is theALD210800A/ALD210800/ALD212900A/ALD212900 Zero-Thresh-old™ mode EPAD MOSFETs. The second is the ALD2108xx/ALD2129xx enhancement mode EPAD MOSFETs. The third cat-egory includes the ALD2148xx/ALD2169xx depletion mode EPADMOSFETs. (The suffix “xx” denotes threshold voltage in 0.1V steps,for example, xx=08 denotes 0.80V). For each device, there is azero-tempco bias current and bias voltage point. When a designutilizes such a feature, then the gate-threshold voltage is tempera-ture stable, greatly simplifying certain designs where stability ofcertain circuit parameters over a temperature range is desired.

The ALD210800A/ALD210800 are quad Zero Threshold MOSFETsin which the individual gate-threshold voltage of each MOSFET isset at zero, VGS(th) = 0.00V at IDS(ON) = 10µA @ VDS(ON) = +0.1V(IDS(ON) = 20µA for the dual ALD212900A/ALD212900). ZeroThreshold MOSFETs operate in the enhancement region when op-erated above threshold voltage (VGS > 0.00V and IDS > 10µA) andsubthreshold region when operated at or below threshold voltage(VGS ≤ 0.00V and IDS < 10µA). These devices, along with otherlow VGS(th) members of the product family, enable ultra low supplyvoltage analog or digital operation and nanopower circuit designs,thereby reducing or eliminating the use of very high valued (expen-sive) resistors in many cases.

The ALD2108xx/ALD2129xx (quad/dual) product family featuresprecision matched enhancement mode EPAD MOSFET devices,which require a positive gate bias voltage VGS to turn on. PrecisionVGS(th) values at +3.30V, +1.40V, +0.80V, +0.40V and +0.20V areoffered. No conductive channel exists between the source and drainat zero applied gate voltage (VGS = 0.00V) for +3.30V, +1.40V and+0.80V versions. The +0.40V and the +0.20V versions have a sub-threshold current at about 1nA and 100nA for the ALD2108xx (2nAand 200nA for the ALD2129xx) respectively at zero applied gatevoltage. They are also capable of delivering lower RDS(ON) andhigher output currents greater than 68mA (see specifications).

The ALD2148xx/ALD2169xx (quad/dual) features Depletion ModeEPAD MOSFETs, which are normally-on devices at zero appliedgate voltage. The VGS(th) is set at a negative voltage level(V- < VGS < VS) at which the EPAD MOSFET turns off. Without asupply voltage and/or with VGS = V- = 0.00V = Ground, the EPADMOSFET device is already turned on and exhibits a defined andcontrolled on-resistance RDS(ON). An EPAD MOSFET may beturned off when a negative voltage is applied to V- pin and VGS setmore negative than its VGS(th). These Depletion Mode EPADMOSFETs are different from most other depletion mode MOSFETsand JFETs in that they do not exhibit high gate leakage currentsand channel/junction leakage currents, while they stay controlled,modulated and turned off at precise voltages. The same MOSFETdevice equations as those for enhancement mode devices apply.

KEY APPLICATION ENVIRONMENTS

EPAD MOSFETs are ideal for circuits requiring low VOS and lowoperating currents with tracked differential thermal responses. Theyfeature low input bias currents (less than 200pA max.), low inputcapacitance and fast switching speed. These and other operatingcharacteristics offer unique solutions in one or more of the follow-ing operating environments:

* Low supply voltage: 0.1V to 10V (+0.05V to +5V) * Ultra low supply voltage: < +10mV to +0.1V * Nanopower operation: voltage x current = nW or µW * Precision VOS characteristics * Matching and tracking of multiple MOSFETs * Matching across multiple packages

ELECTRICAL CHARACTERISTICS

The turn-on and turn-off electrical characteristics of the EPADMOSFET products are shown in the IDS(ON) vs. VDS(ON) andIDS(ON) vs. VGS graphs. Each graph shows IDS(ON) versus VDS(ON)characteristics as a function of VGS in a different operating regionunder different bias conditions, while IDS(ON) at a given gate inputvoltage is controlled and predictable. A series of four graphs titled“Forward Transfer Characteristics”, with the 2nd and 3rd sub-titled“expanded (subthreshold)” and “further expanded (subthreshold)”,and the 4th sub-titled “low voltage”, illustrates the wide dynamicoperating range of these devices.

Classic MOSFET equations for an N-channel MOSFET also applyto EPAD MOSFETs.

The drain current in the linear region (VDS(ON) < VGS - VGS(th)) isgiven by:

IDS(ON) = u . COX . W/L . [VGS - VGS(th) - VDS/2] . VDS(ON)

where: u = Mobility COX = Capacitance / unit area of Gate electrode VGS = Gate to Source Voltage VGS(th) = Gate Threshold (Turn-on)Voltage VDS(ON) = Drain to Source On Voltage W = Channel width L = Channel length

In this region of operation the IDS(ON) value is proportional to theVDS(ON) value and the device can be used as a gate-voltage con-trolled resistor.

For higher values of VDS(ON) where VDS(ON) ≥ VGS - VGS(th), thesaturation current IDS(ON) is now given by (approx.):

IDS(ON) = u . COX . W/L . [VGS - VGS(th)]2


PERFORMANCE CHARACTERISTICS OF EPAD®PRECISION MATCHED PAIR MOSFET FAMILY (cont.)

SUB-THRESHOLD REGION OF OPERATION

The gate threshold (turn-on) voltage VGS(th) of the EPAD MOSFETis a voltage below which the MOSFET conduction channel rapidlyturns off. For analog designs, this gate threshold voltage directlyaffects the operating signal voltage range and the operating biascurrent levels.

At a voltage below VGS(th), an EPAD MOSFET exhibits a turn-offcharacteristic in an operating region called the subthreshold re-gion. This is when the EPAD MOSFET conduction channel rapidlyturns off as a function of decreasing applied gate voltage. The con-duction channel, induced by the gate voltage on the gate elec-trode, decreases exponentially and causes the drain current to de-crease exponentially as well. However, the conduction channel doesnot shut off abruptly with decreasing gate voltage, but rather de-creases at a fixed rate of about 104mV per decade of drain currentdecrease. For example, for the ALD2108xx device, if the gate thresh-old voltage is +0.20V, the drain current is 10µA at VGS = +0.20V.At VGS = +0.096V, the drain current would decrease to 1µA. Ex-trapolating from this, the drain current is about 0.1µA atVGS = 0.00V, 1nA at VGS = -0.216V, and so forth. This subthresh-old characteristic extends all the way down to current levels below1nA and is limited by junction leakage currents.

At a drain current of “zero current” as defined and selected by theuser, the VGS voltage at that zero current can now be estimated.Note that using the above example, with VGS(th) = +0.20V, thedrain current still hovers around 100nA when the gate is at groundvoltage. With a device that has VGS(th) = +0.40V (part numberALD210804), the drain current is about 2nA when the gate is atground potential. Thus, in this case an input signal referenced toground can operate with a natural drain current of only 2nA internalbias current, dissipating nano-watts of power.

LOW POWER AND NANOPOWER

When supply voltages decrease, the power consumption of a givenload resistor decreases as the square of the supply voltage. Thus,one of the benefits in reducing supply voltage is to reduce powerconsumption. While decreasing power supply voltages and powerconsumption go hand-in-hand with decreasing useful AC bandwidthand increased noise effects in the circuit, a circuit designer canmake the necessary tradeoffs and adjustments in any given circuitdesign and bias the circuit accordingly for optimal performance.

With EPAD MOSFETs, a circuit that performs any specific functioncan be designed so that power consumption of that circuit is mini-mized. These circuits operate in low power mode where the powerconsumed is measure in mW, µW, and nW (nano-watt) region andstill provide a useful and controlled circuit function operation.

ZERO TEMPERATURE COEFFICIENT (ZTC) OPERATION

For an EPAD MOSFET in this product family, operating points existwhere the various factors that cause the current to increase as afunction of temperature balance out those that cause the current todecrease, thereby canceling each other, and resulting in a net tem-perature coefficient of near zero. An example of this temperaturestable operating point is obtained by a ZTC voltage bias condition,which is 0.38V above VGS(th) when VDS(ON) = +0.1V, resulting ina temperature stable current level of about 380µA for the ALD2108xxand 760µA for the ALD2129xx devices.

PERFORMANCE CHARACTERISTICS

Performance characteristics of the EPAD MOSFET product familyare shown in the following graphs. In general, the gate thresholdvoltage shift for each member of the product family causes otheraffected electrical characteristics to shift linearly with VGS(th) biasvoltage. This linear shift in VGS causes the subthreshold I-V curvesto shift linearly as well. Accordingly, the subthreshold operating cur-rent can be determined by calculating the gate source voltage droprelative to its gate threshold voltage, VGS(th).

NORMALLY-ON FIXED RDS(ON) AT VGS = GROUND

Several members of this MOSFET family produce a fixed resis-tance when their gate is grounded. For ALD210800, the drain cur-rent at VDS = 0.1V is @ 10µA at VGS = 0.00V. Thus, just by ground-ing the gate of the ALD210800, a resistor with RDS(ON) = ~10KΩ isproduced (For ALD212900 device, RDS(ON) = ~5KΩ). When anALD214804 gate is grounded, the drain current IDS = 424µA @VDS = 0.1V, producing RDS(ON) = ~236Ω. Similarly, ALD214813and ALD214835 produces 1.71mA and 3.33mA for each MOSFET,respectively, at VGS = 0.00V, producing RDS(ON) values of 59Ωand 30Ω, respectively. For example, when all 4 MOSFETs in anALD214835 are connected in parallel, an on-resistance of 30/4 =~7.5Ω is measured between the Drain and Source terminals whenVGS = V- = 0.00V, producing a fixed on-resistance without any gatebias voltages applied to the device.

MATCHING CHARACTERISTICS

One of the key performance benefits of using matched-pair EPADMOSFETs is to maintain temperature tracking between the differ-ent devices in the same package. In general, for EPAD MOSFETmatched pair devices, one device of the matched pair has gateleakage currents, junction temperature effects, and drain currenttemperature coefficient as a function of bias voltage that cancelout similar effects of the other device, resulting in a temperaturestable circuit. As mentioned earlier, this temperature stability canbe further enhanced by biasing the matched-pairs at Zero Tempco(ZTC) point, even though that may require special circuit configu-rations and power consumption design considerations.

POWER SUPPLY SEQUENCES AND ESD CONTROL

EPAD MOSFETs are robust and reliable, as demonstrated by morethan a decade of production history supplied to a large installedbase of customers across the world. However, these devices dorequire a few design and handling precautions in order for them tobe used successfully.

EPAD MOSFETs, being a CMOS Integrated Circuit, in addition tohaving Drain, Gate and Source pins normally found in a MOSFETdevice, have three other types of pins, namely V+, V- and IC pins.V+ is connected to the substrate, which must always be connectedto the most positive supply in a circuit. V- is the body of the MOSFET,which must be connected to the most negative supply voltage inthe circuit. IC pins are internally connected pins, which must alsobe connected to V-. Drain, Gate and Source pins must have volt-ages between V- and V+ at all times.

Proper power-up sequencing requires powering up supply voltagesbefore applying any signals. During the power down cycle, removeall signals before removing V- and V+. This way internally backbiased diodes are never allowed to become forward biased, possi-bly causing damage to the device. Of course, standard ESD con-trol procedures should also be observed so that static charge doesnot degrade the performance of the devices.


TYPICAL PERFORMANCE CHARACTERISTICS

FORWARD TRANSFER CHARACTERISTICSLOW VOLTAGE

500

400

300

200

0

100

GATE SOURCE OVERDRIVE VOLTAGEVGS - VGS(th) (V)

DR

AIN

SO

UR

CE

ON

CU

RR

EN

TI D

S(O

N)

(µA

)

0 +0.1 +0.2 +0.4 +0.5+0.3-0.4 -0.3 -0.1-0.2

VDS = + 5.0VTA = + 25°C

FORWARD TRANSFER CHARACTERISTICSFURTHER EXPANDED (SUBTHRESHOLD)


DR

AIN

SO

UR

CE

ON

CU

RR

EN

T ID

S(O

N)

(nA

)

1000000.00

10000.00

1000.00

100.00

10.00

1.00

0.10

0.01

-0.5 -0.4 -0.3 -0.2 -0.1 0.0 +0.1 +0.2

100000.00TA = + 25°C

LOW VOLTAGE OUTPUT CHARACTERISTICS

DRAIN SOURCE ON VOLTAGE - VDS(ON) (V)

DR

AIN

SO

UR

CE

ON

CU

RR

EN

T

I DS

(ON

) (m

A)

-0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5

40

30

20

10

0

-10

-20

-30

-40

V- = 0V

1V

2V

4V5V

VGS - VGS(th) = 0.5V

3V

OUTPUT CHARACTERISTICS


DR

AIN

SO

UR

CE

ON

CU

RR

EN

T ID

S(O

N)

(mA

)

0 2

40

100

80

60

20

0

6 8 10 4

VGS=VGS(th)+0.5V

VGS=VGS(th)+1.0V

VGS=VGS(th)+2.5V

VGS=VGS(th)+3.0V

VGS=VGS(th)+1.5V

VGS=VGS(th)+2.0V

FORWARD TRANSFER CHARACTERISTICS

100

DR

AIN

SO

UR

CE

ON

CU

RR

EN

T ID

S(O

N)

(mA

)

GATE SOURCE VOLTAGE - VGS (V)

-4 0

60

0

-2 2 4 6 8

20

80

40

TA = + 25°CVDS = + 5V

VGS(th) = +0.4V

VGS(th) = -3.5V

VGS(th) = +1.4V

VGS(th) = -0.4V

VGS(th) = 0.0V

VGS(th) = +0.2VVGS(th) = -0.8V

VGS(th) = -0.2V

VGS(th) = +0.8V

VGS(th) = -1.3V

FORWARD TRANSFER CHARACTERISTICSEXPANDED (SUBTHRESHOLD)

GATE SOURCE VOLTAGE - VGS (V)

DR

AIN

SO

UR

CE

ON

CU

RR

EN

T I D

S(O

N)

(nA

)

100000.00

10000.00

1000.00

100.00

10.00

1.00

0.10

0.01

-5 -4 -3 -2 -1 0 +1 +2

1000000.00

ALD

216935 ALD

212914

ALD

212908

ALD

212904

ALD

216904

ALD

216908

ALD

216913

ALD

216902

ALD

212900

ALD

212902

TA = + 25°C


TYPICAL PERFORMANCE CHARACTERISTICS (cont.)

LOW LEVEL OUTPUT CONDUCTANCE vs. AMBIENT TEMPERATURE

1000

800

600

400

200

0

LO

W L

EV

EL O

UT

PU

T

CO

ND

UC

TA

NC

E -

GO

S (µ

A/V

)

AMBIENT TEMPERATURE - TA (°C)

-50 -25 0 +25 +50 +125+100+75

VGS = VGS(th) + 0.5VVDS = + 3.0V

HIGH LEVEL OUTPUT CONDUCTANCE vs. GATE THRESHOLD VOLTAGE

GATE THRESHOLD VOLTAGE - VGS(th) (V)

-4.0 -3.0 -2.0 -1.0 0.0 +2.0 +3.0+1.0

HIG

H L

EV

EL

OU

TP

UT

C

ON

DU

CT

AN

CE

- G

OS

(m

A/V

) 2.75

2.50

2.00

2.25

1.75

1.50


TA = + 25°C

LOW LEVEL OUTPUT CONDUCTANCEvs. GATE THRESHOLD VOLTAGE

1000

0

LO

W L

EV

EL O

UT

PU

T

CO

ND

UC

TA

NC

E -

GO

S (µ

A/V

)

-3.0 -2.0 -1.0 0 +2.0 +3.0+1.0-4.0

200

400

600

800


TA = + 25°C


HIGH LEVEL OUTPUT CONDUCTANCE vs. AMBIENT TEMPERATURE

3.50

3.00

2.75

HIG

H L

EV

EL

OU

TP

UT

C

ON

DU

CT

AN

CE

- G

OS

(m

A/V

)

-50 -25 0 +25 +50 +125+100+75

3.25

2.50

2.00

2.25


VGS = VGS(th)+ 3.0VVDS = + 3.0V

TRANSCONDUCTANCE vs.AMBIENT TEMPERATURE

TR

AN

SC

ON

DU

CT

AN

CE

GF

S (

mA

/V)

100

80

60

40

0

20


-50 -25 0 +25 +50 +125+100+75


TRANSCONDUCTANCE vs.GATE THRESHOLD VOLTAGE


-4.0 -3.0 -2.0 -1.0 0.0 +2.0 +3.0+1.0

80

60

40

20

TR

AN

SC

ON

DU

CT

AN

CE

GF

S (

mA

/V)

0

TA = +25°C VGS = VGS(th) + 3.0VVDS = 3.0V



OUTPUT CHARACTERISTICS


100

80

60

40

20

0

DR

AIN

SO

UR

CE

ON

CU

RR

EN

TI D

S(O

N)

(mA

)

543210

VGS = VGS(th) + 3V

+125°C+70°C

-55°C

+25°C

0°C

ZERO TEMPERATURE COEFFICIENT (ZTC)

GATE SOURCE OVERDRIVE VOLTAGE VGS - VGS(th) (V)

1000

600

0

+0.3 +0.50 +0.4+0.2+0.1

DR

AIN

SO

UR

CE

ON

CU

RR

EN

TI D

S(O

N)

(µA

)

800

400

200

+125°C

- 55°C

+25°C

VDS = + 0.1V

Zero TemperatureCoefficient (ZTC)

GATE SOURCE OVERDRIVE VOLTAGE vs. DRAIN SOURCE ON CURRENT

0 10 20 30 40 706050

DRAIN SOURCE ON CURRENT - IDS(ON) (mA)

GA

TE

SO

UR

CE

OV

ER

DR

IVE

VO

LT

AG

EV

GS

-VG

S(t

h)

(V)

4

3

2

5

1

0

+125°C

+25°C

+70°C

-55°C 0°C

V+ = VDS = + 5V

GATE THRESHOLD VOLTAGE vs.AMBIENT TEMPERATURE

2.0

0

GA

TE

TH

RE

SH

OLD

VO

LT

AG

E

VG

S(t

h)

(V)


-50 -25 0 +25 +50 +125+100+75

-1.0

-2.0

1.0

VDS = + 0.1VID = 20µA

VGS(th) = 0.8V

VGS(th) = 0.0V

VGS(th) = -1.4V

DRAIN SOURCE ON CURRENT vs.GATE SOURCE OVERDRIVE VOLTAGE

100

80

60

40

20

0

543210

DR

AIN

SO

UR

CE

ON

CU

RR

EN

T

I DS

(ON

) (m

A)


VDS = + 1.0V -55°C

+25°C

+70°C +125°C0°C

5

4

3

2

1

0

1086420

GATE SOURCE OVERDRIVE VOLTAGE vs. DRAIN SOURCE ON CURRENT

GA

TE

SO

UR

CE

OV

ER

DR

IVE

VO

LT

AG

EV

GS

-VG

S(t

h)

(V)

DRAIN SOURCE ON CURRENT - IDS(ON) (mA)

VDS = + 0.1V

+25°C

- 55°C

0°C

+125°C

+70°C



OFFSET VOLTAGE vs. AMBIENT TEMPERATURE

+10

+8

+6

+4

+2

-2

0

-10

OF

FS

ET

VO

LT

AG

EV

OS

(m

V)

-50 -25 0 +25 +50 +125+100+75


-8

-6

-4

REPRESENTATIVE UNITSVOS = VGS(th)M1 - VGS(th)M2

DRAIN OFF LEAKAGE CURRENT IDS(OFF)vs. AMBIENT TEMPERATURE


-50 -25 0 +25 +50 +125+100+75

500

400

DR

AIN

OF

F L

EA

KA

GE

CU

RR

EN

T ID

S(O

FF

) (p

A)

300

200

600

100

0

IDS(OFF)


DIFFERENTIAL AMPLIFIER CURRENT SOURCE MULTIPLICATION

CURRENT SOURCE MIRROR CURRENT SOURCE WITH GATE CONTROL

TYPICAL APPLICATIONS

ISET RSET

M3

V+ = +5V

ISOURCE

M1, M2: N - Channel MOSFETM3, M4: P - Channel MOSFET

M1 M2

V+ = +5V

M4

M3, M4:ALD1102,ALD1117,1/2 ALD1103,1/2 ALD1105,1/2 ALD1107, or1/2 ALD3107xx

M1, M2:ALD1101, ALD1116, ALD1109xx, ALD2129xx, 1/2 ALD1103,1/2 ALD1105,1/2 ALD1106, 1/2 ALD1108xx, or 1/2 ALD2108xx

RSOURCE

ISOURCE = ISET = V+ - Vt

RSET

where Vt = VGS - VGS(th) = VDS

V+ = +5V

ISOURCE

RSET

M3

ISET

ON

OFF

Digital Logic Controlof Current Source

M1 : N - Channel MOSFETM3, M4 : P - Channel MOSFET

M4

M1

RSOURCE

M1:1/2 ALD1101, 1/2 ALD1116, 1/2 ALD1109xx, 1/2 ALD2129xx, 1/4 ALD1103,1/4 ALD1105,1/4 ALD1106, 1/4 ALD1108xx, or 1/4 ALD2108xx


V+

PMOS PAIR

M4VOUT

VIN-

NMOS PAIR

M2M1

VIN+

CurrentSource

M3

M1, M2: N - Channel MOSFETM3, M4: P - Channel MOSFET


M1, M2:ALD1101, ALD1116, ALD1109xx, ALD2129xx, 1/2 ALD1103, 1/2 ALD1105, 1/2 ALD1106, 1/2 ALD1108xx, or 1/2 ALD2108xx

MSET, M1..MN: N - Channel MOSFET

ISET

V+ = +5V

ISOURCE = ISET x NRSET

M2 M3MSET M1 MN

Package 1 Package N

MSET, M1..MN: N x ALD1101, N x ALD1116, N x ALD1109xx, N x ALD2129xx, N x ALD1103, N x ALD1106, N x ALD1108xx, or N x ALD2108xx

All M's in the set are from the same part number.

V+ = +5V

RSOURCE


CASCODE CURRENT SOURCES

BASIC CURRENT SOURCES

P- CHANNEL CURRENT SOURCEN- CHANNEL CURRENT SOURCE

TYPICAL APPLICATIONS (cont.)

ISET

V+ = +5V

M2

ISOURCE RSET

M3

M1

M1, M2, M3, M4: N - Channel MOSFETwhere M1 and M2 is a matched pair

and M3 and M4 is a second matched pair.

M4

M1, M2:ALD1101, ALD1116,ALD2129xx, 1/2 ALD1103,1/2 ALD1105,1/2 ALD1106, or 1/2 ALD2108xx

V+ = +5V

RSOURCE

M3, M4:ALD1101,ALD1116, 1/2 ALD1103, 1/2 ALD1105,1/2 ALD1106, or 1/2 ALD2108xx

ISOURCE

V+ = +5V

RSETISET

1

2

3

M1

568M2

7

M1, M2 :N - Channel MOSFET

V+ = +5V

RSOURCE

M1, M2: ALD1101, ALD1116, ALD1109xx, ALD2129xx, 1/2 ALD1103, 1/2 ALD1105,1/2 ALD1106, 1/2 ALD1108xx, or 1/2 ALD2108xx

ISOURCE = ISET = V+ - Vt

RSET


V+ = +5V

23 5

678

M4

ISOURCE

M3

RSETISET

M3, M4: P - Channel MOSFET

RSOURCE


ISET

V+ = +5V

M1

M3

M2

M4

ISOURCERSET

M1, M2, M3, M4: P - Channel MOSFETwhere M1 and M2 is a matched pair

and M3 and M4 is a second matched pair.

ISOURCE = ISET = V+ - 2Vt

RSET


RSOURCE

M1, M2: ALD1102,ALD1117,1/2 ALD1103,1/2 ALD1105,1/2 ALD1107, or1/2 ALD3107xx



8 Pin Plastic SOIC Package

Millimeters Inches

Min Max Min MaxDim

A

A1

b

C

D-8

E

e

H

L

S

1.75

0.25

0.45

0.25

5.00

4.05

6.30

0.937

8°

0.50

0.053

0.004

0.014

0.007

0.185

0.140

0.224

0.024

0°

0.010

0.069

0.010

0.018

0.010

0.196

0.160

0.248

0.037

8°

0.020

1.27 BSC 0.050 BSC

1.35

0.10

0.35

0.18

4.69

3.50

5.70

0.60

0°

0.25

ø

SOIC-8 PACKAGE DRAWING

L

CH

S (45°)

ø

e

A

A1

b

D

S (45°)

E


8 Pin Plastic DIP Package

Millimeters Inches

Min Max Min MaxDim

A

A1

A2

b

b1

c

D-8

E

E1

e

e1

L

S-8

ø

3.81

0.38

1.27

0.89

0.38

0.20

9.40

5.59

7.62

2.29

7.37

2.79

1.02

0°

5.08

1.27

2.03

1.65

0.51

0.30

11.68

7.11

8.26

2.79

7.87

3.81

2.03

15°

0.105

0.015

0.050

0.035

0.015

0.008

0.370

0.220

0.300

0.090

0.290

0.110

0.040

0°

0.200

0.050

0.080

0.065

0.020

0.012

0.460

0.280

0.325

0.110

0.310

0.150

0.080

15°

PDIP-8 PACKAGE DRAWING

b1

S

b

E E1

D

e

A2

A1

A

L

c

e1 ø

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