aida: advanced interconnections for chip packaging in future detectors, frascati, 2013, ivan peric...

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric Development of HV CMOS sensors for 3D integration Ivan Peri Bonn, CPPM, CERN, Heidelberg

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric Overview Collaboration between Bonn, CPPM, CERN, Heidelberg Sensors for particle physics in standard CMOS Merging of two technologies: HV CMOS detectors 3D integrated CMOS 3D integrated HV CMOS sensors 2

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric HVCMOS pixel detectors

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric HV-CMOS sensors Potential energy (electrons)/e p-substrate NMOS p-well n-well - 3.3 V 1.1 V 4 n-well PMOS

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric HV-CMOS sensors Potential energy (electrons)/e p-substrate NMOS n-well PMOS - 3.3 V 5 p-well 1.1 V

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric HV-CMOS sensors Potential energy (electrons)/e p-substrate NMOS n-well p-well PMOS - 3.3 V 6 1.1 V

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric HV-CMOS sensors High-voltage pixel Potential energy (electrons)/e collected charge p-substrate NMOS n-well p-well particles PMOS - 3.3 V 50 V 7

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric HV-CMOS sensors the structure Charge collection occurs by drift. (main part of the signal) Certain part of the signal collected by diffusion PMOSNMOS p-substrate Depletion zone Potential energy (e-) deep n-well Drift 8

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric HV-CMOS sensors the structure Charge collection occurs by drift. (main part of the signal) Additional charge collection by diffusion PMOSNMOS p-substrate Depletion zone Potential energy (e-) deep n-well Drift Diffusion 9

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric HV-CMOS sensors the structure HVCMOS sensors can be implemented in any CMOS technology that has a deep-n-well surrounding low voltage p-wells. (e.g. GF 130nm.) Maximizing of the depleted regions improves performances (less capacitance and noise, more signal) the best results can be achieved in high-voltage technologies (like AMS HV): These technologies (usually) use deeper n-wells and the substrates of higher resistances than the LV CMOS. PMOSNMOS p-substrate Depletion zone Potential energy (e-) deep n-well 10

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric HV-CMOS sensors the structure Example AMS 350nm AMS HV: Typical reverse bias voltage is 60-100 V and the depleted region depth ~15 m. 20 cm substrate resistance -> acceptor density ~ 10 15 cm -3. PMOSNMOS Depletion zone 100V ~15m deep n-well 11

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric HV-CMOS sensors The advantages of the HV CMOS pixel sensors are: Fast charge collection by diffusion that leads to a high radiation tolerance. The use of CMOS electronics in pixels, both PMOS and NMOS can be used. Possibility of thinning: only the surface region of the sensor is relevant for the signal generation. Compatibility with the existing CMOS technologies. 12

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric Signal-generation and amplification

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric Signal-generation and amplification Particle hit N-well e-h 14

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric Signal-generation and amplification Charge collection Assume: V sat = 8 x 10 4 m/s T col = 188 ps e- 188 ps 15

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric Signal-generation and amplification Voltage drop in the n-well Cdet Q/Cdet 188 ps Q 16

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric Signal-generation and amplification Amplification Cdet Q/Cdet 188 ps20ns Q 17

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric Signal-generation and amplification Feedback action through Cf N-well potential restored The diode amplifies its own signal Active or smart diode Cdet Q/Cf Q 188 ps20ns Q Cf 18

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric19 Measurements 55 Fe spectrum and RMS noise Not irradiated Room temperature RMS Noise 12 e 55 Fe spectrum, RMS noise Irradiated -10C RMS Noise 40 e Base line noise (RMS) 55 Fe Base line noise (RMS) 50 x 50 m pixels, shaping time 300ns

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric Technology drawbacks crosstalk Capacitive feedback into the sensor (n-well) Many important circuits do not cause problems: charge sensitive amplifier, simple shaper, tune DAC, SRAM but Active (clocked) CMOS logic gates and sometimes comparators cause large crosstalk. Possibility 1: Place the active digital circuits on the chip periphery. OK for large pixels. Possibility 2: Using of RO chips, either bump-bonded or capacitive coupling. Used so far. Possibility 3: 3D integration. 20 RO cells ROC

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric HV CMOS sensors based on 3D integration Smart diode sensor Readout chip Signal charge 21 Wafer bondingTSV

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric Tezzaron-GF 3D Process 22 Tezzaron Global Foundries process, offered by Mosis and CMP. Two tier process based on Global Foundries 130nm technologies. Two wafers (tier 1 and tier 2) are connected face to face with Cu-Cu thermo-compression bonding. For this purpose Tezzaron uses the 1m thick Cu TopMetal to create the leopard skin pattern. The Super contacts (TSVs) are realized after the transistor processing and before the metallization via middle process (TSV diameter of 1,2 m, TSV distance 25 m). The top wafer is thinned to access the super contacts. Back side metal is added for bonding after thinning. One tier Bond interface layoutWafer to wafer bonding

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric SDA 3D HVCMOS in Tezzaron-GF Process 23 TSV Tier 2 Tier 1 (thinned wafer) Back Side Metal M5 M4 M3 M2 M1 M2 M3 M4 M5 M4 M3 M2 M1 M2 M3 M4 M5

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric Technology options 24 For the sensor part three options. 1) Use the HV technology BCD lite. This technology includes the low-power option and the high-voltage option. Substrate resistivity 20 cm. High voltage n-well available. 35V reverse bias is achievable, leading to a depleted layer of about 5 m. 5 metal layers Reticle size : 26 x 30 mm. The engineering run cost ~ 350k$ Upper tier thinned down.

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric Technology options 25 For the sensor part three options. 2) Use 130nm LP process. Lower substrate resistivity (?). N-well diode breakdown voltage ~ 20V. Avalanche multiplication process might be possible. PSUB DN LPWNW NMOSPMOS DN LPWNW

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric Avalanche Multiplication 5 6 7 8 9 10 11 0 20406080 Reverse bias [V] Time over threshold [s] LED light pulses have been detected. Signal amplitude has been measured as the time over threshold. From 60V reverse bias, the time over threshold increases exponentially. (about 2x increase) Charge multiplication! 26 Measurement done by Ann-Kathrin Perrevoort

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric Technology options 27 For the sensor part three options. 3) Use 130nm GF process with a high resistivity wafer. Wafer resistances 500 to 1000 cm might be possible. PSUB DN LPWNW NMOSPMOS DN LPWNW

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric 3D HVCMOS readout architecture 28 20um x 20um pixels, expected noise of 15 e Time resolution of about 20 ns and a power consumption of 1-2 uW/pixel AddressToTTS Comparator FIFO AddressToTTS AddressToTTS AddressToTTS RO cell Pixels TS Trigger TSdel

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric 3D HVCMOS results and plans 29 Submission planned for spring 2013. We have separately tested both components of the detector, the sensor part implemented in the AMS HV technology and the Tezzaron / GF 3D technology. Sensor readout chip in Tezzaron/GF 3D process designed by Bonn and CCPM nice results will be presented by Theresa Obermann. HVCMOS in AMS H18 technology stand alone tests and the readout with FEI4; will be presented by Daniel Mnstermann. The 3D integration of HVCMOS sensors should be straightforward.

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric Summary 30 The HV-CMOS technology allows production of a hybrid detectors in a commercial process without the need for dedicated sensors. In this way we are reducing of costs, time and complexity.

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric Thank you 31

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric Additional Slides 32

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric FETC4 33

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric FETC4 FETC4 prototype 3D IC Circuitry of analog tier

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric FETC4 The depleted layer is relatively small => relatively small signals. 35 Threshold ~2400 e Noise ~94 e The threshold can be measured by reading out both tiers with the same result The measured threshold and noise dispersions and mean values are within the expectations THRESHOLDNOISE Read analog tier Read digital tier

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric Test Chip HV2FEI4

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric HV2FEI4 Pixel matrix: 60x24 pixels Pixel size 33 m x 125 m 21 IO pads at the lower side for CCPD operation 40 strip-readout pads (100 m pitch) at the lower side and 22 IO pads at the upper side for strip-operation Pixel contains charge sensitive amplifier, comparator and tune DAC. Strip pads IO pads for CCPD operation IO pads for strip operation Pixel matrix 4.4mm 37

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric CCPD readout 2 3 1 2 3 1 Bias A Bias B Bias C FEI4 Pixels CCPD Pixels Signal transmitted capacitively 38

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric Sr-90 signals after 80 MRad 39

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric 40

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric Irradiation with protons at KIT (10 15 n eq /cm 2, 300 MRad) 55 Fe 22 Na 0V-30V -60V 41

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric Publications I. Peric, A novel monolithic pixelated particle detector implemented in high-voltage CMOS technology, Nucl. Instrum. Meth. A582 (2007) 876885. I. Peric, A novel monolithic pixel detector implemented in high-voltage CMOS technology, IEEE Nucl. Sci. Symposium Conference Record vol. 2 (2007) 10331039. I. Peric, Ch. Takacs, Large monolithic particle pixel-detector in high voltage CMOS technology, Nucl. Instrum. Meth. A624 (2010) 504508. I. Peric, Ch. Takacs, J. Behr, P. Fischer, The first beam test of a monolithic particle pixel detector in high-voltage CMOSTechnology, Nucl. Instrum. Meth. A628 (2011) 287291. I. Peric, Ch. Takacs, J. Behr, P. Fischer, Particle pixel detectors in high voltage CMOS technology - new achievements, Nucl. Instrum. Meth. A650 (2011) 158162. I. Peric for HVCMOS Collaboration, Active Pixel Sensors in high voltage CMOS technologies for ATLAS, JINST 7 C08002 (2012). I. Peric, Hybrid Pixel Particle Detector Without Bump Interconnection, IEEE Trans. Nucl. Sci. 56 (2009) 519528. I. Peric, C. Kreidl, P. Fischer, Hybrid pixel detector based on capacitive chip to chip signal- transmission, Nucl. Instrum.Meth. A617 (2010) 576581. 42

AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric Experimental results - overview HVPixel1 CMOS in-pixel electronics with hit detection Binary RO Pixel size 55x55m Noise 60e MIP seed pixel signal 1800 e Time resolution 200ns CCPD2 -capacitive coupled pixel detector Pixel size 50x50m Noise 30-40e Time resolution 300ns MIP SNR 45-60 PM2 chip - frame mode readout Pixel size 21x21m 4 PMOS pixel electronics 128 on-chip ADCs Noise: 21e (lab) - 44e (test beam) MIP signal - cluster: 2000e/seed: 1200e Test beam: Detection efficiency >98% Seed Pixel SNR ~ 27 Cluster signal/seed pixel noise ~ 47 Spatial resolution ~ 3 m Irradiations of test pixels 60MRad MIP SNR 22 at 10C (CCPD1) 10 15 n eq MIP SNR 50 at 10C (CCPD2) Monolithic detector - frame readout Capacitive coupled hybrid detector MuPixel Monolithic pixel sensor for Mu3e experiment at PSI Charge sensitive amplifier in pixels Hit detection, zero suppression and time measurement at chip periphery Pixel size: 39x30 m (test chip) (80 x 80 m required later) MIP seed signal 1500e (expected) Noise: ~40 e (measured) Time resolution < 40ns Power consumption 7.5W/pixel HV2FEI4 chip CCPD for ATLAS pixel detector Readout with FEI4 chip Reduced pixel size: 33x125m RO type: capacitive and strip like Noise: ~80e (stand alone test, preliminary) HPixel - frame mode readout In-pixel CMOS electronics with CDS 128 on-chip ADCs Pixel size 25x25 m Noise:60-100e (preliminary) MIP signal - cluster: 2100e/seed: 1000e (expected) SDS - frame mode readout Pixel size 2.5x2.5 m 4 PMOS electronics Noise: 20e (preliminary) MIP signal (~1000e - estimation) Monolithic detector continuous readout with time measurement 1. Technology 350nm HV substrate 20 cm uniform 2. Technology 180nm HV substrate 10 cm uniform 3. Technology 65nm LV substrate 10 cm/10 m epi 43

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