AHCAL DAQ

HardwareData organizationTiming

Jiri KvasnickaEUDAQ meetingDESY, 25.11.2015

Jiri Kvasnicka | EUDAQ workshop, DESY | 25.11.2015 | Page 2/10

AHCAL Detector

> 3x3x0.3 cm3 scintillator tiles with SiPM

> SPIROC ASIC (designed by Omega group)

36 channels

Autotrigger (signal must pass a threshold)

16 analogue memory cells

Optional Trigger validation (unvalidated events are discarded): only in beam test mode

Runs until 16 memory cells are full, then it needs long time to convert and readout (~10 ms)

> Base unit: HBU 4 ASICs, 144 channels, 36x36 cm2

Scalability: 6 HBU in row (called “slab”)

Up to 3 slabs read out by single HDMI cable

Jiri Kvasnicka | EUDAQ workshop, DESY | 25.11.2015 | Page 3/10

DAQ hardware: chain of devices

> Clock and Control Card (CCC) Provides master clock Starts and stops the acquisition according to the

spill level and readiness of all ASICs Distributes trigger validation

> Link Data Aggregator (LDA) Packet collecting Packet processing (decoding, merging) Send the packets over TCP/IP to DAQ PC

> Detector InterFace (DIF) Controls the ASICs (voltages, acq. state) Collects data from all ASICs on HBU Sends the data to LDA

> ASIC (SPIROC 2b, Omega group) Reads out 36 SiPMs Has 16 memory channels for ADC and TDC

> BIF (Beam Interface) – new (Nov 2015) Mini-TLU in slave mode (firmware modified) Independent DAQ offline correlation

CCC

LDA

DIF

PC

ASIC

…Up to 8LDAs

...Up to 96

DIFs

…Up to 72SPIROCs

36SiPMs

...Up to 96

DIFs

...Up to 96

DIFs

TriggerSpill

Data

BIF

Jiri Kvasnicka | EUDAQ workshop, DESY | 25.11.2015 | Page 4/10

Acquisition

> SPIROC operates either in ILC mode (200 ns clock period => 337 ns) or Testbeam mode (4 us clock period)

> SPIROC internally counts clock cycles with 12 bit counter – Bunch crossing ID (BxID)> BxID counters synchronous in all layers, reset during start> Whenever 1 channel triggers, all 36 channels are stored in the analogue memory cells (at

the end of the BxID latest)> Acquisition continuous until all memory cells are filled. Then BUSY signal is set> We count acquisition cycle

0 1 2 3 4 5 6 7 8 9

Phys. event Phys. event Phys. event

10 ...BxID:

ASIC stores:

time

Mcell BxID0 21 62 73 94 ...

noise

Jiri Kvasnicka | EUDAQ workshop, DESY | 25.11.2015 | Page 5/10

Data organization

> TCP stream. One readout = all packets with same ROC.> Smallest “event” (packet): up to 2.4 kB RAW ASIC packet

LDA Header (length, Readout Cycle number, LDA id, port number, flags) RAW ASIC data (up to 16 BxIDs, up to 16x TDC+ADC for 36 channels)

> Packets come out-of-order (depends on data occupancy) Only ASIC packets from 1 detector layer are in order

>Generally Independent BxIDs in ASICs, even within single layer>Can have 2 particles within same BxID (DESY: ~1 us spacing)

How to correlate this case? ASIC TDC needs calibration before it can be used.

Mcell: BxID:0 21 62 73 94 ...

ADC+TDC:16*36*2*2

BytesMcell: BxID:

0 21 52 93 ...

ADC+TDC:16*36*2*2

BytesMcell: BxID:

0 21 32 63 85 9

ADC+TDC:16*36*2*2

Bytes

4 ...

noise

Layer 2, ASIC 1Layer 1, ASIC 1 Layer 1, ASIC 2

(missing BxID 6)

L1 A1L1 A2

L1 A3

L1 A4

L2 A1

L2 A2

L2 A3L2 A4

L3 A1L3 A2

L3 A3

L3 A4

L3 A1ROC+1

ROC

Jiri Kvasnicka | EUDAQ workshop, DESY | 25.11.2015 | Page 6/10

Timing

> Typical active time: few ms Depends on noise & beam rate

> Sustained for single HBU: >30 Readout_Cycles/s

~500 physical_events/s recoded

<16ms ~1ms ~15ms ~10ms

CERN PS 2014 timing

~8ms

Oct 2015:

ROC+1

Jiri Kvasnicka | EUDAQ workshop, DESY | 25.11.2015 | Page 7/10

Common running with SiW ECAL @ CERN PS 2014

> AHCAL + SiW ECAL layer> SiW ECAL System differences

50 MHz clock (vs. 40 MHz) No busy / Memory full (re-enabled in the Si ECAL

DIF by Remi Cornat) Only Spill input 2.5 MHz BXID (vs. 250 kHz) No TDC

> EUDAQ as common DAQ SW> Common properly timed events found!

Scint.CCC

xLDA

8 DIFs

xLDA

7DIF

CCC

LDA

1 DIF

AHCALSW

SiEcalSW

SiECAL Sci CAL

Spill,clk

Eudaq AHCAL PC(Labview)SiECAL PC

Jiri Kvasnicka | EUDAQ workshop, DESY | 25.11.2015 | Page 8/10

Conclusion

> Stable Hardware DAQ tested in many beam tests

>Common running with 1 SiECAL layer (Implementation: Taikan Suehara)

>New BIF based on mini-TLU tested.

“Proper” adoption of mini-TLU under discussion

>Near future plans for updates (hardware only):

mini-TLU

New DIF firmware

Tests of new ASIC (SPIROC2d)

power-pulsing tests

Jiri Kvasnicka | EUDAQ workshop, DESY | 25.11.2015 | Page 9/10

Oct 2014(USB)

Dec 2014(HDMI1)

Aug 2015(HDMI2)

Future(3)

Sustained LED calib (16 mem. cells) 1-2 3-4 6.2 12

Sustained TB (no spill) RO/s 2-3 ~6-7 (est.) ~17 35

Readouts per 400 ms spill 2 3-4 7 (Est) 14

Theoretical events per 400ms spill 30 45-60 105 210

Theoretical sustained phys.events/s ~30 ~100 ~255 ~525

Beamtest data rates: PS 2014, SPS 2015

TB Dec 2014 (CERN PS) TB Aug 2015 (CERN SPS)

1 Explicit RO command2 Automatic data send3 Foreseen DIF speedup

Jiri Kvasnicka | EUDAQ workshop, DESY | 25.11.2015 | Page 10/10

BIF connection

HDMI cable

Clock (diff)gnd

3 pairsin RJ45