LAB 3 – PIC 18 I/O PORTPROGRAMMING

PART I : VERIFY SFR AND FILEREG AND CALCULATE TIME EXECUTION

1.

Instruction Instruction cycles

Time to execute

MOVLW 0X55 1 1x1u =1usDECF MYREG 1 1x1u =1usMOVWF 1 1x1u =1usGO TO 2 2x1u =2usCALL 2 2x1u =2us

2. Using crystal frequency of 20MHz

Instruction Instruction cycles

Time to execute

MOVLW 0X0A 1 1x1u =1usMOVWF MYREG 1 1x1u =1usNOP 1 1x1u =1usNOP 1 1x1u =1usNOP 1 1x1u =1usDECF MYREG 1 1x1u =1usBNZ 2 2x1u =2usRETURN 1 1x1u =1us

Solution :Time delay = [(10x6)+1+1+1] x 0.2µs

= 12.6µs

3. Using crystal frequency is 20MHz

Instruction Instruction cycles

Time to execute

MOVLW 0X55 1 1x1u =1usMOVWF MYREG 1 1x1u =1usNOP 1 1x1u =1usNOP 1 1x1u =1usDECF MYREG 1 1x1u =1usBNZ 2 2x1u =2usRETURN 1 1x1u =1us

Solution :Time delay = [(85x5)+1+1+1] x 0.2µs

= 85.6µs

4. Using crystal frequency is 20MHz

Instruction Instruction cycles

Time to execute

MOVLW 0X55 1 1x1u =1usMOVWF PORTB 1 1x1u =1usCALL DELAY 2 2x1u =1usMOVLW 0XAA 1 1x1u =1usMOVWF PORTB 1 1x1u =1usCALL DELAY 2 2x1u =2usGOTO BACK 2 2x1u =1us

Solution :Time delay: [(85x170x4)+6] x 0.2µs

: 11.5612ms

DISCUSSION :

In this experiment, we have learned many things about verifying SFR and FileReg and how to calculate the time execution. It takes certain amount of time for the CPU to execute an instruction. For example ,this subroutine will generate an 1 mSec delay. The PIC operates with a 4 MHz clock input. This means that each instruction cycle is executed with 1MHz frequency, in other words, once every 1uSec. So we need to call a subroutine that will execute 1000 instructions, in order to achieve the 1mSec delay. In this exercise, we have made calculation on how to get the time to execute for each instruction. Each instruction have their own and exact value of instruction cycles. For example, for PIC18 of 4 Mhz, we must take ¼ of the crystal frequency. Eg: 4MHz/4=1M; instruction cycle is 1/1MHz = 1µs(microsecond).

PART 2 : I/O PORT PROGRAMMING with MPLAB Simulator

A. TRIS register role in-out putting data

DISCUSSION :

The TRIS register is data direction register which defines if the specific bit or whole port will be an input or an output. Each PORT has its own TRIS register. Here's a map of the locations.The default mode of each TRIS is input. If you want to set a specific port as exit you must change the state of the TRIS to 0.Keep in mind: to change a specific port to an output, one should first move to the BANK1, make the change, and then return to BANK0. The default state of the banks is BANK0. The running program is working only with one bank at all time. If not set otherwise, then as stated, the default bank is BANK0. Part of the registers located inside BANK0, and some are not. When we need to access a register that is not located inside BANK0, we are required to switch between the banks. For example, the access to PORT registers is done inside BANK0. However, to change port from an input to an output and vice versa, we need to access TRIS register that is located inside BANK1. From the moment we moved to the BANK1, the program will always work with BANK1; at this time, to access registers inside BANK0, we will have to return to the situation in which our program will work with BANK0.

B. TRIS register role in inputting data

DISCUSSION :

To make a port an input port, we must first put 1s into the TRISx register for that port, and then bring in (read) the data present at the pins. Notice that 0 stands for out and 1 for in. this is easy to remember because O and 0 look alike the same way I looks like 1. Again, it must be noted that unless we activate the TRIS bits (by putting 1s there), the data will not be brought into the WREG register from the pins of PORTC. To see the role of the TRISx register in allowing the data to come into the CPU from the pins.

C. I/O OPERATION

CLRF TRISBSETF TRISC

L5 MOVFF PORTC,PORTBBRA L5

DISCUSSION :

We need NOP to make sure that the data is written into WREG before it is read for outputting for PORTB. This is called data dependency in CPU design. This data is commonly referred to as RAW (Read-After-Write). The NOP will introduce a bubble into the pipeline to remove data dependency due to RAW.

CONCLUSION :

After we have finish with this experiment, we can conclude that to determine on how to verify SFR, FileReg, and to calculate time execution. We also know that there are three ways to create time delay in PIC 18. One, is by using a simple loop. By using a simple loop, the instruction can buy some delay . Second, is by using delay function library and lastly is by using the PIC18 timers. All of this can create time delays in PIC18. To make a port an input port, we must first put 1s into the TRISx register for that port, and then bring in (read) the data present at the pins. Notice that 0 stands for out and 1 for in. this is easy to remember because O and 0 look alike the same way I looks like 1. Again, it must be noted that unless we activate the TRIS bits (by putting 1s there), the data will not be brought into the WREG register from the pins of PORTC. To see the role of the TRISx register in allowing the data to come into the CPU from the pins. To make a port an input port, we must first put 1s into the TRISx register for that port, and then bring in (read) the data present at the pins. Notice that 0 stands for out and 1 for in. this is easy to remember because O and 0 look alike the same way I looks like 1. Again, it must be noted that unless we activate the TRIS bits (by putting 1s there), the data will not be brought into the WREG register from the pins of PORTC. To see the role of the TRISx register in allowing the data to come into the CPU from the pins. We need NOP to make sure that the data is written into WREG before it is read for outputting for PORTB. This is called data dependency in CPU design. This data is commonly referred to as RAW (Read-After-Write). The NOP will introduce a bubble into the pipeline to remove data dependency due to RAW.