advantages of ldd-only implanted fluorine with submicron cmos technologies

388 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 44, NO. 3, MARCH 1997

Advantages of LDD-Only Implanted Fluorinewith Submicron CMOS Technologies

Homyar C. Mogul, Timothy A. Rost, and Der-Gao Lin

Abstract— The effect of fluorine implantation on the proper-ties of shallow n+/p junctions has been investigated. The novelapproach of this work lies in the introduction of fluorine onlyin the LDD regions of the device and not in the active regionunderneath the gate. Gated diodes were used as test vehicles tostudy the effect of the fluorine incorporation. Gated diodes areideal for measurements of this nature since they are sensitive tochanges in the interfacial properties near the gate to diffusionoverlap region. Results from electrical device characterizationindicate a reduction in gated diode leakage and mid-gap interfacestate density as the F-implanted dose is increased without causingany significant change in the flat-band voltages. Results alsoshowed that samples with F incorporation tended to be morerobust to electrical stress than those without F. Materials analysisindicated reduced junction depths for samples with F introducedin the LDD regions indicating suppression of phosphorus dopantdiffusion.

I. INTRODUCTION

A S TRANSISTOR dimensions continue to be scaled intothe deep submicron region, the process steps in a tran-

sistor flow need to be continuously re-evaluated to determinetheir suitability at each node. In particular, the processes whichinfluence the final channel length become extremely important.This has led to the requirement of very shallow junctions fordeep submicron technologies. However, as the junction depthis decreased, lateral diffusion becomes more of a problem.If the lateral diffusion is not properly controlled, undesiredchannel shortening may result. In recent years, a number ofdifferent approaches have been investigated to control thelateral diffusion, including the incorporation of fluorine to theactive gate region [2]–[5]. The introduction of fluorine hasalso been shown to provide high quality SiO/Si interfaces,improve channel hot-carrier effects (CHC), and reduce n/pand p /n junction surface leakage [2], [6], [7].

Unfortunately, the presence of F has also been linkedto several problems. In one study where F was implanteduniformly under the entire poly gate, effective gate oxidethickness increases, threshold voltage shifts, and gate oxidequality issues were observed [3], [6]. To overcome theseproblems, devices investigated in this work were fabricatedby implanting F only in the lightly-doped drain (LDD) regionsand not the entire active device area. The rest of the transistor

Manuscript received October 10, 1995; revised April 1, 1996. The reviewof this paper was arranged by Editor D. A. Antoniadis.

H. C. Mogul and T. A. Rost are with Deep Submicron ASP Productization,Texas Instruments, Inc., Dallas, TX 75265 USA.

D.-G. Lin was with Deep Submicron ASP Productization, Texas Instru-ments, Inc., Dallas, TX 75265 USA. He is now with Motorola, Inc., AdvancedCustom Technologies, Mesa, AZ 85202 USA

Publisher Item Identifier S 0018-9383(97)01481-0.

flow followed a conventional CMOS process. Parameters suchas gated diode leakage, flat band voltage, threshold voltagewere then measured to calculate recombination velocitiesand mid-gap interface densities as a function of F implantenergy and dose. Secondary ion mass spectroscopy has beenimplemented to observe the effect of fluorine incorporation onjunction depth and dopant diffusion.

II. EXPERIMENTAL

Polysilicon gate MOS devices with thick field isolation for3.3-V operation were fabricated on (100)-oriented p-type Siwafers. The as-drawn poly is 0.6m with a nominal gateoxide of 100A. After poly doping (POCl), gate patterningand etching, a phosphorus LDD implant was performed.Immediately following this LDD implant, F is introduced intothe LDD regions only by ion implantation at 25 and 35 keVwith doses ranging from 8 10 to 2 10 cm . Allthe implants were done at a 0angle. After the F implant,the control wafers (not receiving any F implant) and the LDDfluorine-implanted wafers follow a normal unsilicided CMOSprocess. The split information is shown in Table I.

The structures that were used as test vehicles were n/p-gated diodes and 25 0.6 ( m) NMOS transistors. The gateddiode consisted of 126 poly fingers with an area of 1.45cm . This type of gated diode structure is considered to be anoptimum one for performing measurements such as surfacerecombination velocity [8]. This is because this structure isvery sensitive to the properties of the SiO/Si interfaces in thegate to diffusion overlap region.

III. RESULTS AND DISCUSSION

A. Electrical Characterization

Fig. 1 shows the comparison of n/p gated diode leakageat a fixed reverse bias of 1V, as a function of gate voltage be-tween the baseline sample and samples which were implantedwith 25-keV fluorine at doses ranging from 8 10 to 2

10 cm . The leakage current of a reverse biased gate-controlled diode is essentially due to carrier generation. Theinterface is accumulated for < V and the leakage currentoriginates from the junction controlled depletion region. When

< < the interface is depleted and the current is mainlydue to surface generation. At > (inversion) the interfacegeneration is seen to drop [7].

An important feature observed from Fig. 1 is the fact thatthe incorporation of fluorine in the LDD regions is directly

0018–9383/97$10.00 1997 IEEE

MOGUL et al.: ADVANTAGES OF LDD-ONLY IMPLANTED FLUORINE 389

TABLE ISPLIT INFORMATION AND PARAMETERS EXTRACTED FROM n /p GATED DIODE MEASUREMENTS FOR THECASE OF 25-KeV

AND 35-KeV FOUORINE IMPLANTS AT VARIOUS DOSES

Fig 1. n+/p junction leakage at reverse bias of 1 V for gated diodes as a function of gate voltage for 25-keV fluorine implant. The variable parameteris the fluorine implantation in the LDD region.

related to the dramatic reduction of leakage current especiallyin the depletion condition. This implies that as the fluorine doseincreases the recombination–generation current at the SiO/Sisurface reduces by almost 50%. This result matches wellwith values previously reported where fluorine was uniformlyimplanted in the entire junction as opposed to just in theLDD regions [1], [2]. This result suggests that a similarimprovement can be obtained using the present technique

while at the same time reducing the adverse effects of uniformF-implantation in the entire device area reported previously[3], [6]. Comparison of n /p gated diode leakage at a fixedreverse bias of 1 V, as a function of gate voltage implantedwith 35-keV fluorine at different doses showed a similar trend.

Surface recombination velocity which is estimated from theleakage current in the gate controlled area under depletionconditions is shown in Fig. 2 for the case of 25-keV fluorine-


Fig 2. Dependence of surface recombination velocity on fluorine dose.

Fig 3. Mid-gap interface density and flat band voltage dependence on fluorine dose for a 25-keV implant case.

implanted samples. The figure indicates that as the fluorinedose increases, the recombination velocity drops to almost50% of the baseline sample.

Fig. 3 compares the calculated mid-gap interface trap den-sity of the fluorinated samples with the control sample forthe case of 25-keV fluorine implant. It is apparent that the

interface trap density decreases rapidly as the dose of thefluorine implant increases. Also superimposed on the same plotis the trend of flat-band voltage with the various fluorinatedsamples and the control sample. The flat band voltage forthese samples was extracted from the leading edge of thegated diode leakage curves and is indicated on Fig. 1. The


TABLE IISAMPLE INFORMATION FOR MATERIALS ANALYSIS (SIMS)

plot indicates little change in the value for flat-band voltage.This result is significant from the process point of view inthat it indicates that by performing the fluorine implant in thismanner, no significant amount of fixed charge is generatedeven with an implant dose of cm . Similar resultsare seen for the case of 35-keV fluorine-implanted samples.Table I comprehensively lists all the pertinent parameters forboth the 25-keV and the 35-keV F-implant cases.

Another advantage of the gated diode measurement is thatit provides an alternate means of measuring the thresholdvoltage other than the traditional – FET characteristics.The threshold voltage is measured from the falling edge ofthe gated diode leakage curves. Also this threshold voltage ismeasured at very low level of current, approximately 0.5-1pA in this particular experiment. An important point to realizeis that the threshold voltage as obtained from the– curveas shown in Fig. 1 is actually the voltage between the drain(source) and the gate. Therefore, to arrive at the typicallydefined threshold voltage, i.e., voltage at zero source (drain)bias one must subtract the constant value of reverse bias (1V) to arrive at the actual value of threshold voltage. TableI shows the values of threshold voltage measured from thevarious samples and indicates that it does not change as afunction of F-implant conditions.

Fig. 4(a) shows the– profile of an m NMOStransistor with no F implant which was connected in a gateddiode configuration (source floating) and with V(i.e., in forward bias). Gated diode measurements were madeon a fresh device, then stressed (with the source grounded)at V V for 30 min, followed by post-stress gated diode measurement. The stress condition selectedhere was found to be the worst case stress for a 3.3-V NMOStechnology. Fig. 4(b) shows a similar gated diode profile withthe drain in forward bias for a sample implanted with fluorineat 25 keV/2 10 cm . One of the advantages of performinggated diode measurements under forward bias is that therelative change of current corresponding to the same amountof stress related defects is higher than in the reverse bias mode.We also interpret that since these stress related defects createdby hot-carriers are expected to be close to the drain of thetransistor and lie at the interface, that an enhancement of thecurrent in the accumulation region should be seen. Such atechnique has also been employed in other situations [9], [10].

There are several key observations that can be made fromFig. 4(a) and (b). First, the change in current before and afterthe stress is significantly larger for negative Vg. Secondly,

there is a peak in the accumulation region which is present ataround 0.1 V. Also, the current level for the sample withoutthe F implant is greater than the sample with F implanted in theLDD region. Another observation is that the difference in thecurrents before and after the CHC stress is higher (five times)for the sample without any F implant than that for the samplewith the F implant. This is illustrated in Fig. 5 whereId (

after stress before stress) is plotted as a function ofbetween 0 to –3 V (i.e., in accumulation region).

The first two observation mentioned above lead to the factthat there is significant amount of interface damage [2]. Basedupon the results observed in Figs. 4 and 5 we propose thathot-carrier stressing has indeed generated defects in the Sisurface below the interface and that this damage dominatesthe degradation seen after the stress. It also shows that thesamples which are implanted with F provide better immunitytoward this interface damage than the samples without any Fimplant.

B. Materials Characterization

Secondary ion mass spectroscopy (SIMS) was performedon various samples to understand the effects of fluorine im-plantation on the junction depth. It would also give proof thatthe introduction of F does indeed supress the diffusion of thephosphorus ions. SIMS measurements were performed on sam-ples with only P implant and compared with samples havingadditional F implanted in the LDD regions. The samples werealso annealed under different thermal budgets (i.e., temperatureand time) to see if there was any significant impact. The matrixof samples prepared for the SIMS experiment is shown inTable II.

Fig. 6 is an example of the SIMS doping profile for sampleswith only P-implant at 50 keV/6 10 cm and for thesample with the additional F-implant in the LDD region at35 keV/1 10 cm . The profile for just the F-implant isalso included as a reference. The figure shows the impact ofthe F-implant in the LDD region with the tail of the dopingprofile now being much reduced. The dual peak observed forthe fluorine profile in the Fig. 6 has been well documented andis believed to be due to F pile up near the damaged region dueto ion-implantaion (initial peak) and a pile up of fluorine atresidual lattice defects near the amorphous/crystalline interface[1].

Table III shows the comparison of junction depth (x)for the samples indicated in Table II. Junction depth in thiscase is defined as the depth at an atomic concentration of


(a)

(b)

Fig 4 (a) Forward bias drain current as a function of gate voltage before and after stress for sample without fluorine implant. (b) Forward bias drain currentas a function of gate voltage before and after stress for sample with 25 keV/2� 1015 cm-2 fluorine implant.

cm . An important point to realize is that the valueof reported here is not the electrical junction depth sincethe SIMS profile measures the overall atomic concentrationand not the electrically activated concentration. From Table

III it is seen that the junction depth of the samples withonly P-implant show no significant dependence on the annealconditions e.g., x (Sample 1) x (Sample 3). It is alsonoticed that by comparing each of the samples with and


Fig 5. Comparison of difference between forward bias currents before and after stress as a function of gate voltage.

TABLE IIIJUNCTION DEPTHS OFSAMPLES WITH AND WITHOUT F IMPLANTATION

IN THE LDD REGION OBTAINED FROM SIMS MEASUREMENTS

without the F-implant a significant % change in the junctiondepth is observed, e.g., for the case of Sample 2 the junctiondepth is reduced by almost 40% with the introduction of F-implant in the LDD region. Finally, a comparison of Samples1 and 3 shows a negligible dependence of junction depth onannealing conditions. This would tend to indicate that theintroduction of F aids in the formation of a more shallowjunction (implying that the P dopant diffusion is suppressed)even at a higher anneal temperature and for a longer time.

IV. CONCLUSIONS

A systematic study of fluorine introduced in the LDDregions of NMOS devices has been completed. Results indicatethat fluorine incorporation tends to suppress the phosphorusdopant diffussion resulting in shallower junctions even underthe conditions of high source/drain anneal temperatures forlonger times. This could possibly open up alternative avenuesfor relaxing the thermal budget constraints on smaller geome-try devices. Results of gated diode measurements also indicate

Fig 6. SIMS doping profile for phosphorus and fluorine. P dose was6� 1013 cm�2 at 50 keV while F dose was 1� 1016 cm�2 at 35 keV. Annealtime was 950�C/100 min.

that the leakage current decreases with fluorine incorporation.It was observed that as the fluorine dose increases, the gateddiode leakage decreased resulting in a lower surface recom-bination velocity as well as mid-gap interface density withapparently no change in the flat band voltage.

Since fluorine is introduced only in the LDD regions andnot in the entire device area, the negative effects of fluorineon effective gate oxide thickness, threshold voltage and gate-oxide quality are minimized.


REFERENCES

[1] K. Ohyu, T. Itoga, and N. Natsuaki, “Advantages of fluorine introductionin boron-implanted shallow p+/n junction formation,” Jpn. J. Appl.Phys.,vol. 29, p. 457, 1990.

[2] K. Ohyu, T. Itoga, Y. Nishioka, and N. Natsuaki, “Improvement ofSiO2/Si interface properties using fluorine ion implantation and drive indiffusion,” Jpn. J. Appl. Phys.,vol. 28, p. 1041, 1989.

[3] P. Wright and K. Saraswat, “The effect of fluorine in silicon dioxidegate dielectrics,”IEEE Trans. Electron Devices,vol. 36, p. 879, 1989.

[4] D. G. Lin and T. Rost, “The impact of fluorine on CMOS channel lengthand shallow junction formation,” inIEDM Tech. Dig.,1993, p. 843.

[5] D. G. Lin, T. Rost, H. Lee, D. Lin, A. Tsao, and B. McKee, “The effectof fluorine on MOSFET channel length,”IEEE Electron Device Lett.,vol. 14, p. 469, 1993.

[6] X. Wang, A. Balasinki, and T. Ma, “Pre-oxidation fluorine implantationinto silicon, process related MOS characteristics,” J. Electrochem. Soc.,vol. 139, p. 238, 1992.

[7] A. S. Grove and D. Fitzgerald, “Surface effects on p-n junctions-characteristics of surface space-charge regions under nonequilibriumconditions,”Solid State Electron,vol. 9, p. 783, 1966.

[8] J. Spiegel and G. Declerck, “Theoritical and practical investigation ofthe thermal generation gate controlled diodes,”Solid State Electron,vol.24, p. 869, 1981.

[9] P. Speckbacher, A. Asenov, M. Bollu, F. Koch, and W. Weber, “Hot-carrier-induced deep level defects from gated diode measurements onMOSFET’s,” IEEE Electron Device Lett.,vol. 11, p. 95, 1990.

[10] P. Speckbacher, J. Berger, A. Asenov, F. Koch, and W. Weber, “Thegated diode configuration in MOSFET’s, a sensitive tool for character-izing hot-carrier degradation,”IEEE Trans. Electron Devices,vol. 42,p. 1287, 1995.

Homyar C. Mogul received the Ph.D. degree inelectrical and computer engineering in 1994.

In 1994, he joined Texas Instruments, Inc., DallasTX, where he is presently a staff member in theLogic ASP Productization Group. His interests lie inthe area of process integration and development, es-pecially in the fields of shallow junction technology,process-induced damage, and low-k dielectrics.

Timothy A. Rost received the Ph.D. degree inelectrical and computer engineering from Rice Uni-versity, Houston, TX, in 1991, in the area of ferro-electric thin films and devices.

In 1991, he joined Texas Instruments, Inc., Dallas,TX, where be has been involved in the area ofwafer level reliability. He is presently managing theASP Productization Reliability Engineering effortand is a member of the Group Technical Staff. Heis also the Program Chair of the Dallas Chapter ofthe IEEE Reliability Society, and has published a

number of articles in the areas of semiconductor reliability, semiconductordevice physics, and ferroelectric thin films and applications.

Der-Gao Lin was born in Kaoshong, Taiwan. Hereceived the B.S. degree in material science fromTsing Hwa University in 1977, and the Ph.D. de-gree in electronic materials from the MassachusettsInstitute of Technology, Cambridge, in 1987.

From 1987 to 1992, he worked at Analog Deviceson the project of submicron CMOS device designand process development. From 1992 to 1994, hewas with Texas Instruments, Inc., Dallas, TX, wherehe worked on the process integration of 0.5-�mCMOS and BiCMOS for DSP application and mi-

croprocessor application. Since 1994, he has been with Motorola, Inc., Mesa,AZ, where he is working on the process integration of CMOS with nonvolatilememory device and power device, and the process integration of subhalfmicron CMOS.

advantages of ldd-only implanted fluorine with submicron cmos technologies

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