advances in soi compact modeling -...

MOS-AK Workshop, December 9th 2009, Baltimore

Funded by the European project COMON (Compact Modeling Network)

Contact: [email protected] / [email protected]

ROVIRA I VIRGILI UNIVERSITY COMON

Advances in SOI Compact Modeling

Prof. Benjamin Iñiguez, and Romain Ritzenthaler

Rovira i Virgili University (URV), Tarragona, Spain

MOS-AK workshop, Dec. 9th 2009 (Baltimore, USA)ROVIRA I VIRGILI UNIVERSITY 2

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Outline

Presentation of the COMON project

1. Introduction2. Charge based compact models3. Conformal mapping4. Fourier’s series5. Conclusions


COMON

Outline

Presentation of the COMON project- Who are we?- Goals

1. Introduction2. Charge based compact models3. Conformal mapping4. Others techniques5. Conclusions


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EU COMON Project – Who are we?COMON: COmpact MOdeling Network

“Marie-Curie” Industry-Academia Partneship and Pathways project (IAPP FP7, ref. pro. 218255)

Duration:4 years, started fromDec. 2008.

Coordinator:Prof. B. Iñiguez(URV Tarragona)[email protected]

More information available on our website: http://www.compactmodelling.eu

Melexis Ukraine

Dolphin Integration Grenoble

RFMD UK

AIM-software

Austria Microsystems

AdMOSInfineon Munich

Industrial partners

Academic partners

URV Tarragona

UNIK Kjeller

EPFL Lausanne

TUC Chania

UdS Strasbourg

UCL Louvain-la-Neuve

ITE Warsaw

TUI IlmenauFH Giessen

Associate partners


COMON

EU COMON Project – GoalsTo address the full development chain of Compact Modeling, to develop complete compact models of Multi-Gate MOSFETs (Foundry: Infineon), HV MOSFETs (Foundry: Austriamicrosystems) and III-VFETs (RFMD (UK)).

Development of complete compact models of these types of advanced semiconductor devices.Development of suitable parameter extraction techniques for the new compact models.Implementation of the compact models and parameter extraction algorithms in automatic circuit design tools.Demonstration of the implemented compact models by means of their utilization in the design of test circuits.Validation and benchmarking: compact model evaluation for analog, digital and RF circuit design: convergence, CPU time, statistic circuit simulation.

+ facilitate the mobility of young researchers, secondments ofknowledge, organisation of training courses, ...


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Outline


1. Introduction- SOI technology- Why several gates?- Multi-gate SOI structures benchmark

2. Charge based compact models3. Conformal mapping4. Others techniques5. Conclusions


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1.1 SOI technology

isolation

isolation

Gate

Necessity to reduce the gate length while maintaining a good

electrostatic control and controling the leakages


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1.1 SOI technology

isolation

isolation

Gate Junction leakages

Necessity to control the gate length while maintaining a good



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1.1 SOI technology

isolation

isolation

Gate

High field effects

in the drain

Junction leakages




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1.1 SOI technology

isolation

isolation

Gate

Subthreshold leakages

High field effects

in the drain

Junction leakages




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1.1 SOI technology

isolation

isolation

Gate Junction leakages

High field effects

In the drain

Subthreshold leakagesBuried oxide

SOI allows to continue further the downscaling

with SOI:

Reduced parasitic effects – reduction of

source/channel and drain/channel capacitances

Better electrostatic control

Isolate the electrically active layer from the bulkSOI (Silicon On Insulator) concept




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1.2 Why several gates?

Excellent electrostatic coupling:Short Channel Effects

(SCEs) reductionleakage currents

reduction

Two conduction channelsDouble-gate transistor

good ION

‘Planar double-gate’ architecture

Frontgate

front channelback channel

Silicon Substrate

tSi

Backgate

But self-alignment of the gatesrequired to maintain Double-gateadvantages

idea of vertical gates: FinFET type transistors

Gate misalignment

Frontgate

front channelback channel

Silicon Substrate

tSi

Backgate


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1.2 FinFET-like transistors

Better electrostatic control

FinFETFinFET: vertical Double-gate

gate

drain

source

Hardmask

Triple-gate

Triple-gate (plus avatars ΠFETand ΩFET)

gate

drain

source

Quadruple-gate

Quadruple-gate (or GAA), plus Surrounding-Gate FET

gate

drain

source


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1.3 (non exhaustive) SOI Benchmark


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Outline


1. Introduction2. SOI Charge based compact models

- Surrounding-gate FETs- Double-gate transistors- FinFETs

3. Conformal mapping4. Others techniques5. Conclusions


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2.1 Surrounding-gate FETs

( )kTVq

eqkT

drd

rdrd

−

⋅=+ψ

δψψ 1

2

2

( ) ⎟⎟⎠

⎞⎜⎜⎝

⎛ ++⎟⎟

⎠

⎞⎜⎜⎝

⎛+=−−

0

0

0ox0GS Q

QQlogq

kT QQlog

qkT

CQVVV

∫=DSV

0DS Q(V)dV

LR2πμI

Solving the 1D Poisson’s equation [Jimenez’04], charge control modelobtained:

1D Poisson’s equation (no SCEs):

Drain current calculation:

Comparison model/numerical simulations:drain current ID vs. gate voltage VG

Comparison model/numerical simulations:drain current ID vs. drain voltage VD

[Jimenez’04] D. Jimenez et al., IEEE EDL, vol. 25, no. 8, pp. 571-573, 2004.


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2.1 SGFETs- Capacitance modeling

0 0.5 1 1.5 2-0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

Nor

mal

ized

Cap

acita

nces

CD

G,C

SG

VGS [V]

(a)

(d)

(c)

(b)

Normalized CDG (a, c) and CSG (b, d) withrespect to the gate voltage, for SG MOSFET with VGB=0, VDS=1V (a, b) and VDS=0.05V (c, d); tsi=31nm. L=1 μm. Solid line: analyticalmodel; Symbols: DESSIS-ISE simulation

Normalized CGD (a, b) and CGS capacitance (c, d) with respect to the gate voltage, for SG MOSFET

VDS=0.05V (b,c) and VDS=1V (a,d). Solid line: DESSIS-ISE simulations; Symbol: analytical model.

L=1 μm, tSi=20 nm, tox=2 nm

Analytical expressions [Moldovan’09] of the total electrode charges obtained by integrating the mobile charge density over the channel length. Ward-Duttonpartitioning is assumed. Capacitances are obtained by differentiation of total charges.

[Moldovan’09] O. Moldovan et al., IEEE TED, vol. 54, no. 1, pp. 162-165, 2007.


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2.1 SGFETs, short channels effects

[AbdElHamid’07] H. Abd El Hamid et al., IEEE TED, vol. 54, no. 3, pp. 572-577, 2007.

DIBL vs. channel length LG (radius = 5 and 10 nm). Comparison between model (lines) and numerical

simulations (circles, diamonds)

Subthreshold slope SS vs. channel length LG(radius = 5 and 10 nm). Comparison between

model (lines) and numerical simulations (circles, diamonds)

Inclusion of SCEs [AbdElHamid’07]:

Minimum of potential giving threshold voltage VTH and subthreshold slope SS

),()(),( 21 yxyyx ϕϕϕ +=

)(1 yϕ

),(2 yxϕ

Solution of the 1D Poisson’s equation

Solution of the remaining 2D equation


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2.3 Symmetrical Double-gate FETs

x

y

ΔLS D

G

G

L

tsi

GCA region Saturation region

),()(),( 21 yxyyx ϕϕϕ +=

)(1 yϕ

Electrostatic potential derived from2D Poisson’s equation:

),(2 yxϕ



( ) ( ) ( ) nyxcyxbayx ++=,φ

022

2

=−∂∂

λϕϕ

x ( ) ( )11

21

21

2121

82

2

+−+=⎟⎟

⎠

⎞⎜⎜⎝

⎛+

−+=nnr

tnn

ttt sisi

ox

sioxsi

εε

λ

⎟⎠⎞

⎜⎝⎛ +Δ

+⎟⎠⎞

⎜⎝⎛ +Δ

=λ

λμλ

ϕϕ xLvkxLx satsat sinhcosh)(

( ) ( ) satbdeffS VLx ϕφφϕϕ =+==Δ−=

μϕ sat

Lx

vkdxd

=Δ−=

with

with

Transistor in saturation [Lime’08]:

Determination of saturated length ΔL

NMOS: k=2PMOS: k=1

[Lime’08] F. Lime et al., IEEE TED, vol. 55, no. 6, pp. 1441-1448, 2008.


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2.3 Symmetrical Double-gate FETs

0 1 20

10

20

30

40

(a)

L=50nmtox=2nm

tsi=15nm

tsi=30nm

Vgs-Vt

ΔL (n

m)

Vds (V)

0.0 0.5 1.0 1.5 2.010-5

10-4

10-3

10-2

10-1 (c)

Vg

Symbols = SilvacoLines = ModelVg = 0.4V, 0.75V, 1V, 1.5V

Gd (

A.V -1

)

Vds (V)

Output conductance GD vs. draincurrent VDS . VGS = 0.4, 0.75, 1, and 1.5 V;

tox = 2nm, tSi = 15 nm and L = 50 nm.

Saturation region length ΔL vs. draincurrent VDS . (VGS – VTH = 0.25

and 0.5V; L = 50nm)

Modeling of the saturation for Symmetrical Double-gate FETs


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2.4 FinFETs compact modelling

[Sallese’05] J. M. Sallese et al., Solid State Electronics, vol. 49, no. 3, pp. 485-489, 2005.[Tang’09] M. Tang, F. Prégaldiny, C. Lallement and J.-M. Sallese, IEEE TED, vol. 56, no. 7, pp. 1543-1547, Jul. 2009.[Prégaldiny’06] F. Prégaldiny et al., Int. J. Numer. Model: Elec. Network Dev. Fields, vol. 19, no. 3, pp. 239–256, May 2006.

Relationship between the charge density and the potentials [Sallese’05][Tang’09] :

*This equation is solved by an explicit algorithm [Prégaldiny’06].

Drain current expression:

( ) [ ]gggtochg qqqvvv ⋅+++⋅=−− α14 lnln*

Si

ox

CC

=αwith

mD

mS

q

q

mmm

qqqi ⎟⎠⎞

⎜⎝⎛ ⋅−⋅+⋅+−=

21222 α

αln ( )chtogm vvvfq −−= *withFinFET scheme

Comparison model/numerical simulations:drain current ID vs. gate voltage VG

Comparison model/numerical simulations:drain current ID vs. drain voltage VD


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Outline


1. Introduction2. Charge based compact models3. Conformal mapping

- Application to Fully Depleted single-gate FETs: effect of the Drain through the BOX

- Symmetrical Double-gate FETs 4. Others techniques5. Conclusions


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3.1 What is conformal mapping?

0

B A

ED

C G F

0A B C D E

G

F

Y

xX

y

Conformal transformationx+iy=F(X+iY)

V(x+iy)=W(F-1(x+iy))

V1

V1Complex potentialW(X+iY)

V=0 V=0

V=0

+∞-∞ +∞

+∞

-∞

-∞

0

B A

ED

C G F

0A B C D E

G

F

Y

xX

y

Conformal transformationx+iy=F(X+iY)

V(x+iy)=W(F-1(x+iy))

V1

V1Complex potentialW(X+iY)

V=0 V=0

V=0

+∞-∞ +∞

+∞

-∞

-∞

source drainchannel

BOXCBOX

COX

CBDCBS

source drainchannel

BOXCBOX

COX

CBDCBS

Conformal transformation: transformation of an analytical function in a complex space:

Simplification of the geometry possible

source drainchannel

BOX

tBD

virtual source

virtualdrain

source drainchannel

BOX

tBD

virtual source

virtualdrain

Conservation of the Laplace’s equation in the two spaces

Application to FDSOI structures:


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3.1 FDSOI: effect of the Drain through the BOX

Penetration of the electric field from the drain into the BOX and the substrate

electrostatic potential at the body-BOX interface modified

because of coupling between back and front channels (Lim & Fossum model), front channel properties degraded

‘Drain Induced Virtual Substrate Biasing’ (DIVSB) effect [Ernst’99]

Gate

Source DrainDIBL

Substrate

BOX DIVSB

[Ernst’99] T. Ernst, S. Cristoloveanu, IEEE Int. SOI conf. 1999, pp. 38-39.


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Electrostatic potential modelling in the BOX

3.1 Conformal mapping in the BOX for FDSOI

),,,(),,,(),,(),,,,,( 222 BDDBSSGBGGBDSTOT VVyxVVyxVVyVVVVyx ψψψψ ++=

Bidimensionnal case: fully depleted transistor

source drainchannel

BOX VG2

VB VDVS

VG1

Poisson’s equation solve

Superposition theorem

With the analytical transformation:

Electrostatic problem to solve

Superposition theorem:

⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢

⎣

⎡

−+

−−

=⎪⎩

⎪⎨⎧

⎥⎦

⎤⎢⎣

⎡⎥⎦

⎤⎢⎣

⎡−++

−=

))2

(exp()cos(1

))2

(exp()sin(arctan)

2)((exp1lnRe),( Lx

ty

t

Lxt

ytVVLiyx

tiVVyx

BOXBOX

BOXBOXBD

BOX

BDD ππ

ππ

ππ

πψ

VG2

VB VDVS

xyBOX

body drainsource

Substrate

→+∞-∞←

x=LG/2x=-LG/2

ΨS

ΨD

ΨG2

+

+

ΨTOT =

0 V

0 V

0 V

0 V

VS - VB

VD - VB

VB

VG2


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0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

0 10 20 30 40 50 60 70 80 90 100 110 120 130y [nm]

Elec

tros

tatic

Pot

entia

l[eV

]

BOX channel

LG = 500 nm; W FIN = 30 nm; V D = 1.2 V; V G = 1.2 VLG = 100 nm; W FIN = 500 nm; V D = 1.2 V; V G = 1.2 VLG = 100 nm; W FIN = 500 nm; V D = 1.2 V; V G = 0.1 Vanalytical model

3.1 Conformal mapping in the BOX for FDSOI

Comparison model / numerical simulations (ISE DESSIS)

Exact modellingof the electrostaticpotential

[Ernst’07] T. Ernst, R. Ritzenthaler, O. Faynot, and S. Cristoloveanu, IEEE TED, vol. 54, no. 6, pp. 1366-1375, Jul. 2009

Comparing with numerical simulations (using ISE/Synopsis) [Ernst’07]:


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3.2 Application to Symmetrical Double-gate FETsIn the subthreshold regime (resolution of 2D Laplace’s equation)

for Double-gate FETs [Børli’08] and Schottky Barriers DGFETs [Schwarz’09]:

[Børli’08] H. Børli et al., IEEE TED, vol. 55, no. 10, oct. 2008.[Schwarz’09] M. Schwarz et al., to appear in ISDRS’09 proceedings, Dec.. 2009

2D closed formNo fitting parametersIntrinsically compact expressionExcellent agreement with numericalsimulations

Scheme and core formula (‘Poisson’s integral’)

Potential in the channel obtained for a step of gate bias VG withmodel (solid lines) and numerical simulations (points.

Drain voltage VD = 0 V (a) and 1 V (b). LG = 22 nm, tSi = 10 nm.

(a)

(b)


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Outline


1. Introduction2. Charge based compact models3. Conformal mapping4. Fourier’s series development

- Triple-gate FETs 2D interface coupling- Π-gate FETs 2D interface coupling

5. Conclusions


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4.1 Triple-gate FETs 2D interface coupling

BOXWFIN

HFIN

LG

Source

Drain

Gate

Substrate

VG2

VG1

eOX2

Si

eOX1

x

yz

BOXWFIN

HFIN

LG

Source

Drain

Gate

Substrate

VG2

VG1

eOX2

Si

eOX1

BOXWFIN

HFIN

LG

Source

Drain

Gate

Substrate

VG2

VG1

eOX2

Si

eOX1

x

yz

H

0

W0

VG1

VG2

BOX

φS1

φS2

x

ySi

Front channel

Lateral symmetry

H

0

W0

VG1

VG2

BOX

φS1

φS2

x

ySi

Front channel

Lateral symmetry

Resolution of 2D Laplace’s equation using series’s development andGauss’s theorem at the interfaces:

analytical (but notcompact) modellingof the thresholdvoltage

480

500

520

540

560

580

600

620

640

-15 -10 -5 0

Back-gate bias VG2 [V]

Fron

t-gat

e th

resh

old

volta

ge V

TH1 [

mV]

eOX1 = 2 nm, eOX2 = 100 nmH = 30 nm, eOV = 20 nm

W = 10 μm, 100 nm, 70 nm, 50 nm, and 30 nm

Comparison front-gate threshold voltage VTH1 vs. back-gate bias VG2 with model (lines)and numerical simulations (squares)

Triple-gate FET Triple-gate FET, transversal cross-section


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4.2 Π-gate FETs 2D interface couplingTriple-Gate

Substrate

Pi-Gate

overetch

Buried Oxide(BOX)

Si Si

Triple-Gate

Substrate

Pi-Gate

overetch

Buried Oxide(BOX)

Si Si

50

60

70

80

90

100

110

120

130

140

150

20 30 40 50 60 70 80 90

Gate Length LG [nm]Su

bthr

esho

ld S

lope

SS

[mV/

dec] Double-gate

Triple-gatePi-FETFour gates GAA

WFIN = 30 nmHFIN = 30 nmVD = 100 mV

HfO2 TiN

SiO2

Si

SiO2Poly

HfO2 TiN

SiO2

Si

SiO2Poly

Subthreshold slope SS vs. gate lengthLG for TG and Pi-FETs (from [Park’01])

Tranversal cross-section for Triple-and Pi-gate FETs

[Jahan’05] C. Jahan et al., VLSI tech. dig., 2005.[Frei’04] J. Frei et al., IEEE Electron Device Letters, vol. 25, no. 12, pp. 813-816, 2004. [Park’01] J.-T. Park, J.-P. Colinge, C.H. Diaz, “Pi-Gate SOI MOSFET”, IEEE Electron Device Letters, vol. 22, no. 8, pp. 405-406, 2001.

The process-inducedgate overetch in theBOX is improving thedevice scalability

LETI[Jahan’05]

TI / Infineon[Frei’04]


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4.2 Π-gate FETs 2D interface coupling

0.4

0.45

0.5

0.55

0.6

0.65

0.7

0.75

0.8

-15 -10 -5 0 5


Fron

t-gat

e th

resh

old

volta

ge V

TH1

[V]

eOX1=1.95 nm, eOX2 = 100 nmH = 26 nm, eOV = 30 nm

W = 2000, 500, 250,100 and 50 nm

VG2 = VFB2 + φST

VG1 = VFB1 + φST

back-gate invertedat VG2 = 0V

HfO2 TiN

SiO2

Si

SiO2Poly

HfO2 TiN

SiO2

Si

SiO2Poly

0.4

0.45

0.5

0.55

0.6

0.65

0.7

0.75

0.8

-15 -10 -5 0 5


Fron

t-gat

e th

resh

old

volta

ge V

TH1

[V]

eOX1=1.95 nm, eOX2 = 100 nmH = 26 nm, eOV = 30 nm

W = 2000, 500, 250,100 and 50 nm

VG2 = VFB2 + φST

VG1 = VFB1 + φST

back-gate invertedat VG2 = 0V

HfO2 TiN

SiO2

Si

SiO2Poly

HfO2 TiN

SiO2

Si

SiO2Poly

Comparison front-gate threshold voltage VTH1 vs. back-gate bias VG2 with model (lines) and experimental

measurements (squares) [Ritzenthaler’09]

Perfect agreement analytical model/experimental measurements

[Ritzenthaler’09] R. Ritzenthaler, O. Faynot, S. Cristoloveanu, and B. Iniguez, ISDRS conference proceedings, 2009.


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4.2 Π-gate FETs 2D interface coupling

0.5

0.55

0.6

0.65

0.7

0.75

0.8

-15 -13 -11 -9 -7 -5 -3 -1


Fron

t-gat

e th

resh

old

volta

ge V

TH1 [

V]

H = 26 nm, eOX1 = 2 nm, eOX2 = 100 nmeOV = 30 nm, εOX1 = εOX2 = εBOX = 3.9

W = 2000, 500, 250,100 and 50 nm

0

0.005

0.01

0.015

0.02

0.025

1.E-08 1.E-07 1.E-06 1.E-05

Fin width W [nm]

Inte

rface

cou

plin

g co

effic

ient

[1]

1 D limit (Lim and Fossum model)

model PiFET

experimental PiFET

model TGFET

compact modelof the thresholdvoltage taking intoaccount the effect ofthe overetch

Comparison coupling coefficient vs. gate width W usingmodel (lines) and experimental measurements (squares)

Coupling coeff.: slope of VTH1(VG2)when the back-gate is depleted.

Good agreement betweenexperimental measurements and model.

Triple-gate FETs are slightly more sensitive to back-gate influence than Pi-gate FETs.

Comparison front-gate threshold voltage VTH1 vs. back-gate bias VG2 with model (lines), compact model

(dashed lines) and experimental measurements (squares)


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Outline


1. Introduction2. Charge based compact models3. Conformal mapping4. Others techniques5. Conclusions


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5. ConclusionsRecent developments in compact/analytical modeling from COMONpartners presented:

Compact charge based models in Multiple-Gate MOSFETs (DG MOSFETs, GAA MOSFETs, FinFETs):- A core model, developed from a unified charge control model

obtained from the 1D Poisson’s equation (using some approximations in the case of DG MOSFETs).

- 2D or 3D scalable models of the short-channel effects (thresholdvoltage roll-off, DIBL, subthreshold swing degradation andchannel length modulation), developed by solving the 2D or 3D Poisson’s equation using appropriate techniques.

Conformal mapping technique presented, with applications to the case of fringing fields in FDSOI, and Schottky Barriers DGFETs.

Series´s development used to develop compact threshold voltage models for 2D interface coupling in Triple-gate and Pi-FETs architectures


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Thank you for your attention!Special thanks to all the contributors:

URV Tarragona (Spain): Prof. B. Iñiguez, Dr. F. Lime, Dr. O. Moldovan, Dr. H. Abd El Hamid, Dr. B. Nae, G. Darbandy, M. Cheralathan.

FH Giessen (Germany): M. Schwarz, M. Wiedemann, Prof. A. Kloes.

Strasbourg University (France): M. Tang, Dr. F. Prégaldiny, Prof. C. Lallement.

EPFL Lausanne (Switzerland): Dr. J.-M. Sallese

and special acknowledgments to:LETI Grenoble (France): Dr. O.Faynot, Dr. T. ErnstMinatec Grenoble (France): Prof. Sorin CristoloveanuTyndall Cork (Ireland): Prof. J.-P. Colinge


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Back-up slides


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Triple-gate FETs short channel effectsz

x

yO

TeffHeff

Leff

z

x

yO

TeffHeff

Leff

Subthreshold slope SS vs. channel length LG.Comparison between model (lines) and numerical

simulations (markers)

Inclusion of SCEs [AbdElHamid’07-2]:

Conduction path approach and virtualcathode position calculation.

),()(),( 21 yxyyx

[AbdElHamid’07-2] H. Abd El Hamid et al., IEEE TED, vol. 54, no. 9, pp. 2487-2493, 2007.

ϕϕϕ +=

)(1 yϕ

),(2 yxϕ




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advances in soi compact modeling -...

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