7/29/2019 Advanced Topics in Logic Design Final Exam

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Cairo University

Faculty ofEngineering

Department of Electronics

and Electrical

Communications

Engineering

Advanced Topics in Logic DesignFourth Year 2012/2013 - Term 1

Final ExamJanuary 20132 Hours

Attempt ALL Questions

Question 1 Boolean Function Decomposition & Boolean SAT

a. [2 marks] Write the general expression for the Shannon Function Decomposition of a Booleanfunction fofn Boolean variables x1, x2, ., xn about the splitting variable xi, where 1 i n, in

terms of its positive and negative cofactors with respect to xi.

b. [2 marks] Show that the Boolean function given in part (a) is independent ofxi if its positive andnegative cofactors with respect toxi are logically equivalent.

c. [3 marks] Show that the Boolean function given in part (a) is negative unate with respect toxi if allminterms in its positive cofactor with respect to xi are also minterms of its negative cofactor with

respect toxi, and the positive and negative cofactors with respect toxi are not logically equivalent.

d. [3 marks] If the universal quantification of the Boolean function given in part (a) with respect to xi isfound to be unsatisfiable, can there exist a product term in any SOP of the function that does not

contain either the positive or negative literal ofxi? Explain the reason, and give an example to

illustrate the answer.

e. [5 marks] Use Davis-Logemann-Loveland Depth-First Search Algorithm to solve the following SATproblem: (x1 + x3) (x2 + x3) (x1 + x4) (x2 + x4) (x1 + x3 + x4) (x1 +x2 + x4).

Question 2 Boolean Matching

a. [3 marks] Write an expression for the total number of mappings that can be considered whenattempting to find a possible matching for a pair of Boolean functions in terms of the number of

Boolean variables of the functions n. Can a pair of Boolean functions be matched if they have

different number of variables? What are the drawbacks of the Canonical Boolean Matching

algorithms based on truth tables and table lookup?

b. [4 marks] Compute the Unateness and the Size of the Onset signatures of the pair of Booleanfunctionsf=x1x3 +x2 +x1x3 andg=y1y2 y3 +y1 y2y3.

c. [3 marks] Find a possible matching for the two functions given in part (b) if it exists.

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Question 3 Logic Optimization

a. [4 marks] Explain how to check whether cube C in coverF of the Boolean function f is eitherredundant or irredundant. Illustrate that by checking whether the cube C= x1x3 in the following

coverF= {x1x2,x2x4,x3x4,x1x3,x2x3} is redundant or irredundant.

b. [6 marks] Illustrate how the Quine-McClosky procedure is applied to generate all prime cubes of theBoolean function fwhose on-set is given by the coverF= {x1x2x4,x2x3x4} and dont care set is

given by the coverD = {x1x2,x2x4}. Write the covering table of the function and show how it is

used to generate the minimum-size cover.

c. [5 marks] Illustrate how the minimum column cover is used to generate the complement of the unateBoolean functionf=x1x3 +x2x4 +x1x4 +x2x3.

Question 4 ROBDD

a. [2 marks] Explain the tradeoff between using canonical data structures such as truth tables and binarydecision diagrams and non-canonical data structures such as covers to represent Boolean functions.

b. [4 marks] Explain how the if-then-else (ITE) operator is used to build a reduced-ordered binarydecision diagram representation of a Boolean function f. Illustrate that by sketching the ROBDD

representation of a 2-input NOR Boolean function.

c.

[4 marks] Show that the ROBDD representation of an n-input XOR Boolean function has n levelsand (2n-1) nodes. Illustrate how the onset of the 4-input XOR Boolean function is generated from its

ROBDD representation.

Question 5 AIG

a. [2 mark] Use De Morgans law to design an AIG with the minimum number of levels for a 4-inputOR gate.

b. [4 marks] Construct an AIG representation with the minimum number of level for a 42 encoder.c. [4 marks] Show how construct an AIG representation for a 5-input majority encoder.

Question 6 Logic Difference & Incremental Synthesis

a. [4 marks] Describe the main phases of the DeltaSyn incremental synthesis techniques used tominimize the logic difference between an original design and the desired design modified by

Engineering Change Orders CEO.

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b. [6 marks] Illustrate how the DeltaSyn technique is applied to minimize the logic difference betweenthe desired outputy and the original modely* whose schematics are given in the following Figure.