advanced pcb routing

Advanced PCB Routing Technologies

Advanced PCB Routing, EDA Tech Forum 20072

Agenda

Challenges in PCB routingCore PCB designBus path designAdvanced fabrication technologiesTeam collaboration


Interconnect Routing Challenges

Design constraints— Too many; sometimes conflicting; limit flexibility— Must understand rules to know when they can be

bentBus path design

— Parallel and serial structuresAdvanced fabrication technologies

— Impact of HDI, flex, embedded passivesEmphasis on reduced design time

— Need for team collaboration and design reuse


Current State of PCB Design

Many designs involve significant interactive labor— Interactive labor for the sake of “art” is diminishing— Use of automation within interactive tasks is evolving

Auto-routers often used for place/routing strategy evalsDesigners iterate between automatic & interactive tasks

— Auto route typically not a push-button solutionHigh volume of design constraints demand a high level of creativity from designersEngineering and layout designer roles are blendingThe traditional “one layout, one designer” methodology is being challenged


Agenda



PCB Layout

AutoActive environment is a next-generation, best-in-class solution that enables designers to break through the technology wall and create today’s most challenging and complex PCB designs

Ease of use + advanced technology support + superior routing performance= Increased designer productivity= Increased design quality= Decreased design times


PCB Layout

AutoActive design environment— Auto-routing technology combined

with interactive editing capabilities— Correct-by-construction

methodology— Single layout environment

Supports constraints for advanced interconnect and high-speed design technologiesCommon user interfaceIntegrated design processSuperior router setup and performance


Productivity, Power and Value

Increased productivity reduces time to market— Single PCB editing environment (no translation)— No artificial limits to constrain design— Ease of use (common Windows GUI, usage model)— Tight integration with system design environment— Router performance (speed, completion rates)

Improved design quality / manufacturabilityAdvanced technology support facilitates state-of-the-art designs

— Upgrade path as design complexity increases


Agenda



Differential Pairs and Multi-Gigabit

Frequency

~ 10 MHz

C2

CO

RE

C1

CO

RE

C2

CO

RE

C1

CO

RE

Synchronously clocked “parallel” architectures(primarily single-ended)

C1 C2

+

-tx rx

+

-

CO

RE

CO

RE

I/O I/O

C1 C2

+

-tx rx

+

-

CO

RE

CO

RE

I/O

C1 C2

+

-tx rx

+

-

CO

RE

CO

RE

I/O I/O

•Asynchronously clocked “serial” architectures (primarily differential pair)

•SERDES (serializer – at driver; deserializer – at load)

0.5 GHz Multi-GHz


Traditional Parallel Buses Still Exist!

Serial interconnect only make up 10-20% of designsParallel structures have long been associated with the “artistry” of PCBs

— Improved performance (matched timing & impedance)— Improved ECO-ability

Serial usage— Above 1GHz; low power; high noise immunity; high data

rates; telecom, networking, mil/aeroParallel usage

— Below 500MHz; cheap; high noise margins; simpler device architecture; consumer electronics, automotive, industrial


Parallel Bus Routing

Without adequate constraints, auto routers do this …but designers would prefer this


Parallel Bus RoutingTypical Design Process

Design engineer— Typically sketches the physical bus

systems and sub-systems architecture on paper

— Specific placement and bus interconnect guidelines remain in hard copy form with little automation

Board designer— Looks for potential routing patterns that flow from

component to component— Plans ahead, knowing why a particular group of

traces must route in a certain path on a specific layer


Parallel Bus RoutingTopology-Driven Design

Planning Routing

Old methodology

Planning Routing

New methodology


Parallel Bus Routing Special Routing Controls

Bus with shieldingDesignated high-speed tuning areas


Constraints

Topology Plan and Routing

Layout

Design Iterations and Reuse

Topology plan and routing becomes part of design database

— Design team can iterate to best solution without re-entry –performance and cost optimization

— ECOs are easily implemented –reduced design cycle time

— Database can be re-used in future products, “design reuse” –productivity and quality

Schematic

Designdatabase


Benefits of Topology Routing

Reduced product design cycle time— Capitalize on auto-routing speed

More compact designs— Mimics the expertise of an experienced designer— More functionality in smaller spaces

Higher quality designs— Manufacturability— Performance

Efficient re-use of design databases in future productsEngineer to designer communication

— No more paper or over the shoulder!


Agenda



High-Density InterconnectBenefits

Product size reductionIncreased wiring densityHigher density at a lower costImproved electrical performanceImproved thermal efficiency Greater design efficiencyIncreased flexibility Improved design time Lower RFI/EMILayer reductionImproved yield

1.6 mm(.064")

0.05 mm (.002")


High-Density InterconnectThings to Consider

Creation of complex BGA packages Via structure

— Stacked, adjacent— Combo with vias through laminate

Localized rules under components to facilitate escape paths

Laminatelayers

Laminatelayers

High pin-count ball grid array (BGA)

HDI /microvia

layers


HDI /microvia

layers


HDI /microvia

layers

Coincident InsetAdjacent


High-Density InterconnectThings to Consider

Via fanout— Via-in-pad; patterns— Routing schemes


Embedded PassivesBenefits

Increased design density Reduced system costReduced system weightReduced board areaIncreased performanceImproved reliabilityIncreased board yieldIncreased value flexibilityIncreased functionalityReduced assembly time

Source: Ohmega Technologies, Inc.


Embedded Passive DesignThings to Consider

Parameter-driven device synthesis— Automatic geometry creation

Material characteristics library— Input via design kits

Trade-off tools for discrete vs. embedded

— Multiple materials— Design optimization

Manufacturing data generationValue of automation

— Increase throughput— Minimize risks, increase quality— Optimize cost, materials


Agenda



Collaboration Drivers

Optimize system performance— Efficiently leverage unique skill sets of team

Reduce design cycle time— Leverage local or globally dispersed teams for parallel

/ concurrent designIncrease resource management flexibility

PCB layoutPCB layout




Design entryDesign entry


RF layoutRF layout

Digital layoutDigital layout

Analog layoutAnalog layout

Analog layoutAnalog layout


Design entryDesign entryDigital layoutDigital layout RF layoutRF layout


Layout Collaboration Methodologies

Outsourcing— Design must be partitioned (isolated), then

merged when completeExpanded team

— Traditionally done with multiple shifts (at single location or “follow-the-sun”)

— Can also use the partitioning model

Digital Designer

Analog DesignerDrafter

Electrical Engineer


Layout Collaboration Challenges

Most layout designers are used to driving start to finish— Consistent planning and ownership— Undisciplined “teamwork” may actually be “redesign”

Managing design partitioning and collisions

JoeJoe

BillBill


Evolving CollaborationResource Management

True simultaneous design— Link designers over local or global networks— Dynamically display peer results— Automatically keep database current— Reduce design times proportionally with the

number of designers working concurrently— Share design tasks and pressures across the team— Use any time in the design flow

Pre-placement, ECOs, documentation, etc.— Design review by specialists, management,

manufacturing


Evolving CollaborationResource Management

Utilize networked computing resources— Single designer harnessing the power of

multiple CPUs to accelerate auto-routing— Geographically distributed

computational resources— Evaluate multiple placement /

routing strategies— Automated distribution process

not efficient for smaller designs


Conclusion

Design challenges— Increasing and conflicting constraints for

performance and manufacturing— Drive to reduce design time

Designers and their tools are evolving— Continued iteration between interactive &

automatic tasks— Blending of engineering and layout designer roles

New breed of planning (design abstraction) tools emerging

— Concept of “resource management” is changing

advanced pcb routing

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