advanced embedded system design on zynq using vivado workshop zybo course...

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© Copyright 2013 Xilinx

Advanced Embedded System Design on Zynq Using Vivado Workshop ZYBO

COURSE DESCRIPTION This workshop provides participants the necessary skills to develop complex embedded systems and enable them to improve their designs by using the tools available in Vivado. It also helps developers understand and utilize advanced components of embedded systems design for architecting a complex system in the Zynq™ All Programmable System on a Chip (SoC). . 1. Install Xilinx software

Professors may submit the online donation request form at http://www.xilinx.com/member/xup/donation/request.htm to obtain the latest Xilinx software. The workshop was tested on a PC running Microsoft Windows 7 professional edition. Vivado 2013.4 System edition

2. Setup hardware

Connect ZYBO a. Set the power supply jumper to USB so the board can be powered up and laboratory

assignments can be carried out using single micro-usb cable b. Connect micro USB cable between PROG UART port of ZYBO and PC

3. Install distribution

Extract the labsource.zip file in c:\xup\adv_embedded directory. This will generate sources and labs folder. The labdocs.zip file consists of lab documents in PDF format. Extract this zip file in c:\xup\adv_embedded\ directory or any directory of your choice.

4. For Professors only

Download the labsolution.zip and docs_source.zip files using your membership account. Do not distribute them to students or post them on a web site. The docs_source.zip file contains lab documents in Microsoft Word and presentations in PowerPoint format for you to use in your classroom.

5. Get Started Review the presentation slides (see course agenda) and step through the lab exercises (see lab descriptions) to complete the labs.

http://www.xilinx.com/member/xup/donation/request.htm

README

© Copyright 2013 Xilinx

COURSE AGENDA Day 1 Agenda Day 1 Materials

Class Intro 01_class_intro.pptx Embedded System Design Review 11_embedded_system_design_review.ppt x Lab 1: Building a Complete Embedded System 11a_lab1_intro.pptx

Lab1.docx Advanced Zynq Architecture 12_Advanced_Zynq_Architecture.pptx System Debugging 13_System_Debugging.pptx Lab 2: Debugging using Vivado Logic Analyzer 13a_lab2_intro.pptx

Lab2.docx Memory Interfacing 14_Memory_Interfacing.pptx Lab 3: Extending Memory Space with Block RAM 14a_lab3_intro.pptx

Lab3.docx Day 2 Agenda Day 2 Materials

Interrupts 15_ Interrupts.pptx Low Latency High Bandwidth 16_Low_Latency_High_Bandwidth Lab 4: Direct Memory Access using CDMA 16a_lab4_intro.pptx

Lab4.docx Configuration and Bootloading 17_Configuration_and_Bootloading.pptx Lab 5: 17_Configuration_and_Bootloading 17a_lab5_into.pptx

Lab5.docx Profiling and Performance Improvement 18_Profiling_and_Performance_Improvement.pptx Lab 6: Profiling and Performance Tuning 18a_lab6_intro.pptx

Lab6.docx LAB DESCRIPTIONS Lab 1 - Create a complete processor system with built-in processor and IP in programmable logic. Lab 2 - Insert various ChipScope cores to debug/analyze system behavior. Lab 3 - Instantiate AXI BRAM controller and BRAM to extend address space and run application from it. Lab 4 - Perform DMA operations between various memories using AXI CDMA controller in polling and interrupt modes. Lab 5 - Create images to boot off the SD card and QSPI flash. Load previously generated hardware bitstreams and executable and execute desired application. Lab 6 - Profile an application performing a function both in software and hardware. 6. Contact XUP

Send an email to [email protected] for questions or comments

mailto:[email protected]

Lab Workbook Building a Complete Embedded System

www.xilinx.com/support/university ZYBO 1-1 [email protected] © copyright 2014 Xilinx

Building a Complete Embedded System Introduction This lab guides you through the process of using Vivado and IP Integrator to create a complete ARM Cortex-A9 based processor system targeting the ZYBO Board. You will use the Block Design feature of the IP Integrator to add and configure the PS7 and IP to create the hardware system and SDK to create an application to verify the design functionality.

Objectives After completing this lab, you will be able to: • Create an embedded system design using Vivado and SDK flow • Configure the Processing System (PS) • Add Xilinx standard IP in the Programmable Logic (PL) section • Use and route the GPIO signal of the PS into the PL using EMIO • Use SDK to build a software project and verify the design functionality in the hardware by using the

ZYBO

Procedure This lab is separated into steps that consist of general overview statements that provide information on the detailed instructions that follow. Follow these detailed instructions to progress through the lab.

This lab comprises eight primary steps: You will create a top-level project using Vivado, create the processor system using the IP Integrator, add two instances of the GPIO IP, validate the design, generate the bitstream, export to the SDK, create an application in the SDK, and, test the design in hardware.

Design Description In this lab, you will design a completed embedded system consisting of the ARM Cortex-A9 processor SoC, two standard GPIO IPs to connect to four on-board LEDs and their corresponding switches. The following block diagram represents the completed design (Figure 1).

Figure 1. Completed Design

Building a Complete Embedded System Lab Workbook

ZYBO 1-2 www.xilinx.com/support/university [email protected] © copyright 2014 Xilinx

General Flow for this Lab

Create a Vivado Project Step 1

1-1. Launch Vivado and create an empty project targeting the ZYBO board (having xc7z010clg400-1 device) and using the VERILOG language.

1-1-1. Open Vivado 2013.4 by selecting Start > All Programs > Xilinx Design Tools > Vivado 2013.4 > Vivado 2013.4

1-1-2. Click Create New Project to start the wizard. You will see the Create A New Vivado Project dialog box. Click Next.

1-1-3. Click the Browse button of the Project Location field of the New Project form, browse to c:\xup\adv_embedded\labs, and click Select.

1-1-4. Enter lab1 in the Project Name field. Make sure that the Create Project Subdirectory box is checked. Click Next.

Figure 2. Project Name Entry

Step 1: Create a Vivado Project

Step 2: Create the

System using IP Integrator

Step 3: Add Two

Instances of GPIO

Step 4: Validate the

Design

Step 5: Generate the

Bitstream

Step 6: Export the Design to

SDK

Step 7: Create an

Application in SDK

Step 8: Test in

Hardware



1-1-5. Select the RTL Project option in the Project Type form, and click Next.

1-1-6. Select Verilog as the Target language and Verilog as the Simulator language in the Add Sources form, and click Next.

1-1-7. Click Next two times.

1-1-8. In the Default Part form, select Parts, and using various filters shown in the figure below, select xc7z010clg400-1 part as it is on the ZYBO board. Click Next.

Figure 3. Board Selection

1-1-9. Click Finish to create an empty Vivado project.

Creating the Hardware System Using IP Integrator Step 2

2-1. Create block design in the Vivado project using IP Integrator to generate the ARM Cortex-A9 processor based hardware system.

2-1-1. In the Flow Navigator, click Create Block Design under IP Integrator.

2-1-2. Name the block as system and click OK.

2-1-3. Click on Add IP in the message at the top of the Diagram panel.

2-1-4. Once the IP Catalog is open, type zy into the Search bar, and double click on ZYNQ7 Processing System entry to add it to the design.



2-1-5. Double click on the Zynq block to open the Customization window for the Zynq processing system.

A block diagram of the Zynq should now be open, showing various configurable blocks of the Processing System.

At this stage, designer can click on various configurable blocks (highlighted in green) and change the system configuration.

Figure 4. Zynq System Configuration View

2-1-6. Click on the Import XPS Settings button on the top tools bar to import the setting for the ZYBO board using the provided xml file.

2-1-7. Click on the browse button, browse to c:\xup\adv_embedded\sources, select the provided ps7_system_prj.xml file, and click OK.

2-1-8. Click OK.

Notice now the Customization window shows selected peripherals (with tick marks).

2-1-9. Click OK to close the Customization window for now.



2-2. Configure the I/O Peripherals block to have UART 1, SD 0, and GPIO support. Route 1-bit wide GPIO_I port to the EMIO so it can be connected to a user IO pin.

2-2-1. Click on Run Block Automation and select /processing_system7_0

2-2-2. Click OK when prompted to run automation

Once Block Automation has been complete, notice that ports have been automatically added for the DDR and Fixed IO, and some additional ports are now visible. The imported configuration for the Zynq related to the ZYBO board has been applied which will now be modified.

2-2-3. In the block diagram, double click on the Zynq block to open the Customization window for the Zynq processing system.

2-2-4. A block diagram of the Zynq should now be open, showing various configurable blocks of the Processing System.

At this stage, the designer can click on various configurable blocks (highlighted in green) and change the system configuration.

2-2-5. Click on one of the peripherals (in green) in the IOP Peripherals block, or select the MIO Configuration tab on the left to open the configuration form.

2-2-6. Expand the I/O Peripherals.

2-2-7. Uncheck all the peripherals except UART 1 and SD 0.

We will use SD interface in Lab 5, hence we are keeping it enabled here.

2-2-8. Expand GPIO and check GPIO MIO.

Figure 5. Selecting UART 1 and GPIO Peripherals of PS



2-2-9. Route the PS section GPIO of a 1-bit width to the PL side pad using the EMIO interface by doing the following:

o Expand the GPIO branch

o Select the check-box of the EMIO GPIO (Width) to use the EMIO GPIO. Then click in the right-column and select 1 as the width

Figure 6. Routing GPIO to PL

2-3. Deselect TTC device.

2-3-1. In the MIO Configuration panel, expand the Application Processing Unit and uncheck the Timer 0.

Figure 7. Deselecting Timer

2-3-2. Click OK.

The configuration form will close and the block diagram will be updated as shown below.

Figure 8. ZYNQ7 Processing System configured block

2-4. Add one instance of GPIO with width of 4 bits and name the instance as sw_8bit. Connect the instance to the processing_system7_0 instance.

2-4-1. Click the Add IP icon and search for AXI GPIO in the catalog.

2-4-2. Double-click the AXI GPIO to add an instance of the core to the design.

2-4-3. Click on the AXI GPIO block to select it, and in the properties tab, change the name to sw_4bit.



2-4-4. Double click on the AXI GPIO block to open the customization window.

If during the project creation, the target board had been selected then Vivado would have knowledge of available resources on the board. You could then have selected peripherals and generated the corresponding constraints based on the selected board.

Since the ZYBO board was not selected during the project creation, the GPIO has to be configured and the constraints will have to be explicitly added.

2-4-5. Select the All Inputs option as the switches are input only type devices. Also, set the GPIO width to 4 as the ZYBO board has four switches.

Notice that the peripheral can be configured for two channels, but, since we want to use only one channel without interrupt, leave the GPIO Supports Interrupts and Enable Channel 2 unchecked.

2-4-6. Click OK to save and close the customization window

2-4-7. Notice that Design assistance is available. Click on Run Connection Automation, and select /sw_4bit/S_AXI

2-4-8. Click OK when prompted to automatically connect the master and slave interfaces

Notice two additional blocks, Processor System Reset, and AXI Interconnect have automatically been added to the design. (The blocks can be dragged to be rearranged, or the design can be redrawn.)

2-5. Add another instance of GPIO with width of 4 bits. Name the instance as led_4bit and connect it to the processing_system7_0 instance.

2-5-1. Similarly, add another instance of the GPIO peripheral.

2-5-2. Change the name of the block to led_4bit.

2-5-3. Configure it to be all outputs with width of 4.

2-5-4. Click on Run Connection Automation, and select /led_4bit/S_AXI.

2-5-5. Click OK when prompted to automatically connect the master and slave interfaces.

Notice that the AXI Interconnect block has the second master AXI (M01_AXI) interface added and connected to the S_AXI interface of the led_4bit block.

2-6. The dip switch and led instances will be connected to corresponding pins on the ZYBO board. This can be done manually, or using Designer Assistance. The location constraints will have to be explicitly added as the tools are not aware of the ZYBO board. You will add the provided constraints. Normally, one would consult the ZYBO board user manual to find this information.

2-6-1. In the Diagram view, notice that Designer Assistance is available. Since the tools are not board aware we will ignore it, and we will manually create the ports and connect.



2-6-2. Right-Click on the gpio port of the sw_4bit instance and select Make External to create the external port. This will create the external port named gpio and connect it to the peripheral.

2-6-3. Select the gpio port and change the name to sw_4bit in its properties form.

The width of the interface will be automatically determined by the upstream block.

2-6-4. Similarly, create the external port on the led_4bit block and naming it as led_4bit.

2-6-5. Right-click on the GPIO_0 pin of the processing_system7_0 instance, and select Make External.

2-6-6. Select the GPIO_0 connector, and change the name to BTN0 in its properties form.

At this stage the design should look like as shown below.

Figure 9. The completed design

2-7. Verify that the addresses are assigned to the two GPIO instances and validate the design for no errors.

2-7-1. Select the Address Editor tab and see that the addresses are assigned to the two GPIO instances. They should look like as follows.

Figure 10. Assigned addresses

The addresses should be in the 0x40000000 to 0xbfffffff range as the instances are connected to M_AXI_GP0 port of the processing system instance.

2-7-2. Select Tools > Validate Design to run the design rule checker and to make sure that there are no design errors.



2-7-3. Select File > Save Block Design to save the design.

2-7-4. Using the Windows Explorer, browse to the c:\xup\adv_embedded\labs\lab1 directory and observe the various directories created within.

Under the lab1 folder, lab1.data and lab1.srcs directories are created along with the lab1.xpr (Vivado project) file. The lab1.data directory consists of constrs_1, sources_1, sim_1, and wt directories carrying project information in xml format.

The lab1.srcs directory structure consists of the sources_1 > bd > system directories. Under the system directory, the ip directory is created along with the system.bd files amongst others. The ip directory consists of directories of various instances in the design.

Figure 11: Directories Created by Vivado

2-8. Add the provided Xilinx Design Constraints file (lab1.xdc), which contains the led, switches, and BTN0’s location constraints, to the project.

2-8-1. Click the Add Sources button in the Flow Navigator.

2-8-2. Select Add or Create Constraints, and click Next.

2-8-3. The Add or Create constraints window will appear. Click Add Files… and browse to the c:\xup\adv_embedded\sources\lab1 directory.

2-8-4. Select the lab1.xdc file and click OK.

2-8-5. Click Finish to add the constraint file to the project.



Generate the Bitstream Step 3

3-1. Generate the output products. Create the top-level HDL of the embedded system. Generate the bitstream.

3-1-1. In the sources panel, right-click on system.bd, and select Generate Output Products … and click Generate to generate the Implementation, Simulation and Synthesis files for the design

3-1-2. Right-click on system.bd, and select Create HDL Wrapper… to generate the top-level Verilog model. Leave the Let Vivado manager wrapper and auto-update option selected, and click OK.

Figure 12. Selecting the system design to create the wrapper file

3-1-3. The wrapper file, system_wrapper.v, is generated and added to the hierarchy.

Figure 13. Design Hierarchy View

3-1-4. Click on the Generate Bitstream in the Flow Navigator pane to synthesize and implement the design, and generate the bitstream.

3-1-5. Click Yes to run the necessary processes.

3-1-6. Select the Open Implemented Design option when the bitstream generation is complete, and click OK.

It is necessary to open the implemented design in order to include the generated bitstream when exporting the design to the SDK.



Export the Design to the SDK Step 4

4-1. Start the SDK by exporting the implemented design.

4-1-1. Start the SDK by clicking File > Export > Export Hardware for SDK.

The window shown in figure below will appear. Click on the Launch SDK box to launch the SDK session. Then click OK.

Note: Since we have hardware in the PL and we have generated the bitstream, and have opened the implemented design, the Include Bitstream option check box is selected.

Figure 14. Exporting to SDK

Generate an Application in SDK Step 5

5-1. Generate a software platform (board support package) project with default settings and default software project name.

5-1-1. In SDK, select File > New > Board Support Package.

5-1-2. Click Finish with the default settings selected (using the Standalone operating system).

This will open the Software Platform Settings form showing the OS and libraries selections.

5-1-3. Click OK to accept the default settings as we want to create a standalone_bsp_0 software platform project without requiring any additional libraries support.

5-1-4. The library generator will run in the background and will create the xparameters.h file in the C:\xup\adv_embedded\labs\lab1\lab1.sdk\SDK\SDK_Export\standalone_bsp_0\ps7_cortexa9_0\include\ directory.



5-2. Create an empty application project, named lab1, and import the provided lab1.c file.

5-2-1. Select File > New > Application Project.

5-2-2. In the Project Name field, enter lab1 as the project name.

5-2-3. Select the Use existing option in the Board Support Package field and then click Next.

Figure 15. Create a Blank Application Project

5-2-4. Select the Empty Application template and click Finish.

The lab1 project will be created in the Project Explorer window of SDK.

5-2-5. Select lab1 in the project view, right-click, and select Import.

5-2-6. Expand the General category and double-click on File System.

5-2-7. Browse to the c:\xup\adv_embedded\sources\lab1 folder.

5-2-8. Select the lab1.c source file and click Finish.

A snippet of the source code is shown in the following figure. Note the greyed out code will be used in Lab5.



Figure 16. Snippet of Source Code



Test in Hardware Step 8

6-1. Make sure that the JP7 is set to select USB power. Connect the board with a micro-usb cable and power it ON. Establish the serial communication using SDK’s Terminal tab. Verify the design functionality.

6-1-1. Make sure that the JP7 is set to select USB power.

6-1-2. Make sure that a micro-USB cable is connected to the JTAG PROG connector (next to the power supply connector). Turn ON the power.

6-1-3. Select the tab. If it is not visible then select Window > Show view > Terminal.

6-1-4. Click on and select appropriate COM port (depending on your computer), and configure the terminal with the parameters as shown below.

Figure 17. SDK Terminal Settings

6-1-5. Select Xilinx Tools > Program FPGA.

6-1-6. Click the Program button.

6-1-7. Select the lab1 project in the Project Explorer, right-click and select Run As > Launch on Hardware(GDB) to download the application, execute ps7_init, and execute lab1.elf.

6-1-8. You should see the following output on the Terminal console.

Figure 18. SDK Terminal Output



6-1-9. Press BTN0 and see LED4 light up. Release the button and see the LED4 go OFF.

6-1-10. Play with the slide switches and see the corresponding LED turning ON and OFF.

6-1-11. Set the slide switches to the 0xF position to exit the program.

Click the Terminate button ( ) on the Console ribbon bar to terminate the execution if you want to terminate the application at anytime before setting the slide switches to the 0xF position..

6-1-12. Close SDK and Vivado programs by selecting File > Exit in each program.

6-1-13. Turn OFF the power on the board.

Conclusion In this lab, you create an ARM Cortex-A9 processor based embedded system in the Zynq device located on ZYBO. You learned how to route the GPIO connected to the PS section to the FPGA (PL) pin using the EMIO. You instantiated the Xilinx standard GPIO IP two times to provide input and output functionality. You also saw that whenever the dedicated pins are not used, you had to communicate the locations through the user constraints file (xdc).

You created the project in Vivado, created the hardware system using IPI, implemented the design in Vivado, exported the generate bitstream to the SDK, created a software application in the SDK, and verified the functionality in hardware after programming the PL section and running the application from the DDR memory.

Lab Workbook Debugging Using Hardware Analyzer


Debugging Using Hardware Analyzer Introduction Software and hardware interacts with each other in an embedded system. The Xilinx SDK includes both GNU and the Xilinx Microprocessor Debugger (XMD) as software debugging tools. The hardware analyzer tool allows for hardware debugging by providing access to the internal signals without necessarily bringing them out via the package pins using several types of cores. These powerful cores may reside in the programmable logic (PL) portion of the device and can be configured with several modes that can monitor signals within the design. Vivado provides capabilities of marking any net at several stages of the design flow. In this lab you will be introduced to various debugging cores.

Objectives After completing this lab, you will be able to: • Add the VIO core in the design • Use VIO to insert stimulus and monitor the response • Mark nets to debug so the AXI transactions can be monitored • Add the ILA core in Vivado • Perform hardware debugging using the hardware analyzer • Perform software debugging using the SDK

Procedure This lab is separated into steps that consist of general overview statements providing information on the subsequent detailed instructions. Follow the (step-by-step) detailed instructions to progress through the lab.

Design Description In this lab, you will add a custom core that performs a simple 8-bit addition function. The core used is a prior developed using the IP Packager capability of Vivado and provided as part of the lab source files. The core has additional ports so that stimuli can be brought in and the response can be monitored. This way the core can be tested independently without using the PS or software application. The following block diagram represents the completed design (Figure 1).


Debugging Using Hardware Analyzer Lab Workbook



Open the Project Step 1

1-1. Open the Vivado program. Open the lab1 project you created in the previous lab or use the lab1 project from the labsolution directory, and save the project as lab2. Set Project Settings to point to the IP repository provided in the sources directory.

1-1-1. Start the Vivado if necessary and open either the lab1 project (lab1.xpr) you created in the previous lab or the lab1 project in the labsolution directory using the Open Project link in the Getting Started page.

1-1-2. Select File > Save Project As … to open the Save Project As dialog box. Enter lab2 as the project name. Make sure that the Create Project Subdirectory option is checked, the project directory path is c:\xup\adv_embedded\labs\ and click OK.

This will create the lab2 directory and save the project and associated directory with lab2 name.

1-1-3. Click Project Settings in the Flow Navigator pane.

1-1-4. Select IP in the left pane of the Project Settings form.

1-1-5. Click on the Add Repository… button, browse to c:\xup\adv_embedded\sources\lab2\math_ip and click Select.

1-1-6. The math_ip_v1_0 IP will appear the IP in Selected Repository window.

Step 1: Open the Vivado Project

Step 2: Add the

Custom IP

Step 3: Add the

Hardware Cores

Step 4: Create HDL Wrapper and Mark Debug

Step 5: Generate Bitstream

Step 6: Generate an Application in

SDK

Step 7: Test and Debug in Hardware



Figure 2. Specify IP Repository

1-1-7. Click OK.

Add the Custom IP Step 2

2-1. Open the Block Design and add the custom IP to the system.

2-1-1. Click Open Block Design in the Flow Navigator pane, and select system.bd to open the block diagram.

2-1-2. Click the Add IP icon and search for math in the catalog.

2-1-3. Double-click the math_ip_v1_00_0 to add an instance of the core to the design

2-1-4. Click on Run Connection Automation, and select /math_ip_0/S_AXI.

The custom IP consists of a hierarchical design with the lower-level module performing the addition. The higher-level module includes the two slave registers.



Figure 3. Custom Core’s Main Functional Block

2-1-5. Click OK to add the IP.

Add the ILA and VIO Cores Step 3 We want to connect the ILA core to the LED interface. Vivado prohibits connecting ILA cores to interfaces. In order to monitor the LED output signals, we need to convert the LED interface to simple output port.

3-1. Make the gpio_io_o port of the led_8bit instance external and rename it as led_4bit.

3-1-1. Delete the led_4bit connection, by right-clicking on the connection, and selecting Delete.

3-1-2. Delete led_4bit port connector.

3-1-3. Expand the GPIO interface of the led_4bit instance so you can see gpio_io_o[3:0] port. Move the mouse close to the right end of the gpio_io_o[3:0] port, right-click, and select Make External.

The port connector named gpio_io_o[3:0] will be created and connected to the port.

3-1-4. Select the port connector gpio_io_o[3:0] and change its name to led_4bit by typing it in the properties form.

3-2. Add the ILA core and connect it to the LED output port.

3-2-1. Click the Add IP icon and search for ila in the catalog.

3-2-2. Double-click on the ILA (Integrated Logic Analyzer) to add an instance of it. The ila_0 instance will be added.

3-2-3. Double-click on the ila_0 instance and select the Probe Ports tab.

3-2-4. Set the Probe Width of PROBE0 to 4 and click OK.



3-2-5. Using the drawing tool, connect the PROBE0 port of the ila_0 instance to the gpio_io_o port of the led_4bit instance.

3-2-6. Connect the CLK port of the ila_0 instance to the s_axi_aclk port of one of the other instances.

3-3. Add the VIO core and connect it to the math_ip ports.

3-3-1. Click the Add IP icon and search for vio in the catalog

3-3-2. Double-click on the VIO (Virtual Input/Output) to add an instance of it. The vio_0 instance will be added.

3-3-3. Double-click on the vio_0 instance to open the configuration form.

3-3-4. Set the Output Probe Count to 3 and the Input Probe Count to 1 in the General Options tab.

3-3-5. Select the PROBE_IN Ports tab and set the PROBE_IN0 width to 9.

3-3-6. Select the PROBE_OUT Ports tab and set PROBE_OUT0 width to 1, PROBE_OUT1 width to 8, and PROBE_OUT2 width to 8.

3-3-7. Click OK.

3-3-8. Connect the VIO instance’s ports to the math instance ports as follows:

PROBE_IN -> result PROBE_OUT0 -> sel PROBE_OUT1 -> ain_vio PROBE_OUT2 -> bin_vio

3-3-9. Connect the CLK port of the vio_0 to s_axi_aclk port of one of the other instances.

3-3-10. The block diagram should look similar to shown below.



Figure 4. VIO instance added and connections made

3-4. Mark Debug the S_AXI connection between the AXI Interconnect and math_0 instance. Validate the design.

3-4-1. Select the S_AXI connection between the AXI Interconnect and the math_ip_0 instance.

3-4-2. Right-click and select Mark Debug to monitor the AXI4Lite transactions.

3-4-3. Select Tools > Validate Design to run the design rules checker.

Verify that there are no unmapped addresses shown in the Address Editor tab.

3-4-4. Click OK.

Create HDL Wrapper and Assign Nets for Debugging Step 4

4-1. Create the top-level HDL wrapper of the embedded system. Add the provided lab2.xdc from the sources\lab2 directory. Run the synthesis.

4-1-1. Select the Sources >Hierarchy tab. Expand the Design Sources, right-click the system.bd and select Create HDL Wrapper.

4-1-2. Click Copy and Overwrite when the wrapper file, system_wrapper.vhd, is generated and added to the hierarchy. The wrapper file will be displayed in the Auxiliary pane.

4-1-3. Right click in the Sources panel, and select Add Sources.

4-1-4. Select Add or Create Constraints and click Next.



4-1-5. Click Add Files, and browse to c:\xup\adv_embedded\sources\lab2\ and select lab2.xdc.

4-1-6. Click OK and then click Finish.

4-1-7. Click Run Synthesis.

4-1-8. Click OK and Yes to save the design and run the synthesis process.

4-1-9. When the synthesis is completed, select the Open Synthesized Design option and click OK.

Ignore the warnings. They are appearing because in lab1.xdc file from the previous lab we had defined led_4bit_tri_0[3:0] related constraints whereas in lab2.xdc file we have defined the port as led_4bit[3:0].

4-2. Assign nets for debugging.

4-2-1. The synthesized design will be opened in the Auxiliary pane and the Debug tab will be opened in the Console pane.

If the Debug tab is not open then select Window > Debug.

Notice that the nets which can be debugged are grouped into Assigned and Unassigned groups. The assigned net groups include nets associated with the VIO and ILA cores, whereas the unassigned nets group include S_AXI related nets.

Figure 5. The Debug tab

4-2-2. Right-click on the Unassigned Debug Nets and select the Set up Debug… option.

4-2-3. Click Next.



The nets are listed. There are 122 nets to debug. However, some of them such as led, math are already connected to the ILA and VIO. So we need to remove them from the list.

Figure 6. Nets to debug

4-2-4. Right click on the led_4bit_gpio_io_o, math_ip_0_result, vio_0_probe_out1, vio_0_probe_out2, vio_0_probe_out0 (all these assigned to either ILA or VIO), BRESP and RRESP (which are driven by GND) and select Remove Nets.

4-2-5. Click Next twice, and then Finish.


5-1. Generate the bitstream.

5-1-1. Click on the Generate Bitstream to run the implementation and bit generation processes.

5-1-2. Click Save to save the project, and Yes to run the processes.

5-1-3. When the bitstream generation process has completed successfully, a box with three options will appear. Select the Open Implemented Design option and click OK.

5-1-4. Click Yes to close the synthesized design, if prompted.

5-1-5. Click Yes to open the out-of-dated design. There is a bug in this version tool which shows this message.



Generate an Application in SDK Step 6

6-1. Start the SDK by exporting the implemented design. Refresh the standalone_bsp_0 project as the hardware has changed.


The Export Hardware for SDK window will appear.

6-1-2. Click on the Launch SDK check box to launch the SDK session.

6-1-3. Click OK to export and Yes to overwrite the previous project created by lab1.

6-1-4. Right-click on the standalone_bsp_0 project in the Project Explorer view and select Refresh to rebuild the project since the hardware has changed.

6-2. Create an empty application project named lab2, and import the provided lab2.c file.



6-2-3. Select the Use existing option in the Board Support Package field and then click Next.


The lab2 project will be created in the Project Explorer window of the SDK.




6-2-8. Select lab2.c and click Finish.

A snippet of the part of the source code is shown in the following figure. It shows that we write operands to the custom core, read the result, and print it. We will use the write transaction as a trigger condition in the Vivado Hardware Analyzer.



Figure 7. Source Code snippet


7-1. Make sure that the JP7 is set to select USB power. Connect the board with a micro-usb cable and power it ON. Establish the serial communication using SDK’s Terminal tab. Download the bitstream into the target device. Start the debug session on lab2 project.




7-1-4. Click on and select the appropriate COM port (depending on your computer), and configure it as you did it in Lab 1.


7-1-6. Click the Program button.

7-1-7. Select the lab2 project in Project Explorer, right-click and select Debug As > Launch on Hardware (System Debugger) to download the application, execute ps7_init, and display a dialog box asking to switch the perspective to the Debug perspective.

7-1-8. Click Yes and the perspective will change. The program execution starts and suspends at the entry point.



7-2. Start the hardware session from Vivado.

7-2-1. Switch to Vivado.

7-2-2. Click on Open Hardware Manager from the Program and Debug group of the Flow Navigator pane to invoke the analyzer.

7-2-3. Click on the Open a New Hardware Target link to establish the connection with the board.

7-2-4. Click Next twice to use the default settings.

The JTAG chain will be scanned and the device will be detected.

7-2-5. Click Next twice and then Finish.

The hardware session will open showing the Debug Probes tab.

Figure 8. Debug probes

The hardware session status window also opens showing that the FPGA is programmed (we did it in SDK), there are three cores, of which the two ila cores with the idle state.

Figure 9. Hardware session status



7-2-6. Select XC7Z010_1, and click on the Run Trigger Immediate button to see the signals in the waveform window.

Figure 10. Opening the waveform window

Two waveform windows will be created, one for each ila; one ila (hw_ila_1) is of the instantiated ILA core and another (hw_ila_2) for the MARK DEBUG method.

7-3. Setup trigger conditions to trigger on a write transaction (WSTRB) when the valid address (AWADDR) is written with data (WVALID equal to 1).

7-3-1. In the Debug Probes window, select the AWADDR bus and drag it into the ILA-hw_ila_2 window and release to add it to set a trigger condition on it (you can also add the signal by selecting it, right-clicking and selecting Add Probes to Basic Trigger Setup) .

7-3-2. Change the value from xx to 04 (the slave_reg2 address of the math_1 instance).

7-3-3. Similarly, add the WSTRB and WVALID signals, and change the condition from xxxx to xxx1 and to 1.

7-3-4. Set the trigger position of the hw_ila_2 to 512.

Figure 11. Setting up the trigger position

7-3-5. Similarly, set the trigger position of the hw_ila_1 to 512.

7-3-6. Select hw_ila_2 in the Hardware pane.

7-3-7. Click on the Run Trigger ( ) button and observe that the hw_ila_2 core is armed and showing the status as Waiting For Trigger.



Figure 12. Hardware analyzer running and in capture mode

7-3-8. Switch to SDK.

7-3-9. Double click on the left border on the line where xil_printf statement is (before the while (1) statement) is defined in the lab2.c window to set a breakpoint.

Figure 13. Setting a breakpoint

7-3-10. Click on the Resume ( ) button to execute the program and stop at the breakpoint.

7-3-11. In the Vivado program, notice that the hw_ila_2 status changed from capturing to Idle, and the waveform window shows the triggered output.

7-3-12. Move the cursor to closer to the trigger point and then click on the button to zoom at the cursor. Click on the Zoom In button couple of times to see the activity near the trigger point.

Figure 14. Zoomed waveform view

Observe the following:

Around 490th sample the RDATA value is 0x00, WDATA being written is 0x012 at offset 0 (AWADDR=0x0), WVALID is ‘1’, WREADY ‘1’ indicating the data is being written into the IP.



At 512th sample, WVALID is ‘1’ WSTRB is 0xf, offset is 0x4 (AWADDR), and the data being written is 0x034.

At 536th sample, RREADY and RVALID are ‘1’ indicating data (result=0x046) is being read from the IP at the offset 0x0 (ARADDR).

7-3-13. You also should see the following output in the SDK Terminal console.

Figure 15. SDK Terminal Output

7-4. In Vivado, select the VIO Core in Console, add the signals to the VIO-hw_vio_1 window, and set the vio_0_probe_out0 so math_ip’s input can be controlled manually through the VIO core. Try entering various values for the two operands and observe the output on the math_ip_0_result port in the Console pane.

7-4-1. Select the all the signals of the VIO Cores in the Debug Probes, drag them into the VIO-hw_vio_1 window.

7-4-2. Select vio_0_probe_out0 and change its value to 1 so the math_ip core input can be controlled via the VIO core.

Figure 16. VIO probes

7-4-3. Click on the Value field of vio_0_probe_out1 and change the value to 55 (in Hex). Similarly, click on the Value field of vio_0_probe_out2 and change the value to 44 (in Hex). Notice that for a brief moment a blue-colored up-arrow will appear in the Activity column and the result value changes to 099 (in Hex).

Figure 17. Input stimuli through the VIO core’s probes

7-4-4. Try a few other inputs and observe the outputs.

7-4-5. Once done, set the vio_0_probe_out0 to 0 to isolate the vio interactions with the math_ip core.

This is not required in this exercise but normally you would do.



7-5. Setup the ILA core (hw_ila_1) trigger condition to 0101 (x5). Make sure that the switches on the board are not set at x5. Set the trigger equation to be ==, and arm the trigger. Click on the Resume button in the SDK to continue executing th eprogram. Change the switches and observe that the hardware core triggers when the preset condition is met.

7-5-1. Select the hw_ila_1 in the ILA Cores tab and add the led_4bit_gpio_io_o[3:0] signals to the ILA-hw_ila_1 window.

7-5-2. Set the trigger condition of the hw_ila_1 to trigger at LED output value equal to 5.

Figure 18.Setting up Trigger for hw_ila_1

7-5-3. Verify that the trigger position for the hw_ila_1 is set to 512. If not, then set it.

Make sure that the switches are not set to 0101

7-5-4. Right-click on the hw_ila_1 in the hardware window, and arm the trigger by selecting Run Trigger.

The hardware analyzer should be waiting for the trigger condition to occur indicated by the Capturing status.

7-5-5. In the SDK window, click on the Resume button.

7-5-6. Change the slide switches and see the corresponding LED turning ON and OFF.

7-5-7. When the condition (0x5) is met, the waveform will be displayed.

Figure 20. ILA waveform window after Trigger

7-5-8. Click on the Disconnect button ( ) in the SDK to terminate the execution.

7-5-9. Close the SDK by selecting File > Exit.

7-5-10. In Vivado, close the hardware session by selecting File > Close Hardware Manager. Click OK.

7-5-11. Click No to not to save the waveform configuration.

7-5-12. Close Vivado program by selecting File > Exit. Click OK.




Conclusion In this lab, you added a custom core with extra ports so you can debug the design using the VIO core. You instantiated the ILA and the VIO cores into the design. You used Mark Debug feature of Vivado to debug the AXI transactions on the custom peripheral. You then opened the hardware session from Vivado, setup various cores, and verified the design and core functionality using SDK and the hardware analyzer.

.

Lab Workbook Extending Memory Space with Block RAM


Extending Memory Space with Block RAM Introduction On the ZYBO there are multiple memory choices available, some are volatile (e.g. DDR3) and some are non-volatile (e.g. QSPI Flash). There are hard controllers on the ARM Cortex-A9 core providing processor access to these memories. However, certain IP may need to access additional memory which can be difficult. The PL portion of the Zynq device has plenty of Block RAM (BRAM) which can be used by an IP without contending for external resources and creating performance bottleneck. This lab guides you through the process of extending the memory space in Zynq-based platform using available PL based BRAM resource.

Objectives After completing this lab, you will be able to: • Add BRAM and connect it to the processing system’s AXI master port • Execute the software application having data section in the BRAM


Design Description In this lab, you will add an AXI BRAM memory controller and associated 64 Kb BRAM memory to the system you created in the first lab. The following block diagram represents the completed design (Figure 1).


Extending Memory Space with Block RAM Lab Workbook




1-1. Open the Vivado program. Open the lab1 project you created earlier or use the lab1 project from the labsolution directory, and save the project as lab3.

1-1-1. Start the Vivado if necessary and open either the lab1 project (lab1.xpr) you created earlier or the lab1 project in the labsolution directory using the Open Project link in the Getting Started page.


This will create the lab3 directory and save the project and associated directory with lab3 name.

Configure the Processor to Enable M_AXI_GP1 Step 2

2-1. Open the Block Design and enable the M_AXI_GP1 interface.


2-1-2. Double-click on the processing_system7_0 instance to open its configuration form.

2-1-3. Select PS-PL Configuration in the Page Navigator window in the left pane, expand GP Master AXI Interface on the right, and click on the check-box of the M_AXI GP1 Interface to enable it.

2-1-4. Select Clock Configuration in the Page Navigator window in the left pane, expand PL Fabric Clocks on the right, and click on the check-box of the FCLK_CLK1 to enable it.

2-1-5. Enter the Requested Frequency for the FCLK_CLK1 as 140.00000 MHz, if it is different.

Step 1: Open the Project

Step 2: Configure the Processor to

Enable M_AXI_GP1

Interface

Step 3: Extend with

BRAM

Step 4: Create

Wrapper and Generate the

Bitstream

Step 5: Generate

Applications in SDK

Step 6: Test in

Hardware



2-1-6. Click OK to accept the settings and close the configuration form.

Figure 2. M_AXI_GP1 interface enabled

Extend with BRAM Step 3

3-1. Add an AXI BRAM Controller instance with BRAM.

3-1-1. Click the Add IP icon and search for BRAM in the catalog.

3-1-2. Double-click the AXI BRAM Controller to add an instance to the design.

3-1-3. Click on Run Connection Automation, and select /axi_bram_ctrl_0 /S_AXI.

3-1-4. Click OK to connect to the M_AXI_GP1 interface.

Figure 3. Connecting AXI BRAM Controller to M_AXI_GP1 to run at faster clock speed

Notice that an instance of AXI Interconnect is added, and the M_AXI_GP0_ ACLK is connected to M_AXI_GP1_ACLK.



Figure 4. AXI BRAM controller connections

Since we want the BRAM controller to run at different speed than the rest of the peripherals, we need to reconnect the clocks.

3-1-5. Select the S_AXI_ACLK pin of the axi_bram_ctrl_0 instance, right-click, and select Disconnect Pin.

Figure 5. Disconnecting net to the S_AXI_ACLK pin

3-1-6. Similarly, disconnect the net of the M_AXI_GP1_ACLK pin of the processing_system7_0 instance, and ACLK, S00_ACLK, M00_ACLK pins of the axi_mem_intercon instance.

3-1-7. Using the wiring tool, make the following connections:

o FCLK_CLK1 to ACLK, S00_ACLK, M00_ACLK of the axi_mem_intercon (AXI Interconnect) instance

o FCLK_CLK1 to S_AXI_ACLK of the axi_bram_ctrl_1 instance



o FCLK_CLK1 to M_AXI_GP1_ACLK of the processing_system7_0 instance

3-1-8. Double-click on the axi_bram_ctrl_0 instance to open the configuration form.

3-1-9. Set the width to 64.

Figure 6. Setting the BRAM controller size to support 64KB and higher performance width

3-1-10. Click OK.

3-1-11. Click the Add IP icon and search for Block in the catalog.

3-1-12. Double-click the Block Memory Generator to add an instance to the design

3-1-13. Double-click on the blk_mem_gen_0 instance to open its configuration form.

3-1-14. Change the memory type from Single Port RAM to True Dual Port RAM and click OK.

Figure 7. Configuring BRAM to True Dual Port RAM

3-1-15. Using the drawing tool, connect the two ports of the BRAM Controller to the two ports of BRAM.



3-2. Using the Address Editor tab, set the BRAM controller size to 64KB. Validate the design.

3-2-1. Select the Address Editor tab and notice that the BRAM controller memory space is 4K.

3-2-2. Click in the Range column of the axi_bram_ctrl_1 instance and set the size as 64K.

Figure 8. AXI BRAM space assignment

Notice that the address range changed to 0x80000000-0x8000FFFF. This is in the M_AXI_GP1 addressing space.

Figure 9. Assigned address range

3-2-3. The design should look similar to the figure below.


3-2-4. Select Tools > Validate Design and fix errors if necessary.

Fixed any errors.



Create the wrapper and Generate the Bitstream Step 4

4-1. Create the top-level HDL wrapper.

4-1-1. Select the Design pane, and click on the Sources tab. Expand the Design Sources, right-click the system.bd and select Create HDL Wrapper.

4-1-2. Click OK to generate and update the wrapper file.

4-1-3. Click on the Generate Bitstream to run the synthesis, implementation, and bit generation processes.


4-1-5. When the bitstream generation process has completed successfully, select the Open Implemented Design option and click OK.

Generate Applications in the SDK Step 5



The Export Hardware for SDK window will appear. Click on the Launch SDK box to launch the SDK session.


5-1-3. Click Yes to update the bitstream and/or bmm files.

5-1-4. Right-click on the standalone_bsp_0 project in the Project Explorer view and select Refresh to rebuild the project since the hardware has changed.

5-2. Create a hello_world application project using the standard template.


5-2-2. In the Project Name field, enter hello_world as the project name.

5-2-3. Use the default settings to create a new BSP and click Next.

5-2-4. Select the Hello World template and click Finish.

The hello_world and hello_world_bsp projects will be created in the Project Explorer window of SDK.






5-3-3. Select the Use existing option in the Board Support Package field, select standalone_bsp_0 using the drop-down button, and then click Next.





5-3-7. Browse to c:\xup\adv_embedded\sources\lab3 folder.


A snippet of the source code is shown in the following figure. It shows that we write a pattern to the LED port, execute a software delay loop, and repeat for 256 times and repeat the process again.



Figure 11. Snippet of Part of the Source Code


6-1. Make sure that the JP7 is set to select USB power. Connect the board with a micro-usb cable and power it ON. Establish the serial communication using SDK’s Terminal tab. Program the FPGA. Run the hello_world.elf application.




6-1-4. Click on to initiated the serial connection and select the appropriate COM port (depending on your computer). Configure it with 115200 baud rate.

6-1-5. In SDK, select Xilinx Tools > Program FPGA.



6-1-6. Click the Program button to program the FPGA.

6-1-7. Select hello_world in Project Explorer, right-click and select Run As > Launch on Hardware(GDB) to download the application, execute ps7_init, and execute hello_world.elf

You should see “Hello World” displayed in the Terminal window.

6-2. Modify the linker script to use the BRAM for the data section and run it.

6-2-1. Select the hello_world application in the Project Explorer view.

6-2-2. Right-click and select Generate Linker Script.

6-2-3. Change the data segment memory to axi_bram_ctrl_0_S_AXI_BASEADDR.

Figure 12. Assigning Data Segment to AXI BRAM

6-2-4. Click the Generate button.

6-2-5. Click the Yes button to overwrite.

6-2-6. Select the hello_world application, right-click, and run it.

You should see “Hello World” displayed in the Terminal window again.

6-3. Run the lab3 application from the DDR3 memory.

6-3-1. Select the lab3 project in Project Explorer, right-click and select Run As > Launch on Hardware (GDB).

The application (lab3.elf) will be downloaded into the target device, execute ps7_init, and execute.

6-3-2. You should see the on-board LEDs changing patterns at roughly a one second delay rate.

6-3-3. Click the Terminate button ( )on the Console ribbon bar to terminate the execution.

6-4. Modify the linker script to use the BRAM for the data section and execute.

6-4-1. Select the lab3 application in the Project Explorer view.




6-4-3. Change the data segment memory to axi_bram_ctrl_0_S_AXI_BASEADDR.



6-4-6. Select the lab3 project in Project Explorer, right-click and select Run As > Launch on Hardware (GDB).

The application (lab3.elf) will be downloaded into the target device, execute ps7_init, and will be executed.

6-4-7. Click the Terminate button ( )on the Console ribbon bar to terminate the execution.

6-4-8. Close the SDK program by selecting File > Exit.

6-4-9. Close the Vivado program by selecting File > Exit.


Conclusion This lab led you through adding BRAM memory in the PL section thereby extending the total memory space available to the PS. You have verified the functionality by creating an application, targeting the data section to the added BRAM, and executing the application.

.

Lab Workbook Direct Memory Access using CDMA


Direct Memory Access using CDMA Introduction In Zynq, multiple interconnections are available between the PS and PL sections with some providing slower data transfer rate and others faster data transfer rate (performance). The lower performance interconnections are slave and master types. You have used the PS master to PL slave interconnection in the previous labs. The PS slave and PL master general purpose interconnections are available for less performance demanding master IPs residing in the PL section. There are also four higher performance PS slave to PL master ports available for IPs related to high-performance demanding applications such as video and image processing. This lab guides you through the process of enabling a high-performance slave port of the PS, adding an AXI central DMA (CDMA) controller, and performing Direct Memory Access (DMA) operations between various memories.

Objectives After completing this lab, you will be able to:

• Enable a high-performance (HP) port of the processing system • Add and connect the CDMA controller in the programmable logic • Perform DMA operation between various memories


Design Description In this lab, you will enable the HP port of the PS and add an instance of the Central DMA (CDMA) controller in the PL. You will also add another instance of an AXI-BRAM controller to access the second port of the BRAM via the processor. You will connect the interrupt request line from the CDMA to the input of the GIC of the PS. The following diagram represents the completed design (Figure 1).


Direct Memory Access using CDMA Lab Workbook




1-1. Open the Vivado program. Open the lab3 project you created earlier or use the lab3 project from the labsolution directory, and save the project as lab4.

1-1-1. Start the Vivado if necessary and open either the lab3 project (lab3.xpr) you created earlier or the lab1 project in the labsolution directory using the Open Project link in the Getting Started page.


1-1-3. This will create the lab4 directory and save the project and associated directory with lab4 name

Configure the Processor to Enable S_AXI_HP0 Step 2

2-1. Open the Block Design and enable the S_AXI_HP0 interface



2-1-3. Select PS-PL Configuration in the Page Navigator window in the left pane, expand HP Slave AXI Interface on the right, and click on the check-box of the S_AXI HP0 Interface to enable it and click OK to close the Configuration window.

Step 1: Open the Project

Step 2: Configure the Processor to

enable S_AXI_HP0

Step 3: Add CDMA and BRAM

Step 4: Create the

Wrapper and Generate the

Bitstream

Step 5: Generate an Application in

SDK

Step 6: Test in

Hardware



Add CDMA and BRAM Step 3

3-1. Instantiate the AXI central DMA controller.

3-1-1. Click the Add IP icon and search for Central in the catalog.

3-1-2. Double-click the AXI Central Direct Memory Access to add an instance to the design.

3-1-3. Click on Run Connection Automation, and select /processing_system7_0 /S_AXI_HP0.

3-1-4. Click OK to connect to the /axi_cdma_0/m_axi interface.

Figure 2. Connecting AXI Central DMA controller to S_AXI_HP0

Notice that an instance of AXI Interconnect (axi_mem_intercon_1) is added, S_AXI_HP0 of the processing_system7_0 is connected to M00_AXI of the axi_mem_intercon_1, S00_AXI of the axi_mem_intercon_1 is connected to the m_axi of the axi_cdma_0 instance. Also, m_axi_aclk of the axi_cdma_0 is connected to the net originating from FCLK_CLK0 of the processing_system7_0.

Figure 3. Connections between the processor, axi_interconnect, and cdma

3-1-5. Click on Run Connection Automation, and select /axi_cdma_0/S_AXI_LITE.

3-1-6. Select M_AXI_GP0 using the drop-down button and click OK.

M_AXI_GP0 uses 32-bit interface whereas M_AXI_GP1 uses 64-bit interface. Since s_axi_lite is 32-bit interface, hence M_AXI_GP0 is selected.



3-2. Instantiate the BRAM Controller and a BRAM.

3-2-1. Click the Add IP icon and search for BRAM in the catalog.

3-2-2. Double-click the AXI BRAM Controller to add an instance to the design.

3-2-3. Click on Run Connection Automation, and select /axi_bram_ctrl_1 /S_AXI.

3-2-4. Select axi_cdma_0/M_AXI interface from the pull-down button and click OK.

Notice that another axi interface (M01_AXI) is added to the axi_mem_intercon_1 instance and is connected to the S_AXI interface of the axi_bram_ctrl_1 instance.

Figure 4. Connection between axi_bram_ctrl_1 and the axi_mem_intercon_1

3-2-5. Double-click the axi_bram_ctrl_1 instance and change the Number of BRAM Interface to 1. Change the data width to 64. Click OK.

3-2-6. Double-click the axi_bram_ctrl_0 instance and change the Number of BRAM Interface to 1. Click OK.

3-2-7. Using wire tool, connect the BRAM_PORTA of the axi_bram_ctrl_1 instance to the BRAM_PORTB of the blk_mem_gen_0 instance.

3-3. Turn OFF the SG (scatter gather) feature of the CDMA. Connect the CDMA interrupt out port to the port of the processor.

3-3-1. Double-click on the axi_cdma_0 instance and uncheck the Enable Scatter Gather option.

3-3-2. Click OK.


3-3-4. Select Interrupts in the Page Navigator window in the left pane, check Fabric Interrupts box.



3-3-5. Expand Fabric Interrupts > PL-PS Interrupts Ports, and click on the check-box of the IRQ_F2P.

Figure 5. Enabling interrupt

3-3-6. Click OK.

3-3-7. Using wiring tool, connect the cdma_introut to the IRQ_F2P port.

3-4. Using the Address Editor tab, set the BRAM controller size to 64KB. Validate the design.

3-4-1. Select the Address Editor tab.

3-4-2. Expand the axi_cdma_0> Data section, and change the memory size of axi_bram_ctrl_1 to 64K.

Figure 6. Address space

3-4-3. The design should look like as shown below.


3-4-4. Select Tools > Validate Design and fix errors if necessary.



Create the wrapper and Generate the Bitstream Step 4

4-1. Create the top-level HDL wrapper.

4-1-1. Select the Sources> Hierarchy tab. Expand the Design Sources, right-click the system.bd and select Create HDL Wrapper.

4-1-2. Click OK to generate and manage the wrapper.

4-1-3. Click on the Generate Bitstream to run the synthesis, implementation, and bit generation processes.


4-1-5. When the bitstream generation process has completed successfully, select the Open Implemented Design option and click OK.

Generate an Application in the SDK Step 5



The GUI will be displayed. Click on the Launch SDK box to launch the SDK session.


5-1-3. Right-click on the standalone_bsp_0 project in the Project Explorer view and select Refresh to rebuild the project since the hardware has changed (the cdma controller was added)..




5-2-3. Select the Use existing option in the Board Support Package (BSP) field, select standalone_bsp_0 using the drop-down button, and then click Next.










6-1. Make sure that the JP7 is set to select USB power. Connect the board with a micro-usb cable and power it ON. Establish the serial communication using SDK’s Terminal tab. Download the bitstream and program the FPGA. Run the lab4 application and verify the functionality.




6-1-4. Click on to initiated the serial connection and select the appropriate COM port (depending on your computer). Configure it with 115200 baud rate.

6-1-5. In SDK, select Xilinx Tools > Program FPGA.

6-1-6. Click the Program button to program the FPGA.

6-1-7. Select the lab4 project in Project Explorer. Right-click and select Run As > Launch on Hardware (GDB).

Follow the menu in the terminal emulator window and test transfers between various memories.

6-1-8. Select option 4 in the menu to complete the execution or click the Terminate button ( ) on the Console ribbon bar to terminate the execution if needed.

6-1-9. Close the SDK and Vivado programs by selecting File > Exit in each program.


Conclusion This lab led you through adding a CDMA controller to the PS so that you can perform DMA transfers between various memories. You used the high-performance port so DMA could be done between the BRAM residing in the PL section and DDR3 connected to the PS. You verified the design functionality by creating an application and executing it from the DDR3 memory.

.

Lab Workbook Configuration and Booting


Configuration and Booting Introduction This lab guides you through creating a bootable system capable of booting off the SD card or the QSPI flash memory located on the ZYBO. It also demonstrates how different bitstream can be loaded in the PL section after the board is booted up and the corresponding application can be executed.

Objectives After completing this lab, you will be able to: • Create a bootable system capable of booting off the SD card • Create a bootable system capable of booting off the QSPI flash • Load the bitstream stored on the SD card or in the QSPI flash memory • Configure the PL section using the stored bitstream through the PCAP resource • Execute the corresponding application


Design Description In this lab, you will design just the PS based embedded system consists of ARM Cortex-A9 processor SoC. The SDIO and QSPI interfaces are included in the base design. The base design will then load the user selected design, consisting of both different hardware and software, and execute it. The following diagram represents the completed design (Figure 1).


Configuration and Booting Lab Workbook




1-1. Launch Vivado and create an empty project targeting the ZYBO board (having xc7z010clg400-1 device) and using the Verilog language.








1-1-8. In the Default Part form, select Parts, and using various filters shown in the figure below, select xc7z010clg400-1 part as it is on the ZYBO board. Click Next



Step 2: Create the Hardware


Step 3: Export the

Design to the SDK

Step 4: Create the

Boot Images and Test

Step 5: Prepare for the Multi-

Applications Boot

Step 6: Create QSPI Application and Image

Step 7: Program the

QSPI and Test




2-1. Create a block design in the Vivado project using IP Integrator to generate the ARM Cortex-A9 processor based hardware system.


2-1-2. Name the block system and click OK.






2-1-8. Click OK.



2-2. Configure the I/O Peripherals block to only have QSPI, UART 1 and SD 0 support.










2-2-6. Expand the I/O Peripherals on the right.

2-2-7. Uncheck ENET 0, and USB 0, leaving UART 1 and SD 0 selected.

2-2-8. Expand the SD 0 box, and select Write Protect check box.

There is a bug in the tool where the write protect bit for the SD peripheral is getting pulled up and the software completely ignores the booting process. The work around this is to enable write protect during Zynq IP Customization in Vivado. Notice that the WP is routed through EMIO and hence the design will have to be implemented.

2-3. Deselect TTC device and M_AXI_GP0 interface.


2-3-2. In the PS-PL Configuration, expand the GP Master AXI Interface, and uncheck the M AXI GP0 Interface.

2-3-3. In the PS-PL Configuration, expand the General > Enable Clock Resets, and uncheck the FCLK_RESET0_N.

2-3-4. In the Clock Configuration, expand the PL Fabric Clocks, and uncheck the FCLK_CLK0.

2-3-5. Click OK.




2-3-7. Select File > Save Block Design to save the design.




3-1. Create the top-level HDL of the embedded system, and generate the bitstream..

3-1-1. In Vivado, select the Sources > Hierarchy tab, expand the Design Sources, right-click the system.bd and select Create HDL Wrapper.

3-1-2. Click OK.

3-1-3. Right-click on the system.bd, and select Generate Output Products.

3-1-4. Click Generate.

3-1-5. Click on the Generate Bitstream to go through the implementation as the WP port is routed through the EMIO due to a workaround the tool bug mentioned above.

3-1-6. Click Save and Yes to save the design and run the necessary processes.

3-2. Export the design to the SDK. Create a first stage bootloader (FSBL) and a hello world applications.

3-2-1. Start the SDK by selecting File > Export > Export Hardware for SDK.



3-2-3. Enter zynq_fsbl_0 as the project name, select the Create New option with zynq_fsbl_0_bsp, and click Next.

3-2-4. Select Zynq FSBL in the Available Templates pane and click Finish.

3-2-5. A zynq_fsbl_0 project will be created which will be used in creating the BOOT.bin file. The BOOT.bin file will be stored on the SD card from which the board will be boot up.


3-2-7. Enter hello_world in the project name field, select the Use existing standalone Board Support Package option with zynq_fsbl_0_bsp, and click Next.

3-2-8. Make sure that the Hello World application template is selected, and click Finish to generate the application.



Create the Boot Images and Test Step 4

4-1. Using the Windows Explorer, create a directory called image under the lab5 directory. Create the BOOT.bin file using the FSBL and hello_world.elf files.

4-1-1. Using the Windows Explorer, create the image directory under the lab5 directory.

4-1-2. In the SDK, select Xilinx Tools > Create Zynq Boot Image.

4-1-3. Click the Browse button of the BIF file path field, and browse to c:\xup\adv_embedded\labs\lab5\image directory and click Save.

4-1-4. Click on the Add button of the Boot image partitions window.

A Add new boot image partition window will show up.

4-1-5. Click on the Browse button of the File Path field, browse to c:\xup\adv_embedded\labs\lab5\lab5.sdk\SDK\SDK_Export\zynq_fsbl_0\Debug, select zynq_fsbl_0.elf, click Open, and then click OK.

Since we do not have any hardware in the PL section, we have not generated the system_wrapper.bit file. Had we generated the system_wrapper.bit file, we would add the system_wrapper.bit file next.

4-1-6. Click on the Browse button of the File Path field, browse to c:\xup\adv_embedded\labs\lab5\lab5.sdk\SDK\SDK_Export\hw_platform_0 and select system_wrapper.bit, click Open, and then click OK.

4-1-7. Click on the Add button of the Boot image partition field again and add the software application, hello_world.elf, from the c:\xup\adv_embedded\labs\lab5\lab5.sdk\SDK\SDK_Export\hello_world\Debug directory.

4-1-8. Make the window bigger (taller), if necessary, so that you can see the Output folder field,

4-1-9. Change the output filename to BOOT.bin and location to c:\xup\adv_embedded\labs\lab5\image (if necessary).



Figure 3. Creating BOOT.bin file

4-1-10. Click the Create Image button.

The BOOT.bin and output.bif files will be created in the lab5\image directory.

4-1-11. Insert a blank microSD card (FAT32 formatted) in a microSD Card reader, and using the Windows Explorer, copy the BOOT.bin file from the image folder in to the microSD card.

4-2. Set the board in the SD card boot mode. Test the functionality by starting a Terminal emulator program and powering ON the board.

4-2-1. Set the board in the microSD card boot mode by putting the jumper on the left most two pins of the mode pins jumper JP5 ( ) to boot the board from the SD card.

4-2-2. Connect your PC to the ZYBO’s UART port with the micro-USB cable, and start a Terminal emulator program.

4-2-3. You should see the Hello World message in the terminal emulator window. If you don’t see it, then press the PS-SRST (left Red button) button on the board.



You should see the Hello World message in the terminal emulator window.

4-2-4. Once satisfied, power OFF the board.

4-3. Create the BOOT.mcs file using the FSBL, bitstream, and hello_world.elf files.


4-3-2. Select Import from existing BIF file option, click the Browse button of the BIF file path field and browse to c:\xup\adv_embedded\labs\lab5\image directory, select output.bif, and click Open.


4-3-4. Change the output filename to BOOT.mcs.


4-3-6. The BOOT.mcs file will be created in the lab5\image directory

4-4. Make sure that the board is in the JTAG boot mode. Power ON the board, Program the QSPI using the Flash Writer utility.

4-4-1. Set the board in the JTAG mode by placing the jumper cap on the two right-most pins of the JP5 jumper ( ).

4-4-2. Power ON the board.

4-4-3. Select Xilinx Tools > Program Flash.

4-4-4. In the Program Flash Memory form, click the Browse button, and browse to the c:\xup\adv_embedded\labs\lab5\image directory, select BOOT.mcs file, and click Open.

4-4-5. In the Offset field enter 0 as the offset and click the Program button.

The QSPI flash will be programmed.



Figure 4. The Program Flash Memory Form

4-5. Power OFF the board and set the board in the QSPI boot mode. Test the functionality by starting a Terminal emulator program and powering ON the board.

4-5-1. Power OFF the board.

4-5-2. Set the board in the QSPI mode by placing the jumper cap on middle two pins of JP5 jumper ( ) to boot the board from the QSPI flash memory.

4-5-3. Connect your PC to the ZYBO’s UART port with the provided micro-USB cable, and start a Terminal emulator program setting it to the current COM port and a 115200 baud rate.


4-5-5. Press the PS-SRST (left Red button) button on the board to see the Hello World message in the terminal emulator window.


Prepare for the Multi-Applications Boot Step 5

If you don’t have time or prefer to use the pre-built lab1.bin and lab3.bin image files then you can skip this step and go directly to Step 6.

5-1. (OPTIONAL) Switch the workspace to lab1’s SDK project. Define MULTIBOOT symbol, create Zynq_fsbl application, and change the lab1 BSP reference to zynq_fsbl_0_bsp. Create the image using the zynq_fsbl_0.elf, system_wrapper.bit, and lab1.elf files and naming it as lab1.bin in the lab1 directory.



5-1-1. In the SDK program switch the workspace by selecting File > Switch Workspace > Other… and browse to the workspace pointing to c:\xup\adv_embedded\labs\lab1\lab1.sdk\SDK\SDK_Export and click OK.

5-1-2. Right-click on the lab1 entry, select the C/C++ Build Settings option.

5-1-3. Select Symbols in the left pane under the ARM gcc compiler group, click the + button on the right, enter MULTIBOOT in open form, and click OK.

The application will re-compile as the MULTIBOOT related code is now included.

Figure 5. Setting user-defined symbol

5-1-4. Select File > New > Application Project



5-1-7. Select lab1 in the Project Explorer pane, right-click, and select Change Referenced BSP.

5-1-8. In the displayed form, select zynq_fsl_0_bsp and click OK.

The lab1 will be re-compiled using the zynq_fsl_bsp_0.


5-1-10. Select Create new BIF file option, click the Browse button of the BIF file path field and browse to c:\xup\adv_embedded\labs\lab1 directory, set filename as lab1, and click Save.


5-1-12. Make sure that the three files, zynq_fsbl_0.elf, system_wrapper.bit, and lab1.elf file entries are added with the correct path. Change if necessary.

5-1-13. Change the output filename to lab1.bin making sure that the output directory is lab1.



Figure 6. Creating the bin file of the lab1 project for the multiboot application


The lab1.bin will be created in the lab1 directory.

5-2. (OPTIONAL) Switch the workspace to lab3’s SDK project. Define MULTIBOOT symbol, create Zynq_fsbl application, and change the lab3 BSP reference to zynq_fsbl_0_bsp. Create the image using the zynq_fsbl_0.elf, system_wrapper.bit, and lab3.elf files and naming it as lab3.bin in the lab3 directory.

5-2-1. In the SDK program switch the workspace by selecting File > Switch Workspace > Other… and browse to the workspace pointing to c:\xup\adv_embedded\labs\lab3\lab3.sdk\SDK\SDK_Export and click OK.

5-2-2. Right-click on the lab3 entry, select the C/C++ Build Settings option.

5-2-3. Select Symbols in the left pane under the ARM gcc compiler group, click the + button on the right, enter MULTIBOOT in open form, and click OK.

The application will re-compile as the MULTIBOOT related code is now included.

5-2-4. Select File > New > Application Project





5-2-7. Select lab3 in the Project Explorer pane, right-click, and select Change Referenced BSP.

5-2-8. In the displayed form, select zynq_fsl_0_bsp and click OK.

The lab3 will be re-compiled using the zynq_fsl_bsp_0.

5-2-9. Select the lab3 application in the Project Explorer view.


5-2-11. Change the data segment memory to ps7_ddr_0_S_AXI_BASEADDR.




5-2-15. Select Create new BIF file option, click the Browse button of the BIF file path field and browse to c:\xup\adv_embedded\labs\lab3 directory, set filename as lab3, and click Save.


5-2-17. Make sure that the three files, zynq_fsbl_0.elf, system_wrapper.bit, and lab3.elf file entries are added with the correct path. Change if necessary.

5-2-18. Change the output filename to lab3.bin making sure that the output directory is lab3.


The lab3.bin will be created in the lab3 directory.

Create the QSPI application and image Step 6

6-1. Switch workspace to lab5 project. Create the lab5_qspi application using the provided lab5_qspi.c, devcfg.c, devcgf.h, and load_elf.s files.

6-1-1. In the SDK program switch the workspace by selecting File > Switch Workspace > Other… and browse to the workspace pointing to c:\xup\adv_embedded\labs\lab5\lab5.sdk\SDK\SDK_Export and click OK




6-1-3. Enter lab5_qspi as the project name, select the Use existing option for the Board Support Package, and using the drop-down button select zynq_fsbl_0_bsp, and click Next.

6-1-4. Select Empty Application in the Available Templates pane and click Finish.

6-1-5. Select lab5_qspi in the project view, right-click, and select Import.

6-1-6. Expand General folder and double-click on File system, and browse to the c:\xup\adv_embedded\sources\lab5 directory.

6-1-7. Select lab5_qspi.c and click Finish.

The program should compile successfully and generate the lab5_qspi.elf file.

6-2. Using the Windows Explorer, create the QSPI_image directory under the lab5 directory. Create the output.mcs file using the zynq_fsbl_0.elf, system_wrapper.bit, and lab5_qspi.elf files.

6-2-1. Using the Windows Explorer, create the QSPI_image directory under the lab5 directory.


6-2-3. Select Create new BIF file option, click the Browse button of the BIF file path field and browse to c:\xup\adv_embedded\labs\lab5\QSPI_image directory, select output.bif, and click Save.

6-2-4. Click on the Add button of the Boot image partitions window.

6-2-5. Click on the Browse button of the File Path field, browse to c:\xup\adv_embedded\labs\lab5\lab5.sdk\SDK\SDK_Export\zynq_fsbl_0\Debug, select zynq_fsbl_0.elf, click Open, and then click OK.

6-2-6. Click on the Browse button of the File Path field, browse to c:\xup\adv_embedded\labs\lab5\lab5.sdk\SDK\SDK_Export\hw_platform_0, select system_wrapper.bit, click Open, and then click OK.

6-2-7. Click on the Add button of the Boot image partition field again and add the software application, lab5_qspi.elf, from the c:\xup\adv_embedded\labs\lab5\lab5.sdk\SDK\SDK_Export\lab5_qspi\Debug directory.


6-2-9. Change the output filename to lab5.mcs and the location to c:\xup\adv_embedded\labs\lab5\QSPI_image (if necessary).


The lab5.mcs file will be created in the lab5\QSPI_image directory.

6-3. Make sure that the board is in the JTAG boot mode. Power ON the board. Program the QSPI using the Flash Writer utility.



6-3-1. Make sure that the board is in the JTAG boot mode. Power ON the board.

6-3-2. Select Xilinx Tools > Program Flash.

6-3-3. In the Program Flash Memory form, click the Browse button, and browse to the c:\xup\adv_embedded\labs\lab5\QSPI_image directory, select lab5.mcs file, and click Open.

6-3-4. In the Offset field enter 0 as the offset and click the Program button.

The QSPI flash will be programmed.

6-3-5. Power cycle the board.

Program the QSPI with Multi-Applications and Test Step 7

7-1. Program the QSPI with either the generated lab1.bin and lab3.bin files in Step 5 OR using the provided files in the sources\lab5 directory with the offset of 0x400000 and 0x800000 respectively using the xmd and provided u-boot.elf program.

7-1-1. Start the terminal emulator program and configure it with the appropriate COM port and 115200 baud rate.

7-1-2. In SDK, start the XMD session by selecting Xilinx Tools > XMD Console.

7-1-3. Execute the following commands in the XMD console:

connect arm hw cd c:/xup/adv_embedded/labs/lab5/lab5.sdk/SDK/SDK_Export dow zynq_fsbl_0/Debug/zynq_fsbl_0.elf con stop cd c:/xup/adv_embedded/sources/lab5 dow u-boot.elf con

7-1-4. Quickly switch to the terminal emulator’s window and press any key on the keyboard to interrupt the uboot process.

You should see zed-boot> prompt in the terminal emulator’s window.

7-1-5. In the XMD console window type the following commands (the following command uses the files provided from the solution. If you want to use your own generated files then change the directory to SD_image where you should have created the files in the previous step):

stop dow -data lab1.bin 0x10400000 dow -data lab3.bin 0x10800000 con



7-1-6. Switch to the terminal emulator’s window and type the following commands at the zed-boot> prompt:

sf probe 0 0 0 sf erase 0x400000 0x800000 sf write 0x10400000 0x400000 0x800000

Note that the first sf probe command should come back with the QSPI detected message. If it does not, then type that command one more time.

Also, note that sf erase command will take about a minute. In that command, we are erasing 0x800000 bytes starting at the offset of 0x400000 in the QSPI.

The sf write command will be very quick. It writes 0x800000 bytes content loaded in DDR at 0x10400000 into the QSPI starting at the offset address of 0x400000.

7-1-7. In xmd console, type the following two commands to stop the processor and disconnect xmd

stop

disconnect 64

7-1-8. Power OFF the board.

7-1-9. Set the board in the QSPI mode.


7-1-11. Start the terminal emulator session and press any key to see the menu.

7-1-12. Follow the menu and test the functionality of each lab.

Press 1 to load and execute lab1 or 2 to load and execute lab3. After each lab is executed, the lab5 gets loaded displaying the menu. Note that lab1 execution terminates when all slide switches are ON (i.e. 0xF) and lab3 execution terminates after it counts from 0 to 15.


7-1-14. Close SDK and Vivado programs by selecting File > Exit in each program.


Conclusion This lab led you through creating the boot images which were capable of booting standalone applications from either the SD card or the QSPI flash memory. You then created the design capable of booting multiple applications and configurations which you developed in the previous labs.

Lab Workbook Profiling and Performance Tuning


Profiling and Performance Tuning Introduction This lab guides you through the process of profiling an application with a function modeled in software, and analyzing the profiled output. The application is then profiled using the hardware accelerated functionalities in Zynq.

Objectives After completing this lab, you will be able to: • Setup the board support package (BSP) for profiling an application • Set the necessary compiler directive on an application to enable profiling • Setup the profiling parameters • Profile an application and analyze the output


Design Description In this lab, you will design an embedded system consists of ARM Cortex-A9 processor SoC and an instance of the provided FIR filter IP. The following diagram represents the completed design (Figure 1).


Profiling and Performance Tuning Lab Workbook




1-1. Launch Vivado and create an empty project targeting the ZYBO board (having xc7z010clg400-1 device) and using the Verilog language.








1-1-8. In the Default Part form, select Parts, and using various filters shown in the figure below, select xc7z010clg400-1 part as it is on the ZYBO board. Click Next



Step 2: Create the Hardware


Step 3: Add FIR Core to the System

Step 4: Generate the

Bitstream

Step 5: Export the

Design to the SDK

Step 6: Create the Application

Step 7: Run the

Application and Profile



1-2. Set the project settings to include provided fir_top IP

1-2-1. Click Project Settings in the Flow Navigator pane.

1-2-2. Select IP in the left pane of the Project Settings form.

1-2-3. Click on the Add Repository… button, browse to c:\xup\adv_embedded\sources\lab6\fir_ip and click Select.

1-2-4. The fir_top _v1_0 IP will appear the IP in Selected Repository window.

1-2-5. Click OK.


2-1. Create a block design in the Vivado project using IP Integrator to generate the ARM Cortex-A9 processor based hardware system.


2-1-2. Name the block system and click OK.






2-1-8. Click OK.





2-2. Configure the I/O Peripherals block to only have UART 1 support. Deselect TTC device.








2-2-6. Expand the I/O Peripherals on the right.

2-2-7. Uncheck ENET 0, SD 0, and USB 0, leaving UART 1 selected.


2-2-9. Click OK.



Add FIR Core to the System Step 3

3-1. Instantiate the provided FIR core and validate the design.

3-1-1. Click the Add IP icon and search for fir in the catalog.



3-1-2. Double-click on the fir_top_v1_0 to add the IP instance to the system

3-1-3. Select the fir_top_0 instance and change its name to fir_filter in its property form.

3-1-4. Click on Run Connection Automation, and select /fir_filer/s_axi_fir_io.

3-1-5. Click OK to connect to the M_AXI_GP0 interface.

The design should look similar to shown below:




4-1. Create the top-level HDL of the embedded system, and generate the bitstream.

4-1-1. In Vivado, select the Design pane, expand the Design Sources, right-click the system.bd and select Create HDL Wrapper.

4-1-2. Click OK to generate and add the system_wrapper.v to the hierarchy.

4-1-3. Click on the Generate Bitstream in the Flow Navigator pane to synthesize and implement the design, and generate the bitstream.

4-1-4. Click Save to save the design and Yes to run the necessary processes.

4-1-5. When the bitstream generation process has completed successfully, a box with options will appear. Select the Open Implemented Design option and click OK.




5-1. Export the design to the SDK, create the software BSP using the standalone operating system; Enable the profiling options.



5-1-2. Select File > New > Board Support Package.

5-1-3. Notice Standalone_bsp_0 in the Project name field and click Finish with default settings.

A Board Support Package Settings window will appear.

5-1-4. Select the Overview > standalone entry in the left pane, click on the drop-down arrow of the enable_sw_intrusive_profiling Value field and select true.

Figure 4. Setting up for profiling

5-1-5. Select the Overview > drivers > cpu_cortexa9 and add –pg in addition to the –g in the extra_compiler_flags Value field.

Figure 5. Adding profiling switch

5-1-6. Click OK to accept the settings and create the BSP.



Create the Application Step 6

6-1. Create the lab6 application using the provided lab6.c, fir.c, fir.h, fir_coef.dat, and xfir_fir_io.h files.


6-1-2. Enter lab6 as the project name, select the Use existing standalone_bsp_0 option, and click Next.

6-1-3. Select Empty Application in the Available Templates pane and click Finish.


6-1-5. Expand the General folder and double-click on File system, and browse to the c:\xup\adv_embedded\sources\lab6 directory.

6-1-6. Select lab6.c, fir.c, fir.h, fir_coef.dat, and xfir_fir_io.h, and click Finish.

The program should compile successfully and generate the lab6.elf file.

Run the Application and Profile Step 7

7-1. Place the board into the JTAG boot up mode. Program the PL section and run the application using the user defined SW_PROFILE symbol.

7-1-1. Place the board in the JTAG boot up mode.



7-1-4. Make sure that the bitstream file path points to the c:\xup\adv_embedded\labs\lab6\lab6.sdk\SDK\SDK_Export\hw_platform_0\system_wrapper.bit file.

7-1-5. Click on the Program button to download the bitstream and program the PL section.

7-1-6. Select the lab6 application, right-click, and select C/C++ Build Settings.

7-1-7. Under the ARM gcc compiler group, select the Symbols sub-group, click on the + button to open the value entry form, enter SW_PROFILE, and click OK.

This will allow us to profile the software loop of the FIR application.



Figure 6. Add user-defined symbol

7-1-8. Under the ARM gcc compiler group, select the Profiling sub-group, then check the Enable Profiling box, and click OK.

Figure 7. Compiler setting for enabling profiling

7-1-9. Select Run > Run Configurations… and create a new configuration.

7-1-10. Select the Profile Options tab. Click on the Enable Profiling check box, enter 100000 (100 kHz) in the Sampling Frequency field, enter 0x10000000 in the scratch memory address field, and click Apply.

Use the high end address as the scratch memory address.

Figure 8. Profiling options

7-1-11. Click the Run button to download the application and execute it.



When program execution has completed, a message will be displayed indicating that the profiling results are being saved in gmon.out file at the lab6\Debug directory.

7-1-12. Click OK.

7-2. Invoke gprof and analyze the results.

7-2-1. Expand the Debug folder under the lab6 project in the Project Explorer view, and double click on the gmon.out entry.

Figure 9. Invoking gprof on gmon.out

7-2-2. The Gmon File Viewer dialog box will appear showing lab6.elf as the corresponding binary file. Click OK.

7-2-3. Click on the Sort samples per function button ( ).

7-2-4. Click in the %Time column to sort in the descending order.

Note that the fir_software routine is called 60 times, 24 samples were taken during the profiling, and on an average of 4.000 microseconds were spent per call.

Figure 10. Sorting results

7-2-5. Change the sampling frequency to 1000000 (1 MHz) and profile the application again.



7-2-6. Invoke gprof, select the Sorts samples per function output, and sort the %Time column.

Notice that the output has better resolution and reports more functions and more samples per function calls. Note that the number of calls to the filr_software function has not changed but the number of samples taken increased from 24 to 378, and the average time spent per call is 6.3 microseconds.

Figure 11. Profiled results with 1 MHz sampling frequency

At this stage, a designer will decide if the FIR function should be ported to hardware accelerator or not.

7-3. Profile the application using the hardware FIR filter IP by removing the user defined SW_PROFILE symbol.

7-3-1. Select the lab6 application, right-click, and select C/C++ Build Settings.

7-3-2. Under the ARM gcc compiler group, select the Symbols sub-group, select SW_PROFILE, and delete it by clicking on the delete button.

This will allow us to profile the hardware IP of the FIR application.

Figure 12. Deleting the user-defined symbol

7-3-3. Select Run > Run Configurations and click the Run button to profile the application again.

7-3-4. Invoke gprof, select the Sorts samples per function output, and sort the %Time column.

Notice that the output now shows filter_hw_accel_input function call instead of the fir_software function call. Note that the number of calls to the filter function has not changed but the average time spent per call is 1.799 us as the filtering is done in the hardware instead of the software.



Also notice that the amount of time spent in the filtering function reduced from about 92% to 0.28%.

Figure 13. Profiling the application with the hardware IP

7-3-5. Close the SDK and Vivado programs by selecting File > Exit in each program.


Conclusion This lab led you through enabling the software BSP and the application settings for the profiling. You went through creating the hardware which included the hardware IP and was later profiled in the application. You analyzed the profiled application output.

advanced embedded system design on zynq using vivado workshop zybo course...

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