advanced cell structures for dynamic rams

Advanced Cell Structures for Dynamic RAMS Nicky C. C . Lu

Introduction

In the last decade, semiconductor memories have been the fastest growing segment of the semiconductor industry, with the large expansion due to the rapid growth of the digital electronics market with increasing applications. Of various types of semiconductor memories, dynamic random access memories (DRAMs) have been produced in the largest quantity because of their high density, low cost, and fast performance. A key contributor to these features is the one-transistor memory cell, which uses a capacitor for storing different amounts of charge to represent the distin- guishable binary logic states [l]. The cell density of DRAM chips has mostly quadrupled for each new generation, which has occurred almost every 3 years based on historical production data. The chip area, however, has increased only about 1.4X per generation in order to promote high chip productivity due to yield, package, and cost concerns. This high chip productivity has not been achieved by other com- peting approaches that attempt to deviate from this historical trend, such as wafer scale integration or laser- recrystallized three-layer SO1 DRAMs [2]. As a result, the individual memory cell area has needed to be reduced by almost 3X for each generation. Figure 1 shows these his-

Year for the First Chip Published By Company Labeled with'

1976 1977 1980 1984 1986 1987 7

1 I I I I

\= Toshiba'

Published. Chip t Cell

M os

Fig. I Chip arid cell areas swrsus both chip dciisity and the year i~herr the chip icifls first published. The chip nrca has iizcrcnsed only nbout 1 . 4 5 per geireratioti ichile the hits per clzip hn i~e qundrupled. This high chip produrtii1ity /ins resulted priniarily from a 3 X reductiori in the cell awn due to both litliogrymphy ndzinnces arid iiinoi1ntioe cell structures.

torical trends of both the chip and cell areas. The other interesting observation from Fig. 1 is that the period between each generation disclosed in publications has decreased from 4 years between 256-Kb and l-Mb chips to only a year from 4-Mb to 16-Mb chips. This dramatizes the intensive investments of R&D efforts on DRAM design and technology in worldwide semiconductor development.

In order to reduce the cell area by 3X each generation, the minimum feature on the chip has been reduced by almost 1.4X per generation through improvements in pho- tolithography. This has effectively shrunk the cell area by 2X, but the remaining 1.5X cell area reduction has been achieved through cell structure innovations. On the other hand, a successful cell design demands more than just shrinking the cell area [51]. Because significant noise is generated from radiation and thermal sources as well as from circuit operations, especially as chip density increases, the sensing signal has not been reduced but has been kept almost constant in order to maintain a reasonable signal- to-noise ratio. The bitline capacitance that the storage charge shares for providing enough sensing signal has remained almost constant or has increased with each generation due to more bits per bitline, though the bitline capacitance per bit has been reduced because of the decreased cell area. Consequently, the amount of charge stored in the cell has remained almost constant for successive generations. The historical trend study shows that the effective insulator thickness for the storage capacitor has been scaled down by about 1.5X per generation, partially because of improvement of the insulator dielectric constant. Therefore, for a constant storage voltage, the capacitor storage area can be scaled down by the same amount. However, because the cell area must be reduced by 3X, the ratio of the capacitor storage area to the cell area, which is one of the key figures of merit for the DRAM cell, needs to increase by almost 2X for each generation.

Design of a successful DRAM cell structure becomes even more difficult as the chip density is increased from 1 Mb through 4 Mb to 16 Mb because the power supply voltage V,,, must be scaled down from 5.0 to 3.3 V, either on or off the chip, because of device reliability concerns 1191. TO give an example: for a 4-Mb chip of 75 mm', the cell area has to be below 10 km2 while the storage capacitance has to be more than 65 fF at a V,,,, of 3.3 V in order to provide stored charge of more than 150 fC. With a storage insulator of 10 nm effective oxide thickness, the capacitor storage area needs approximately 20 kin', which is about twice the cell area. The problem is going to be worse for 16-Mb DRAMs. Through cell structure innovations, however, the problem has recently been shown solvable, thus making the coming era of 4-Mb/l6-Mb chip production expected in the near future.

This article describes recent major progresses in this important and exciting area -advanced DRAM cell structures, with a special focus on three-dimensional approaches. A projection of future trends of cell structures is developed,

27 JANUARY 1989 8755-1996 89 0100-002751 00 1989 IFEE

mainly from the author's personal viewpoint - though such projections are always risky because of rapid and explosive innovations in DRAM cell structures.

Cell Design Criteria

Because of its importance, DRAM cell innovations have continued to grow at an ever-increasing pace since the first disclosure of the basic one-transistor cell structure [l]. This can be seen from Ref. [3], which surveys more than 400 patents and publications. A retrospect on the origin of the DRAMs and present trends in megabit DRAMs are de- scribed in Refs. [4] and [5], respectively. References [6] and [7] reviewed the cell structures and their design before 1979, and two recent reviews on the progress of three-dimensional cell structures are given in Refs. 181 and [9].

In order to optimize a cell structure, understanding the criteria for judging a cell design is important. The following equation summarizes the cell design basics:

where V,,, is the sensing signal; AV is the noise due to leakage, reference cell mismatch, radiation, and V,,, vari- ations, etc.; C, and C,, are the storage capacitance and bitline capacitance (including sense amplifier loading); V , is the storage signal; E is the dielectric constant; A is the capacitor storage area; d is the thickness of the capacitor insulator. A large V,,,, is achieved by reducing AV, C,,, and d, as well as enlarging E, A, and V, , though the magnitude of V, l d is limited by the maximum dielectric strength. Be- sides the cell area reduction and signal enhancement, a good cell requires:

low leakage current and soft error rate (SER) * high immunity to noises due to cell-plate voltage bump,

wordline and bitline swings, etc. fast charge transfer and small R and C parasitics, since chip access becomes faster [40] in spite of increased density and area

* process simplicity/manufacturability - low-risk estimate under a tight development schedule * scalability/extendability * driving technology also suitable for SRAM and logic ap-

The last four factors are playing a more important role than before as DRAMs move toward ULSI, because expensive capital investment cannot be returned quickly and an ac- cumulated manufacturing data base cannot be generated shortly. As a result, the cell selection becomes more com- plicated, especially under intense DRAM competitions where the winner is generally decided by early product delivery.

plications

Three-Dimensional Cell Structures

It i s widely realized that starting with the 4-Mb DRAM, the cell design targets based on historical extrapolation are hardly achieved by the conventional cell structure using a planar access transistor and a planar capacitor cell in a nearly two-dimensional structure (Fig. 2 ) . It is clear, however, that the one-transistor memory cell has a unique potential for

28

Fig. 2 cell is used in most existing I -Mb DRAM products.

Planar capacitor cell using two polysilicon layers. This type c

rn

Fig. 3 between two polysilicon layers and stacked over the access transistor.

Stacked capacitor cell (STC) [ I O ] , [ I l l . The capacitor is made

cell area reduction because of its simple structure; it has only one transistor and one capacitor. Advanced cell structure design activities are therefore focused on how to ar- range these two components by using advanced processing techniques to meet the design criteria. The major effort has been to use the third dimension in the cell structure.

Stacked Capacitor Cell

One approach is to stack the capacitor over the access transistor (STC cell) (Fig. 3) [lo], [ll]. So far, the most advanced design was done in a 16-Mb chip using at least four layers of polysilicon with a cell area of 4.2 kmZ in 0.5-km design rules [12]. Advantages of this cell are the use of the space over the transistor for the storage capacitor area, low SER, and the configuration is particularly suitable for the use of a high dielectric-constant insulator [13] between two poly layers without the dielectric contacting the bulk silicon. The difficulties are how to manage the large surface topography and how to keep high dielectric breakdown between poly layers with scaled insulator thickness. The resulting large surface topography needs to be managed by limiting the step height on the wafer, usually below 1 pm, which is the practical focus depth of an i-line stepper. One solution used in Ref. [12] is to recess the surface of the memory array area about 0.5 Fm from that of the peripheral area by including an extra selective oxidation step before the array fabrication. Another difficulty for the STC cell is

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that one buried contact without self-alignment is needed for the capacitor connection per cell, thus making the cell area hard to scale. In moving toward 16-Mb DRAMS and beyond, the cell storage area will be restricted unless the capacitor storage polysilicon electrode is made thick enough to increase the sidewall areas for charge storage or a low- leakage, very high dielectric-constant storage insulator can be used.

Trench Capacitor Cell

Another approach is to use a three-dimensional trench capacitor (CCC cell) (Fig. 4) [14], [15]. Since all four sidewalls and the bottom of the trench can be used for the capacitor electrode, the storage area is greatly enhanced with even reduced planar surface area for the capacitor. Both the etching uniformity of millions of trenches, which requires a large depth-to-width aspect ratio, and the high dielectric breakdown have been demonstrated [16] in many experimental I-Mb to 16-Mb chips, but only until recently have some 1-Mb DRAM chips using trench capacitors en- tered volume production, proving trench cell manufacturability. However, there are some design concerns in this original trench capacitor structure. Because the signal charge is stored at the trench surfaces in the bulk silicon, the ex- panded storage area results in high susceptibility to minority-carrier leakage disturbance, leading to high leakage and SER. Moreover, unless a deep isolation is used, the minimum distance between trenches and from the trench storage node to the active devices of adjacent cells is limited because of possible junction punchthrough (Fig. 4). One solution is to increase the background doping concentration to narrow the depletion region [17]; however, this increases the electric field around the junction, which may cause avalanching. Another solution is to form Hi-C doping profiles at the trench surfaces (Fig. 5) by using more com- plicated sidewall doping techniques, though the trench spacing can still be limited by the diffusion depths of doping profiles and depletion regions. However, improvements in other parts of the cell, such as bitline pitch reduction, have resulted in the cell being made in a 8+mZ area in 0.8-k.m design rules for a 4-Mb chip [18].

Substra te-Pla te Trench-Capacitor Cell

In the trench-capacitor cell, it is necessary to minimize the punchthrough and to reduce leakage and SER. Placing

Fig. 4 Trench capacitor cell (CCC) 1141, 1151 with arz adjacent trench capacitor. Sirice four sidewalls and the bottom of the trench are used for the capacitor electrode, the storage area is greatly enhanced wi th reduced planar surface area for the capacitor.

JANUARY 1989

Polycide Poly II Bit I i ne I

Fig. 5 Diffusion-storage trench-capacitor cell 1181. Doping profiles are formed at trench surfaces to diminish the luiictiori puriclithrough between trenches.

the cell array within a CMOS well should substantially reduce this sensitivity. However, containing such trench capacitors entirely within the well severely limits both the depth of the trench and the shallowness of the well. A similar restriction is encountered in implementing the cells in an epitaxial CMOS technology, where a heavily doped substrate is used to reduce substrate noise and latch-up susceptibility. For this case, the trench capacitor must be confined to the lightly doped epitaxial layer above the substrate in order to obtain either an inversion layer or metallurgical junction for charge storage. Both of these constraints lead to a disadvantageous trade-off between storage capacitance and desired CMOS characteristics.

To overcome these problems, the substrate-plate trench- capacitor (SPT) cell made in a thin-epi n-well CMOS technology has been introduced (Fig. 6) [19]. The trench capacitor extends from the surface through the well and epitaxial layer into the substrate. The cell stores signal charge on the polysilicon inside the trench and uses the bulk silicon, especially the heavily doped substrate, as the other capacitor plate electrode. This substrate plate is firmly grounded to provide a solid potential for the storage capacitor. Since most of the storage area is inside the insulator-lined trench, the distance between insulator-bounded node sides in adjacent trenches can be greatly reduced below that for diffusion or inversion trench capacitors, and the minority-carrier collection area also is greatly reduced. In addition, configuration of the array using PMOS devices in an n-well results in a metallurgical junction between the

29

c ce

e B a s

Fig. 6 Substrate-plate trend-capacitor cell (191. This concept of using tlie trcwch capacitor is to store the signal charge on the polysilicon inside tlw trench and to use tlic hulk silicon, especially the hcardy doped sirh- strate, a s tlic capncitor counter-electrode. Also, the access device is tnnde inside an n-well, wliich enhances the cell i inmunity to noise disturbances.

substrate and the array to provide a barrier to impede minority carriers generated in the substrate. It also reduces the volume of silicon within the well from which cells may collect minority carriers since the well-to-substrate junction also acts as a collector. Thus, the SPT cell is inherently a low-leakage, low-SER structure. The cell cannot easily em- ploy a half-V,, plate, however. The signal loss may not be significant because the half-V,, plate approach loses some net storage signal to offset the plate bump noise [ZO], and the insulator thickness may not be scaled down propor- tionally to the field stress when the effective oxide thickness has been reduced to less than 10 nm. For the SPT cell, an important design effort is to minimize the access device subthreshold leakage in the well without trading off performance. This has been achieved in a 65-ns 4-Mb DRAM chip [ Z l ] with a cell area of 10.5 km2 by 0.8-km design rules. Reference [41] shows that by using this SPT cell with its storage capacitor merged into the transistor isolation area, this area can be shrunk to 4 pmZ using design rules of 0.5 pm, and can achieve 16-Mb chips.

The concept of storing signal charge on the poly in a trench was published simultaneously in two other different cell structures; one is called the buried-storagi. electrode (BSE) cell [22], [23], and the other is the trencli-transistor cell (TTC) (Fig. 7) [24], [25]. Both were implemented in 4-Mb chips with cell areas of 10.6 pmz in 0.8-pm design rules and 9 pm’ in 1.0-km design rules, respectively. The TTC cell makes a vertical transistor and capacitor in a deep trench, and its unique feature of using a vertical transistor will be ad- dressed later.

If the SPT cell were not located within a well (Fig. 8), with a capacitor configuration similar to that of the BSE or TTC cells, some extra design efforts would be needed. First, in DRAMS, it is essential to apply an array back gate bias to reduce the occurrence of minority-carrier injection into the array [26]. The application of this back gate bias, which is usually generated on-chip, brings with it an inherent noise contribution [23]. If the substrate is used both as the array bulk and the capacitor plate, this noise is strongly coupled directly to the storage node, resulting in a loss in usable signal margin [20], [23]. Some special voltage limiters were designed to minimize the substrate voltage var- iation for the BSE cell [42]. In the SPT cell, the p substrate,

30

I Bi t l i ne

, Word1 ine

n + Diffused Bit I i ne

Channel

Buried Contact

Storage

U 1 - Fig. 7 yacitor, euen the cell access trntisistor t irci i~n~s iicrticnl.

Trencli-transistor cell (241. I n addition to n rwtiral trcncli cn-

Nord I i ne

Silicide

Depletio Region

*

4-l

t

which is a solid ground, acts as the capacitor plate, while the n-well serves as the array bulk to which the generated back gate bias is applied. Second, because of the work func- tion difference between the p + substrate and the n ’ poly used in the BSE cell capacitor, compared to the p poly in the SPT cell, a higher voltage is dropped across the storage insulator in the BSE cell. The voltage difference across the thin insulator becomes larger when a boosted wordline is used or a substrate bias is used for the BSE cell. This con- straint limits scalability of the insulator thickness because

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of possible dielectric breakdown. Third, since along the trench sidewalls in the BSE or TTC cell there is a gated- diode structure (which has a wide depletion region in the lightly doped epitaxial layer), leakage can become a serious concern, especially when the storage node voltage is high and the depletion region is at its maximum width 1371. In contrast, along the trench sidewalls in the SPT cell, there is a turned-off parasitic PMOS transistor with its source tied to the gate. The voltage across the capacitor insulator is lower and the depletion region is narrower due to a high retrograde well doping concentration. The leakage is, thus, smaller, especially with protections by the n-well, which can either reject or sink carriers to diminish the disturbance to the storage node [43].

Dielectrically Insulated Trench Cell or Buried Stacked Capacitor Cell

After understanding the SPT concept, it is not difficult to understand several recently published cells, which have their trench capacitors configurated as either the dielectrically insulated trenches (Fig. 9) [46], [47] or the buried stacked capacitor trenches [48]-[50]. Both trench capacitors have the signal charge stored on a polysilicon electrode inside the trench, which is connected to the source region of the access transistor. The key difference from the SPT concept is that both capacitors use another polysilicon layer inside the trench for the capacitor counter-electrode plate instead of using the heavily doped substrate in the SPT cell. The dielectrically insulated trench-type cell has its polysilicon plate surrounding the storage polysilicon electrode with its plate contact to either the wafer substrate [46] or a half-V,, biased buried layer [47]. The buried stacked capacitor cell has its storage polysilicon layer surrounding the counter- electrode polysilicon plate, which is identical to making the stacked polysilicon layers in the STC cell inside the trench capacitor. As a result, this type of cell faces the similar process challenge of making a reliable thin insulator between two polysilicon layers. Since there are two or three polysilicon layers inside the trench, the trench opening will be ultimately limited to a certain size. In addition, the processing inside the trench becomes more evolving. This type of cell has been made in some 4-Mb [48] or 16-Mb [49] DRAMS.

Folded Capacitor Cell

Instead of using the four sidewalls and the bottom of a trench capacitor for charge storage, a folded capacitor cell (FCC) was proposed to make the storage capacitors on the vertical wall of a long trench (Fig. 10) [27], [28]. Adjacent cells, which are isolated by the p regions on the bottom of the trench and by the plate electrode inside the trench, use the opposite sides of the same trench for signal-charge storage. The cell has small areas, but is made in an open bitline structure that is less immune to noise [26]. Since the cell does not use all four sidewalls and the bottom of a trench for storage, the capacitance can be limited, unless a deeper trench is used; but a deeper trench requires a deeper isolation, which needs more difficult technology. Recently, a more advanced design following this concept has shown large cell capacitance. It is the FASIC cell (folded-bitline adaptive sidewall-isolated cell) that achieves effectively larger sidewall area in a grid-type trench structure (Fig. 11) [29]. The FASIC cell uses several advanced processing steps,

JANUARY 1989

Bit line 1

Fig. 9 Dielectrically insulatcd trrricli cell (46/. Tlic kcy d@rerice hcrc f rom the SPT cell is that the tverich capacitor uscs ariothcr pol!/silicon laycr inside the tretich as the countcr-electrode iristcad ctf iisirig the h m ? $ y doprd substrate as in the SPT cell. As n rcsulf , the capacitor IS t17nde bd71wti

two polysiliron layers like iri the STC cell.

Si02 (Trench)

X X '

Bitline Poly Si Polycide (Wordline)

Fig. 10 vertical walls of a lorig troich arid isrilntc~f by rr7crgcd oxirlc isolntiori.

Foldrd capacitor cell /27]. Storn'yc capacitors arc rtiilde 011 f l w

such as oblique ion-implantation, deep isolation with groove refill, and some processing inside the trench. The cell may need a higher mask count and be sensitive to alignment tolerance. It has been demonstrated in a 4-Mb chip with the cell area of 10.9 km2 in 0.8-km design rules by using a grid trench only 2 )*m deep, though the cell does not avoid storing the signal charge in the bulk silicon.

31

Bottom Isolation

Fig. 1 I Folded-bitline adaptive sidewall-isolated cell [29]. The storage aren is extended to the transistor isolation region, which is parallel to the bitline direction.

Isolation-Merged Capacitor Cell

Another approach to merge the storage node and isolation as in the FCC cell is the isolation-merged vertical capacitor (IVEC) cell (Fig. 12) [30], [31], which extends both the storage and the plate electrodes in a grid-type trench surrounding the access transistor. The storage node is a poly layer inside the trench instead of being in the bulk silicon, thus having a low SER. The storage capacitance is large; however, the storage capacitor plate laid on the sidewalls of the access device forms a gated-diode structure across the ends of the device channel, thus raising the pos- sibility of parasitic channel sidewall leakage [30]. The cell area is hard to shrink in direct proportion to the feature size because each cell needs a bitline contact and the design relies on several critical overlays. The cell process is com- plex since it needs several critical processing steps within the trench. Uniformly high dielectric breakdown may be difficult to achieve for the storage insulator between poly layers in a trench. Nevertheless, the first 16-Mb DRAM has been realized by employing the IVEC cell with only a 4.Y- pm2 area in 0.7-pm design rules, in spite of using 10 levels of E-beam direct writing among 20 masking steps. Each cell still uses one bitline contact but has a small area by employing aggressive contacts that are borderless to both isolation and wordline [31]. On the other hand, several cell structures using a similar approach avoid the possible channel sidewall leakage by either truncating the storage node from the sidewall edges, sacrificing capacitance, or achieving conventional oxide isolation butted to the channel regions [2Y], [32], such as the surrounding Hi-C capacitance (SCC) cell in a 4-Mb chip [32]. An advanced SCC cell has also been made in a 16-Mb DRAM with a 3.3-pmZ area by using 0.5-pm design rules.

Buried Capacitor or Stacked Transistor Cell

Instead of stacking the capacitor over the access device, much like the STC cell, it has been proposed to have the capacitor buried under the access device or, equivalently, to stack the access device over the capacitor. Figure 13 shows a stacked SO1 substrate-plate trench-capacitor (SS-SPT) cell [33] and a similar approach realized the SSS (stacked switching transistor in SOI) cell [34]. The cell can have a

32

Word I i ne Si02

Fig. 12 Isolation-merged vertical capacitor cell /301, [31/. The cell PI- tends both the storage and the plate rlectrodcs in n grid-type trench sur- roundirig the access transistor.

Bit l ine Wordline Thin Insulator

I A /

Fig. 13 SOI f i ln i s ~ ~ l i t h adequate inaterial qurzlity f o r subniicrori dcvices.

Stacked SOI substrate-plate trench crll / 3 3 ] . If is linrd to acliicn~e

small area, but its success depends on the quality of the silicon films obtained over an insulator layer. The cell can have very low SER and leakage with a simple isolation scheme. However, an SO1 access device is required with a most-likely floating substrate. In addition, it is very difficult

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to obtain adequate SO1 film quality for submicron devices. Recently, a breakthrough in the development of a selec-

tive epitaxy-over-trench (EOT) technology has realized an ultra high density 3D buried trench (BT) cell. Figure 14 shows a crosssection of this cell structure [52]. This BT cell has a horizontal access transistor fabricated in an epitaxial layer over a buried trench capacitor [44], [45], [52]. As a result, the cell area is basically that of an access transistor alone. This cell structure based on the EOT technology breakthrough is promising for scaling DRAM density to 64 Mb and beyond.

Trench-Transistor Cell

Most design efforts on the above cells are focused on decreasing the planar area of the capacitor a n d o r optimizing the configuration of the capacitor to the access device, while the planar access device is retained. This is because the planar device technology developed in the last three decades gives excellent device features, such as small-geometry gates, self-aligned source/drains, shallow junctions, shallow threshold implant adjustment, spacer-defined lightly doped drains (LDD), etc., all of which result in an optim- ized MOS transistor, which can provide high performance, uniformity, and reliability. However, DRAM researchers can foresee that for further scaling down the cell area while a high ratio of on-to-off currents of the access device has to be preserved, it may be unavoidable to change the planar

access device into a vertical one. Though this was tried to some extent in the VMOS DRAM cell [35], the sharp edges at the bottom of the V-groove resulted in severely degraded oxide integrity, which caused manufacturability problems. At the same time, improved lithography resulted in reduced cell areas, and the VMOS VLSI efforts eventually were terminated. Recently, the TTC cell (Fig. 7) and a trench- transistor cell with self-aligned contact (TSAC) [36] revived efforts toward the vertical transistor. The TSAC cell uses a shallow trench forming the access device channel to improve both short and narrow channel effects [36]. The nov- elty of the TTC cell is that the vertical access device is above the trench capacitor in a single deep trench. The cell approaches the ideal memory cell structure of a cross point at the crossing of a bitline and a wordline. Since most published information was based on the first version of the cell, there are some concerns that the trench is deep but the capacitance is not large [38]; performance may be slower because of large wordline and wordline-to-bitline capaci- tances, device uniformity [ZS], and the buried lateral contact may limit the scaling. The cell stores charge on the poly inside the trench; however, it is not located within a well and, therefore, can suffer substrate-plate bump effects if a substrate-bias generator is used [23 ] , high-voltage stress across the dielectric [38], and high leakage especially during high-voltage screening [37]. The cell is more suitable for an open bitline layout in order to fully gain the cross-point area advantage, which results in the disadvantage of using

Fig. 14 Buried trench-capacitor cell 1441, (451,1521. A new breakthrough of using an epitaxy-over-trench (EOT) technology results in high-quality epitaxial f i lm, which allows a bulk horizontal access tramistor made on top of the treiich copacitor.

JANUARY 1989 33

an open bitline, such as less noise immunity. Improved peripheral circuit design results in a pseudo folded bitline to the sense amplifier [25]. Both the TSAC and the TTC cells suffer high mask count due to using vertical devices in the array but having planar devices in peripheral circuits. The TTC cell was implemented in the first 4-Mb chip [25].

Future Trends of Cell Structures

There have been many other novel cell structures and many more will surely emerge; however, future trends can be projected from the above study as shown in Fig. 15. As a result of using the trench capacitor, the storage area depends more on the technology enhancement to realize a high-aspect-ratio trench than on enlargement of the planar area, which can thus cope with the required 2 x increase

I

Fig. 75 Trend of cell structure denelopnieiit. UTJ to I M h in density, m s t DRAM cells itse plnnar cnpacitors. Beyond 1 Mh , trench capacitors arc’ ncedcd to proziidt’ cnoirgh chnrgc storage zuith wen n reduction of the p h a r surfacc area ocrirpird by the capacitor. A n a u concept of optimizing i m of the trcnch is to store tlic signnl charge o n th t polysilicori electrode insidc the trmch irzstcnd of being stored i n the bulk silicon, which results in better protcctioli of thr stored charge. A projectiori to 64 M h and beyond S ~ O ~ U S that it is necessary to hnijt, tither a cell using a horizontd access transistor oucr the trench or a ce// z ~ i t h a uevtical access fransistor.

per generation in the ratio of the capacitor storage area to the cell area, at least up to 256-Mb DRAMs. As the chip paclung density increases, high immunity of the cell to leakage, SER, and various noises becomes difficult, which makes the concept of storing signal charge on the polysilicon inside the trench more attractive. As device lateral dimensions continue to be scaled down, it is necessary to reduce the surface topography. In the SPT cell, the storage node and capacitor plate are contained entirely below the silicon surface, allowing a planar surface for subsequent processing steps. Thus, lithographic steps can be per- formed with tighter tolerances and greater density can be achieved. Also, charge storage within the insulator-lined trench, as in the SPT cell, provides freedom from many of the doping and geometry limitations, which occur with diffused or inversion layer storage nodes, or even in the IVEC- type cells. Charge storage in the silicon around the trench would require that the capacitor reside completely within the lightly doped region of the array bulk, either to permit formation of an inversion layer at a n acceptable plate voltage for inversion layer storage or to avoid signal loss due to avalanche breakdown of the metallurgical junction for storage on a diffused node. Minimization of channel sidewall conduction in the IVEC cell (the gated-diode structure mentioned previously) can dictate the bulk or channel doping concentration. Removal of these restrictions permits the CMOS doping profiles to be determined by optimum device design considerations, thus permitting full advantage to be taken of epitaxial CMOS technology, which can be used as the base technology for SRAM [39] and logic applications, aiding the traditional rei- of DRAMs as the gen- eral technology driver. Therefore, from the author’s viewpoint, the SPT cell concept can be one of the best choices for 4-Mb DRAMs and beyond, though further technology or layout optimization must be used for extension [41]. By strong demands for an ultrasmall cell as the chip density surpasses 16 Mb, an era of using either a buried trench storage cell [44], [45], [52] or a vertical access device [25], [36] will arise.

Con c 1 us i o n

In order to fabricate DRAMs beyond 1 Mb at an effective cost, the one-transistor memory cell in a three-dimensional structure is essential as technology features move below 1 km. The trench capacitor can be used to reduce cell area without decreasing the storage capacitance, and an optimum configuration uses polysilicon within the trench as the storage node and a heavily doped bulk silicon as the capacitor plate counter-electrode. Locating the array in the well of a CMOS process further increases the cell noise immunity and separates the array bulk from the substrate plate, which thus can be firmly grounded. Significant efforts will be devoted to retaining the planar bulk transistor as the access device because of its high performance and long manufacturing experience. In the near future, however, a vertical or stacked access transistor over the trench capacitor will become necessary. No ”fundamental” bar- riers have been observed for scaling technology down to quarter-micron dimensions for extending DRAMs to 256 Mb; however, a question mark leaves a 1-Gb DRAM, which is projected to need a cell size around 0.15 km2!

IEEE CIRCUITS AND DEVICES MAGAZINE 34

Acknowledgments

The author wishes to thank L. Terman and H. Yu for their support and helpful discussions. He also wishes to thank his colleagues, W. Noble, W. Hwang, G. Bronner, T. Rajeevakumar, W. Henkels, and S . Dhong, for their constant discussions.

References

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JANUARY 1989 35

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Nicky C. C. Lu received his B.S.E.E. from National Taiwan Uni- versity in 1975 and the M.S. and Ph.D. degrees in electrical engi- neering from Stanford University in 1978 and 1981.

He joined IBM at T.T. Watson Research Center as Research Staff Member in 1982 and has been Manager of Dynamic Memory in IBMs Research Division since 1984, leading exploration of new designs and technologies for DRAMS and involving product development. His other technical interests focus on 3D device structures and technologies, physics of polysilicon devices, and ASIC and nonvolatile memories. He is presently on an assignment to be a Member of the Technical Planning Staff for the Director of Re- search, IBM. Prior to that, he served in the ROTC from 1975 to 1977. From 1977 to 1981, he was a Research Assistant at the Inte- grated Circuits Laboratory of Stanford University. Then he visited National Chiao-Tung University as Associate Professor. He has authored over 40 technical papers and over 70 invention disclo- sures including six U.S. patents issued and many more pending.

Dr. Lu received a Stanford Fellowship, six IBM invention achievement awards, two IBM division awards, and an IBM out- standing innovation award. He has served on the ISSCC Technical Program Committee. He has been a panel speaker, moderator, and organizer for panel discussions in recent ISSCC VLSI Circuit Sym- posium and VLSI Technology Symposium. He is a member of Sigma Xi and Phi Tau Phi and is a Senior Member of the IEEE.

36 IEEE CIRCUITS AND DEVICES MAGAZINE

advanced cell structures for dynamic rams

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