advance processors - multi tasking

Parul Institute of Engineering & Technology

Subject Code : 150701

Name Of Subject : Advance Processors

Name of Unit : Multitasking

Topic : Extension & Input- Output Permissions

Name of Student : Agrawal Swapnil J.

• Extension of 8086 Processor

• MULTITASKING

• INPUT/OUTPUT

• INPUT/OUTPUT PERMISSION

Sub: Advance Processors Topic: Extension & I/O Permission

CONTENTS


Extension of 8086 Processor

The programming model of the 8086 through the Core2 microprocessor including the 64-bit extensions.


MULTITASKING– Task :

• a program module ( the execution of a sequence of steps) which is running, or waiting to run while another program is running

• invoked by an interrupt, exception, jump, or call


MULTITASKING— Program :

―logical entity that can have many representations: ex) a source code file or object program file

–A program becomes a task when it is actually available for execution


MULTITASKING


MULTITASKING– Two types of task-related descriptors

• Task State Segment(TSS) descriptor• Task Gate

– Task Switch• new environment• not re-entrant• does not push anything on the stack• processor state information - TSS


MULTITASKING

• Registers and Data Structures

– Task State Segments– TSS descriptors– Task Register– Task Gate descriptors– Use of the multitasking mechanism is optional


MULTITASKING• Task State Segment

– Dynamic Fields: the processor updates with each task switch• general registers• segment registers• flag registers• EIP• the selector for the TSS of the previous task


MULTITASKING• Static Fields: the processor reads, but does not

change• LDT selector• stacks for privilege levels 0, 1, and 2• T-bit (debug trap bit): cause the processor to

raise a debug exception when a task switch occurs

• I/O permission bit map


MULTITASKING

TSS


The 80386 TSS formatlink

esp0ss0

esp1ss1

esp2ss2

PTDBEIP

ss0 ss0ss0 ss0ss0 ss0ss0 ss0ss0 ss0ss0 ss0ss0 ss0ss0 ss0ss0 ss0

ESCSSSDSFSGS

LDTRIOMAP TRAP

EFLAGSEAXECXEDXEBXESPEBPESIEDI

I/O permission bitmap

= field is ‘static’

= field is ‘volatile’

= field is ‘reserved’

04812162024283236404448525660646872768084889296100

26 longwords

We will need to initialize the SS0 and ESP0 fields (for our ‘hlt’ instruction)

We will need to initialize the IOMAP field and the I/O permission bitmap (for use of ‘in’ and ‘out’)

We won’t have to initialize most of these fields (since our guest doesn’t do ‘task-switching’)


MULTITASKING• TSS Descriptor

– Busy Bit : whether the task is busy

– Task is not reentrant– Limit 67H (size: 68H: 104)– TSS descriptor : only in the GDT

SEGMENT LIMIT 15 .. 0SEGMENT BASE 15 .. 0

BASE 23..16 BASE 31..24 G X 0 LIMIT19..16

P DPL 0 TYPE1 0 B 1

03

47

AVL

023 1615 8 72432


MULTITASKING• Task Gate Descriptor

• The RPL of the TSS selector in the Gate descriptor is not used

• The DPL of the destination TSS descriptor is not used• DPL CPL and the selector’s RPL

ReservedTSS selector

Reserved Reserved PDPL

03

47

0 0 1 0 1


MULTITASKING• Task Switching

– Jump or Call to a TSS descriptor

– Jump or Call to a Task Gate

– Interrupt or Exception indexes to a Task Gate in the IDT

– IRET when the NT flag is set


INPUT/OUTPUT• Input / Output Model

– Method of addressing I/O ports– Instructions which perform I/O operations– The I/O Protection Mechanism

• I/O Instructions– IN, OUT– INS, OUTS (Block I/O)


INPUT/OUTPUTProtection and I/O

– Two protection mechanism

• The IOPL field in the EFLAGS - I/O instructions

• I/O permission bit map of a TSS - individual ports

• Separated I/O address space Vs. memory mapped I/O address space


INPUT/OUTPUT– I/O privilege levels

• Typical protection ring model: 0 or 1 have access to the I/O instructions

• Instructions can be executed only if CPL IOPL

– IN, INS, OUT, OUTS, CLI, STI : “I/O sensitive” instructions


INPUT/OUTPUT– IOPL : can be changed only with the POPF

and IRET

• No procedure may change its IOPL unless it is running at privilege level 0.

• Violation : No exception, the IOPL simply remains unchanged


INPUT/OUTPUT– IF Flag :

• The POPF also may be used to change the state of the IF flag(as can the CLI and STI)

• IOPL-Sensitive, No exception


INPUT/OUTPUT• I/O Permission Bit Map

– Exceptions for references to specific I/O addresses

– The limit of the TSS - the limit on the size of the I/O permission bit map


INPUT/OUTPUT– If CPL IOPL in the protected mode, the

processor allows I/O operations to proceed.

– If CPL > IOPL, or if the processor is operating in the Virtual 86 mode, the processor checks the I/O permission bit map.

– If any of the corresponding I/O permission bits equals 0, the proceed. Otherwise, GP(0) occurs

I/O Permission Bitmap

• There is potentially one bit for every I/O port-address (thus, up to 65536 bits!)

• Our ‘guest’ only needs to use UART ports

To encompass all the i/o ports, the bitmap needs 8K bytes!

065535

0x03FF

0x03F8

00000000

Legend: ‘0’ means I/O is allowed, ‘1’ means I/O is trapped


I/O Permission Bitmap


I/O Permission Bitmap Location in TSS

REFERENCES

Books:-1.The Intel Microprocessors

Eighth Edition by Barry B. Bray2.Advance Processors

By Harish G . Narula & U .S . ShahWeb Resources:-

1.Google2.Wikipedia

ANY QUERIES???