advance datasheet revision: may 2016

Preliminary Information: The data contained in this document describes new products in the sampling or preproduction phase of development and is for information only.

Northrop Grumman reserves the right to change without notice the characteristic data and other specifications as they apply to this product. The product represented by

this datasheet is subject to U.S. Export Law as contained in ITAR or the EAR regulations.

Advance Datasheet Revision: May 2016

APN243 24-28 GHz GaN Power Amplifier

Web: http://www.as.northropgrumman.com/mps ©2016 Northrop Grumman Systems Corporation

Phone: (310) 814-5000 • Fax: (310) 812-7011 • E-mail: [email protected]

Product Features

RF frequency: 24 to 28 GHz

Linear Gain: 20 dB typ.

Psat: 40.5 dBm typ.

Die Size: 14.44 sq. mm.

0.2um GaN HEMT Process

4 mil SiC substrate

DC Power: 28 VDC @ 1.0 A

Product Description The APN243 monolithic GaN HEMT amplifier

is a broadband, two-stage power device,

designed for use in Ka-Band communication

applications such as point-to-point and

point-to-multipoint digital (LMDS) radios and

SatCom Terminals. To ensure rugged and

reliable operation, HEMT devices are fully

passivated. Both bond pad and backside

metallization are Au-based that is compatible

with epoxy and eutectic die attach methods.

Applications

Point-to-Point Digital Radios

Point-to-Multipoint Digital Radios

Space-Earth Communications

Space Research & Earth Exploration

Performance Characteristics (Ta = 25°C)

Absolute Maximum Ratings (Ta = 25°C)

X = 3.8mm Y = 3.8mm

Specification * Min Typ Max Unit Frequency 24 28 GHz

Linear Gain 18 20 dB

Input Return Loss 18 20 dB

Output Return Loss 15 20 dB

P1db (PP*) 38 dBm

Psat (PP*) 39.5 40.5 dBm

PAE @ Psat (PP*) 27 %

Max PAE (PP*) 29.5 %

Vd1=Vg1a, Vd2=Vd2a 28 V

Vg1. Vg1a -3.5 V

Vg2, Vg2a -3.5 V

Id1+Id1a 200 mA

Id2+Id2a 800 mA

Parameter Min Max Unit

Vd1=Vg1a ,Vd2=Vd2a 20 28 V

Id1+Id1a 240 mA

Id2+Id2a 960 mA

Vg1, Vg1a, Vg2, Vg2a -5 0 V

Input drive level TBD dBm

Assy. Temperature 300 deg. C

(TBD seconds)

* Pulsed-Power On-Wafer unless otherwise noted

Approved for Public Release: Northrop Grumman Case 16-1026, 05/16








-40

-35

-30

-25

-20

-15

-10

-5

0

20 21 22 23 24 25 26 27 28 29 30 31 32

Ou

tpu

t R

etu

rn L

oss (

dB

)

Frequency (GHz)

-35

-30

-25

-20

-15

-10

-5

0

20 21 22 23 24 25 26 27 28 29 30 31 32

Inp

ut

Retu

rn L

oss (

dB

)

Frequency (GHz)

0

5

10

15

20

25

30

35

40

45

23 24 25 26 27 28 29 30

Po

ut

(dB

m),

Gain

(d

B),

PA

E%

Frequency (GHz)

Linear Gain (dB) Gain @ Pin=-10 dBm

PGain@Pin=27dBm (dB) P1dB (dBm)

Psat (dBm) PAE% @ PSat

Max PAE%0

2

4

6

8

10

12

14

16

18

20

22

24

26

20 21 22 23 24 25 26 27 28 29 30 31 32

Gain

(d

B)

Frequency (GHz)

Linear Gain vs. Frequency *

Measured Performance Characteristics (Typical Performance at 25°C)

Vd = 28.0 V, Id1 + Id1a = 200 mA, Id2 + Id2a = 800 mA

Power, Gain, PAE% vs. Frequency *

Output Return Loss vs. Frequency *

* Pulsed-Power On-Wafer

Input Return Loss vs. Frequency *









0

5

10

15

20

25

30

-10 0 10 20 30

PA

E%

Input Power (dBm)

PAE%@23GHz

PAE%@24GHz

PAE%@25GHz

PAE%@26GHz

PAE%@27GHz

PAE%@28GHz

PAE%@29GHz

PAE%@30GHz

0

5

10

15

20

25

30

35

40

45

23 24 25 26 27 28 29 30

Po

ut

(dB

m),

Gain

(d

B),

PA

E%

Frequency (GHz)

Linear Gain (dB) Gain @ Pin=-10 dBm

PGain@Pin=27dBm (dB) P1dB (dBm)

Psat (dBm) PAE% @ PSat

Max PAE%

Power, Gain, PAE% vs. Frequency

Pulsed-Power On-Wafer

Output Power, Gain vs. Input Power


PAE% vs. Input Power


Stage Currents vs. Input Power


Measured Performance Characteristics (Typical Performance at 25°C)

Vd = 28.0 V, Id1 + Id1a = 200 mA, Id2 + Id2a = 800 mA

02468101214161820222426283032343638404244

0123456789

10111213141516171819202122

-10 -5 0 5 10 15 20 25

Po

ut

(dB

m)

Gain

(d

B)

Input Power (dBm)

Gain@24GHz Gain@25GHz



Gain@30GHz PAE%@30GHz

Pout@23GHz Pout@24GHz




Pout

Gain

0

100

200

300

400

500

600

700

800

900

1000

1100

1200

1300

1400

-10 -5 0 5 10 15 20 25 30

Id (

A)

Pin (dBm)

Id1@23GHz Id1@24GHzId1@25GHz Id1@26GHzId1@27GHz Id1@28GHzId1@29GHz Id1@30GHzId2@23GHz Id2@24GHzId2@25GHz Id2@26GHzId2@27GHz Id2@28GHzId2@29GHz Id2@30GHz









Biasing/De-Biasing Details:

Bias for 1st stage is from top. The 2nd stages must bias up from both sides.

Listed below are some guidelines for GaN device testing and wire bonding: a. Limit positive gate bias (G-S or G-D) to < 1V

b. Know your devices’ breakdown voltages

c. Use a power supply with both voltage and current limit.

d. With the power supply off and the voltage and current levels at minimum, attach the ground lead to

your test fixture.

i. Apply negative gate voltage (-5 V) to ensure that all devices are off

ii. Ramp up drain bias to ~10 V

iii. Gradually increase gate bias voltage while monitoring drain current until 20% of the operating

current is achieved

iv. Ramp up drain to operating bias

v. Gradually increase gate bias voltage while monitoring drain current until the operating current

is achieved

e. To safely de-bias GaN devices, start by debiasing output amplifier stages first (if applicable):

i. Gradually decrease drain bias to 0 V.

ii. Gradually decrease gate bias to 0 V.

iii. Turn off supply voltages

f. Repeat de-bias procedure for each amplifier stage

Die Size and Bond Pad Locations (Not to Scale)

3800 µm

1122 µm 2678 µm

3800 µm

2077 µm

1477 µm

677 µm

X = 3800 µm 25 µm

Y = 3800 25 µm

DC Bond Pad = 100 x 100 0.5 µm

RF Bond Pad = 100 x 100 0.5 µm

Chip Thickness = 101 5 µm

RFIN GND

GND

RFOUT GND

GND

VG

2A

VD

2A

GN

D

GN

D

GN

D

GN

D

VD

1A

VG

1A

VG

2

VD

2

GN

D

GN

D

GN

D

GN

D

VD

1

VG

1

1077 µm

2077 µm

1477 µm

677 µm 1077 µm









RFIN GND

GND

RFOUT GND

GND

VG

2A

VD

2A

GN

D

GN

D

GN

D

GN

D

VD

1A

VG

1A

VG

2

VD

2

GN

D

GN

D

GN

D

GN

D

VD

1

VG

1

Recommended Assembly Notes

1. Bypass caps should be 100 pF (approximately) ceramic (single-layer) placed no farther than 30 mils from the amplifier.

2. Best performance obtained from use of <10 mil (long) by 3 by 0.5 mil ribbons on input and output.

3. Part must be biased from both sides as indicated.

4. The 0.1uF, 50V capacitors are not needed if the drain supply line is clean. If Drain Pulsing of the device is to be used, do NOT use the 0.1uF , 50V Capacitors.

Mounting Processes

Most NGAS GaN IC chips have a gold backing and can be mounted successfully using either a conductive epoxy or

AuSn attachment. NGAS recommends the use of AuSn for high power devices to provide a good thermal path and a

good RF path to ground. Maximum recommended temp during die attach is 320oC for 30 seconds.

Note: Many of the NGAS parts do incorporate airbridges, so caution should be used when determining the pick up

tool.

CAUTION: THE IMPROPER USE OF AuSn ATTACHMENT CAN CATASTROPHICALLY DAMAGE GaN CHIPS.

Suggested Bonding Arrangement

RF Output

Substrate

RF Input

Substrate

= 100 pF, 15V (Shunt)

= 10 Ohms, 30V (Series)

= 0.01uF, 15V (Shunt)

VG2 VD2

VG1

VD1

VG1A

VD1A

PLEASE ALSO REFER TO OUR “GaN Chip Handling Application Note” BEFORE HANDLING,

ASSEMBLING OR BIASING THESE MMICS!

= 0.1uF, 15V (Shunt)

= 100 pF, 50V (Shunt)

= 0.01uF, 50V (Shunt)

= 0.1uF, 50V (Shunt) [4] [4]

[4]

[4] VG2A

VD2A

[4]


advance datasheet revision: may 2016

Documents