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UNIT-1

1. Difference between asynchronous and synchronous circuits.

Asynchronous circuits Synchronous circuits

Transition happens at any instant

of time.

Transition happens at discrete

instant of time.

Do not use clock pulses. Changes

of internal state occur when there

is a change in input variables.

The circuit response only to

the pulse on particular inputs.

Storage elements are affected

only with the arrival of each

pulse.

Storage elements work as time

Delay devices.

More difficult to design. Easier to design.

2. Define clocked synchronous sequential networks.

In clocked synchronous sequential networks, the network behavior is

defined at specific instant of time associated with special timing signals. Here the

flip-flops receive the common clock signal simultaneously. Such sequential

networks are referred to as clocked synchronous sequential networks.

3. Draw the block diagram of mealy model of a CSSN.

4. Write the next state and output equation for mealy model of a CSSN.

If x denotes the input signal and Q is the collective present states of the flip-flops, then the next state of the network denoted by Q+ is given by,

Q+ = f(x,Q)

The output z is the function of both an input and present state. It is given byZ = g(x,Q)

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5. Draw the block diagram of Moore model of a CSSN.

6. Write the next state and output equation for Moore model of a CSSN.

If x denotes the input signal and Q the collective present states of the flip-

flops, then the next state of the network denoted by Q+ is given by,

Q+ = f(x,Q)

The output z are only the function of present state and not of the external

input is given by,

Z = g (Q)

7. Compare and contrast the features of Moore and mealy state machine.

Mealy machine Moore machine

Its output is a function of present

state as well as external inputs.

Its output is a function of present

state only.

It requires less number of states for

implementing same function.

It requires more number of states

for implementing same function.

It is different to design a mealy

machine because of network

specification that it also a function

of current external inputs.

It is easy to design a Moore

machine.

False identification is simple.

False identification is littledifficult.

8. What are the steps involved in analyzing a CSSN?

Logic diagram

Logic equation

Excitation table

Transition table

State table

State diagram

Network terminal behaviour

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9. Draw the state diagram for a mealy serial binary adder.

10. Draw the state diagram for a Moore serial binary adder.

11. Define excitation and output expressions.

It is the algebraic expressions served as mathematical representation of the

networks. To do this, it is necessary to assign present state variables to each of the

output terminals of the flip-flops. Then it is necessary to assign excitation variables

to the inputs of the flip-flops.

12. What is the use of transition table in analyzing a CSSN?

Transition table is to express information in tabular form. The transition

table is the tabular representation of the transition and an output equation. It

consists of three sections namely,

Present state variables.

Next state variables.

Output variables.

13. What is the need of state table and state diagram in analyzing a sequential

circuit?

An alphanumeric symbol can be assigned to represent the states. When this

relabeling is done to the transition table, the resulting table is called the state table.

To represent the state table in graphical form, state diagram can be established.

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14. Write down the steps involved in state table reduction.

The state table reduction procedure is a three step process.

Equivalent pairs of states are determined.

From the knowledge of the equivalent pairs of states, sets of

equivalent states are established.

The reduced state table is constructed having one state for each of

the sets of equivalent states.

15. What are the guidelines used for obtaining state assignment?

States with the same next state for a given input transition should

be given adjacent assignments in the state map.

Next state of the same state should be given adjacent assignments

in the state map. States with the same output for a given input should be given

adjacent assignments in the state map.

16. What is meant by ASM Chart?

Flowchart specifies a sequence of procedural steps and decision steps for a

state machine. Translates word description into a series of operations with

conditions for execution. It allows for detailed description of control and data

path.

17. What are the elements of ASM Chart?

State box

Decision box

Conditional box

18. Define state box of the ASM Chart.

State box indicates an FSM state Box also indicates operation to be

performed. Binary code and state name also included.

19. Define the decision box of ASM Chart.

It describes the impact of an input on control system. It contains two exit

paths which indicate result of condition. More complicated conditions are possible

which can implement in hardware with a magnitude comparator

20. Define the conditional box of ASM Chart.

It indicates assignments following a decision box. It also indicates data

transfer

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21. Define the binary multiplier.

The multiplication of two binary numbers is done by successive additions

and shifting.

Example:

10111multiplicand

10011multiplier

--------------

10111

10111

00000

00000

10111

------------------

110110101product

22. List out the applications of iterative circuits.

Iterative design is commonly used in the development of human

computer interfaces.

It enables and encourages user feedback, so as to elicit the system's

real requirements.

Continuous, iterative testing enables an objective assessment of the

project's status.

23. State two reasons. Why a state table might be incompletely specified?

When the flow table is incompletely specified, the procedures for

obtaining the minimum state sequential circuit are lengthy.

They require an extensive enumeration that they are impractical for

computer implementation.

24. Define Array Multiplier.

Array multiplier is a fast multiplier that can be designed using an array

structure.

Consider a 4x4 example, where the multiplicand and the multiplier

are M=m3m2m1m0 and Q= q3q2q1q0 respectively.

The partial product 0, PP0=pp03 pp02 pp01 pp00, can be generated

using the and q0 with each bit of M.

Thus, PP0=m3q0 m2q0 m1q0 m0q0.

Partial product 1, PP1 is generated using the AND gate q1 with Mand adding to PP0 as follows,

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PP0: 0 pp03 pp02 pp01 pp00

+ m3q1 m2q1 m1q1 m0q0 0

-----------------------------------------

PP1: pp14 pp13 pp12 pp11 pp1

Similarly, the partial product 2, PP2 is generated using the AND of

q1with M and adding to PP1, and so on.

25. Give the practical applications of state table and state diagram.

State Table:

The time sequence of inputs, outputs, and flip-flop states can be enumerated ina state table. This can be generated from the logic diagram or the state equations.

State Diagram:

The information available in a state table can be represented graphically in

a form of a state diagram. In this diagram, a state is represented by a circle, and

the transitions between states by directed lines connecting the circles.

26. What is meant by carry look ahead adder?

A carry-look ahead adder (CLA) is a type of adder used in digital logic. A

carry-look ahead adder improves speed by reducing the amount of time required

to determine carry bits. It can be contrasted with the simpler, but usually slower,

ripple carry adder for which the carry bit is calculated.

We can write the Boolean expression for the carry-out in an

alternate way:

Ci+1 = xiyi + xici + yici

We use the distributive property to rewrite the carry out as:

Ci+1 = xiyi + ci (xi + yi)

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UNIT-2

1.Draw a block diagram of an asynchronous sequential circuit?

n input variables

m output variables

k internal states

2. Write down the Analysis Procedure for asynchronous circuit.

Steps:

1. Determine all feedback loops.

2. Assign Yi's (excitation variables), yi's (secondary variables)

3. Derive the Boolean functions of all Yi's

4. Plot each Y function in a map, y variables for the rows

The external variable for the columns

5. Combine all the maps into one transition table

showing the value of Y=Y1Y2Yk inside each square

6. Circle the stable states and derive the state table

Those values of Y that are equal to y=y1y2yk in the same row

Total state of the circuit: combine internal state with input value

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3. Define the term race.

It occurs when two or more binary state variables change value in response

to a change in an input variable. When unequal delays are encountered, a race

condition may cause the state variables to change in an unpredictable manner.

4. What are the different types of race?

1. Non-Critical Race

They reach the same final state.

2. Critical Race

End up in two or more different stable states.

5. Define debounce circuit.

Remove the series of pulses that result from a contact bounce and produce a

single smooth transition of the binary signal.

6. Define Cycle

When a circuit goes through a unique sequence of unstable states.

7. What is the Procedure for finding a suitable group of compatibles for merging

a flow table?

1. Determine all compatible pairs by using the implication table.

2. Find the maximal compatibles using a merger diagram.

3. Find a minimal collection of compatibles that cover all the states

8. Define State reduction and State assignment

State reduction:

Reduce flow table by merging rows in primitive flow table. Reduce equivalent states and compatible states

State assignment:

Assign binary state variables to each row of the reduced flow table

to obtain the transition table. Eliminates any possible critical races

9. Define primitive flow table

Asynchronous sequential network that are operate fundamental mode, it is

most convenient to start flow with special from of flow table. This special form is

called primitive flow table.

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10. Define hazard.

A hazard is the potential or actual malfunction of a logic network during the

transition between two input states as the result of a single variable change, where amalfunction is any deviation from intended response.

11. Define static hazard.

A static hazard in a logic network is a transient change of an output value

that is supposed to remain fixed during the transition between two input statesdiffering in the value of one variable.

12. What are the different types of static hazard?

It is classified into two types.

1. Static-02.

Static-1

Static-0

When the input is to remain at the value 0 and a momentary 1 is output

possible during the transition between the two input states.

Static-1

When the input is to remain at the value 1 and a momentary 0 is output

possible during the transition between the two input states

13. Define Essential Hazards:Occur due to unequal delays along two or more paths that originate from the

same input. Another type of hazard may occur in asynchronous sequential circuits.

It cannot be corrected by adding redundant gates.

14. Define Race-free

Avoiding critical races

Only one variable changes at any given time may allow

noncritical race

15. Define Transition diagram

Pictorial representation of all required transitions between rows

Try to find only one binary variable changes during each statetransition

If critical races exist, add extra rows to obtain race-free assignment

16. What are the Methods for race-free state assignment?

Shared-row method

Multiple-row method

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UNIT-3

1. Define fault

A fault of a circuit is the physical defect of one or more components are

connection of the circuit.

2. Define the term fault detection and location.

The task of determine whether fault present or not in the circuit is called

fault detection.

The task of the isolating fault is called fault location.

3. What is meant by fault diagnosis?

The combined task of fault detection and fault location is referred to as

fault diagnosis. The technique adopted to diagnose faults is testing.

4. Define Stuck-at fault.

A stuck-at fault is said to have occurred if a signal line appear to have its

value fixed either a logic 1 or 0, irrespective of input signal applied to the circuit.

Stuck-at 0 fault:

When the signal line is logic 0, the fault is called stuck-at 0 fault, it is

denoted SA0.Stuck-at 1 fault:

When the signal line is logic 0, the fault is called stuck-at 0 fault, it is

denoted SA0.

5. Define Test Vectors.

An input combination in which the presence of a fault produces an output

different from the fault-free output is known as a test vector (TV).

6. Define Test generation

Test generation is the process of finding the set of test vectors that can detect

(or detect and locate) the faults in a circuit.

7. Define Test set

The set of test vectors used for testing the circuit is called test set. The test

set is classified,

1. Fault detection test set

2. Fault diagnosis test set

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8. Define Growth (G) Fault.A missing cross point in the AND array at the intersection of product line p i

and an input line xj or xj is denoted G(i, j). As the result of this, missing cross point

variable xjgets eliminated from the product term p i.

9. Define Shrinkage (S) faults.

An extra cross point fault in the AND array at the intersection of p iand an

input line xj(xj) is denoted S (i, j)[or S (i,-j)]. As a result of this extra cross pointthe variable xjor xj gets AND with the product term pi.

10. Define Appearance (A) faults.

An extra cross point fault at the intersection of product term pi and outputline zk is denoted by A (i, k). Such a fault is called an appearance fault since

product term pi now newly appearance on output function zkas seen on a map.

11. Define Disappearance (D) faults.

A missing cross point at the intersection of pi and zk is denoted by D (i,k).This fault is called a disappearance fault.

12. State the Fault Tolerance techniques.

Fault tolerance can be defined as the ability of the circuit to function

correctly despite the presence of faults.

13. State the Compact Algorithm.

Compact algorithm derives a Folded Compactable Matrix (FCM) that gives

all the information required to fold a given PLA.

14. What are the major goals for testability of design?

The major goals of testable designs are the following:

Tests should remain valid in the presence of undetectable faults.

Compact test sets should also be computationally simple to derive.

The design procedure to achieve testability must not add undue

complexity to the logic design process.

The extra hardware needed to enhance testability must be low.

The speed of operation must not deteriorate.

It must be possible to apply the tests and evaluate the response

using simple hardware, so as to provide built-in self-test (BIST)

capability, if possible.

The test set derived must have very high coverage of all multiple

faults. The techniques that are evolved to meet these goals are

classified as design for testability (DFT) techniques.

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15. Define Bridging fault.

The bridging fault is said to have occurred if two signal lines are shorted

together. It may be either an AND or an OR types of bridging fault.

16. What are the types of fault?

Faults can be either permanent or temporary. Permanent fault are

typically caused by the breaking or wearing out of a component.

Permanent faults are also called hard and solid faults.

Temporary faults can occur certain interval or period of time. This

is also known as soft faults. These faults can be either transient or

intermittent. The fault can be classified into logical or parametric

depending on its effect.

17. What is meant by logical and parametric fault?

A logical fault changes the Boolean function realized by the digital circuit,

while a parametric fault alters the magnitude of a circuit parameter, causing a

change in a factor, such as circuit speed, current or voltage. An important type of

parametric fault is the delay fault which is caused by slow gates. This type of fault

usually leads to problems of hazards or critical races.

18. What are the classifications of logical fault?

Logical fault can be classified into stuck at fault(stuck at 0 and stuck at 1),

bridging fault (shortage wires), cross point fault (growth (G)fault , shrinkage

(S)fault, appearance (A)fault and disappearance (D)fault ).

19. What is meant by cross point fault?

Faults that occur in programmable logic arrays (PLA) due to extra or

missing devices such as diode or transistor are called cross point fault.

20.What is meant by Boolean difference method?

The Boolean difference method is an algebraic technique for test generation

in which the test vectors are generated by utilizing the properties of Boolean

algebra.

Consider a logic circuit which realize under fault free conditions. The n

Number of input variables namely,

X1, x2, xn.The Boolean expression is,

F(x)=F(x1,x2,..xn).

The logic circuit realize under faulty condition. The Boolean function is,F(x) =F(x1, x1, .xn)

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21. What are the steps involved in testing process?

Circuit description

22. What is meant by Kohavi algorithm?

It is used to detect multiple faults in two level networks. The technique,

which consists of determining two sets of tests, the test and b test, considers thealtered Boolean function realized by the circuit due to the presence of the single

fault. Kohavi proved that this single fault test set detect all multiple faults.

23. What are the conditions of Kohavi algorithm?

The network must be two level AND-OR or (OR-AND) network.

AND gate must realize a prime cube.

AND-OR network must implement a Boolean function which is a

sum of irredundant prime implicants.

24. What is the test and b test?

A test: The set of distinguished min terms that tests each AND gate for

SA0 fault iscalled the set of a test.

B test: The set of min terms that test each AND gate for SA1 fault is called

the set of b test.

25. What are the types of fault tolerance techniques?

Static redundancy technique

Dynamic redundancy technique

Fault modeling

Test generation

Fault coverage evaluation

Test application

Fault simulation

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26. What are the applications of fault tolerance technique?

Computer controlled aircraft,

Spacecraft,

Medical electronics,

Traffic control.

27. State about the masking cycles

It states two theorems.

Theorem 1:

A fault from the set GUA on a product term Pi in a PLA can be masked

only be a fault from the set SUD existing on the same product term Pi.

Theorem 2:

A fault from the set SUD on a product term Pi in a PLA can be masked

only be a fault from the set GUA existing on the same product term Pi.

28. What are the drawbacks while testing sequential circuit?

MUX can directly connected to the external bit

If there are many state variables we have many pins.

We can shift the test vector one bit at a time

29. What are the conditions of scan path techniques?

FF can be scanned by the pattern of 0s and 1s.

We can get the same pattern when 01011001 were scanned out.

Y1 Y2 Y3 that is scanned by normal/scan=1.

W1 W2 Wn that is scanned by normal/scan=0.

30. What are the drawbacks of scan path technique?

It works in synchronous present and reset. In asynchronous it does

not suit.

It is level sensitive scan

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UNIT-4

1. Define reliability of the system.

Reliability of a system is defined to be probability that the given system willperform it required function under specified period of time.

Reliability of a system is a real number between 0 and 1.

R (t) = limN->WN(t)/N

2. Define failure rates.

The failure rate is the number of failures that occur per unit time in a

component or system.

It is usually denoted by the Greek letter .

3. What is meant by FIT?

The failure rates for typical electric components are so small there are several

scaled units for expressing them: percent failures per 103

hours, failures per 106

hours and failures per 109hours. The last unit is called a FIT.

1 FIT = 1 failure/ (109hours)

4. What is meant by infant mortality?

The failure rate of a typical electronic component is a function of time. The

typical component has a high failure rate during its early life, during which most

manufacturing defects make themselves visible; failure during this period are called

infant mortality.

5. What are the factors affecting the failure rate?

The factors that can affect component failure rates, including

Temperature, Humidity, Shock, Vibration, Power cycling

6. Define MTBFAnother measure of the reliability of a component or system is the mean

time between failures (MTBF).The average time that it takes for a component to fail. For components

with a constant failure rate , it can be shown that MTBF is simply the reciprocal of

.

MTBF = 1/

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7. What is meant by system reliability?

System reliability is also an exponential function, using a composite

failure rate systhat is the sum of the individual component failure rate.

The system reliability is given by the formula,

Rsys(t) = R1(t).R2(t).Rm(t)

=e-sys

(t)

sys=1+ 2+ .+ m

8. Define characteristic impedance (Z0)

The ratio of voltage to current Vout/ Iout depends on the physical

characteristics of the conductor and is called charecteristicsimpedence( Z0) of a

conductor pair.

9. Define Reflection co-efficient ().

The amplitude of the wave reflected at the end of a transmission line is

determined by the reflection co-efficient (rho).

The value of depends on Z0and Term, the transmission at the end of the

line:

= Z0 Term/ Z0+ Term

10. Define principle of superposition.

The voltage at any point on the line and instant in time is the sum of that

points initial condition and all the waves have passed it which is called as super

position principle.

11. What are the three conditions for transmission lines?

Term= Z0When a transmission line is terminated in its characteristics impedance, the

reflection coefficient is 0.

Term= 0

The reflection coefficient of a short-circuited line is -1, producing a

reflection coefficient of equal magnitude and opposite polarity.

Term=

The reflection coefficient of an open-circuited line is +1, producing a

reflection coefficient of equal magnitude and same polarity.

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12. What is meant by undershoot?

When the wave hits the receiving end at time T, it produces a reflection of

equal sign and magnitude (since = 1). Thus, the voltage at the receiving end is

now a negative voltage. This is called undershoot.

13. What is meant by ringing?

When the reflections continue, the voltage at both the sending and

receiving ends asymptotically approaching 0v, the value one would predict with a

DC analysis of the circuit. This oscillating pattern is called ringing.

14. What are the advantages of clamp diodes?These diodes change the receivers input impedance from very high to

very low for negative voltages, they limit the negative excursion at time T to about

1V. This reduces the reflection back to the sending end, which in turn reduces

the excursion time 3T to less than 1V.

The inputs of some devices also have diodes connected to VCCto handle

the overshoot that occurs when low-impedance drivers make a LOW-to-HIGHtransition.

15. What are the uses of source termination?The wellmatched The venin termination at the end of a transmission

line, little or no reflection will occur. The downside of this termination is that it

consumes DC power at all times and relatively high driver currents are required.

A source termination overcomes these problems. In the source

termination, a resistance equal to Z0minus Rd, the typical output impedence of the

driver, is placed in series with the output, physically close to the output itself.

16. Write down the steps involved in synthesis for design process?

Architectural synthesis

Logical synthesis

Physical design

17. Explain a process of architectural synthesis?

It starts from the behavioral design description and generates an

architecture for the design at the register transfer level, consisting of a data path and

a control unit. The data path is an inter-connection of basic modules such as adders,

multipliers and register files. The control unit specifies the signals that have to be

issued to control the data path. Important steps performed by architectural synthesis

are scheduling and binding, which respectively determine the execution time of the

operations in the behavioral description and the modules which will execute theseoperations.

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18. Define reflection co-efficient termination impedance.

The amplitude of the wave reflected at the end of a transmission line is

determined by the reflection coefficient, (rho). The value

of depends onZ0and Term, the termination impedance at the end of the line

19. Draw path tub curve.

20. How to eliminate reflection co-efficient?

Reflection can be eliminating by terminating transmission lines in their

characteristics impedance.

21. Write the factors of choosing the thevenin resistance.

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22. Define data path in IC.

The data path is an interconnection of basic modules such as adders,

multipliers and register files.

23. Define control unit in IC.

The control unit specifies the signal that has to be issued to control the data

path.

24. Define important steps for architectural synthesis.

Important steps performed by architectural synthesis are scheduling and

binding, which respectively determine the execution time of the operations in

thbehavioral description and the modules which will execute these operations.

25. Write the function of logical synthesis.

Logical synthesis take a register transfer level description & converts it to a

network of logic primitives.

The set of primitives strongly depends on the design style.

26. Design style uses and example.

It is used in set of primitives and it example are

1) Custom design.

2) Cell based design.

3) Array based design.

27. Write the classification of logic synthesis technique.

Sequential synthesis technique.

Combinational synthesis technique.

28. Write the function of physical design.

Physical design performs the final steps in the design process to generate the

geometric patterns defining the physical layout of chip. These steps include floor

planning, placement and routing.

29. Define verification.

Error should be found as early as possible in the design process to avoid the

necessity of performing extra design iteration just to fix these errors. Therefore it is

important to check during the design process that no errors are made. This task is

called verification.

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30. What are the types of verification problems?

The first on is related to question this is called designing verification or

validation.

The second one is concerns the question this is called implementation

verification.

31. Define implementation verification.

Implementation verification related to the correctness of the design step.

It typically involves the comparison of 2 circuit models to check that there

are no inconsistencies.

32. Write the formal verification methods categories.

It providing three categories of theorem that is

Model checking.

Language containment.

Equivalence checking.

UNIT-5

1. What is read-only memory (ROM)?

A read only memory (ROM) is a combinational Circuit with n inputs & b

outputs. The inputs are called address inputs are traditionally named a0, a1an-

1.the outputs are called data outputs are typically named d0, d1, .db-1.

2. What is word line?

The address input select one of the decoder outputs to be asserted. Eachdecoder o/p is called word line because it selects one row or word of the table

stored in the ROM.

3. What is bit line?

Each vertical line is called a bit line because it corresponds to one output bit

of the ROM. An asserted word line pulls a bit line low if a diode is connected

between the word line and the bit line.

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4. What is mask charge?

It has one or more customized masks to manufacture ROMs with the

required pattern. Rom manufactures impose mask charge of several thousand

dollars for the customized aspects of mask-ROM production.

5. What is the Output Enable?

Most commercial ROM chips have three-state data output is called the

Output Enable (OE) input. Most ROMs have a Chip Select (CE) input to simplify

the design of such systems.

6. What is the power-down input?

A CS input is no more than a second output enable that is AND with OE to

enable the three-state output, in many ROMs, CS also serves as a power-down

input.

7. What is the active mode?

In this standby mode of operation, a typical ROM consumes less than 10%

of the power it uses in active mode with CS asserted (RAM control input & timing)

8. What is the access time from chip select (tacs)?

It is the propagation delay from the time CS is asserted until the data outputsare valid. In some chip, this is longer than the access time from address, because

the chip takes a little while to power up.

9. What is the o/p-enable time (toe)?

It is the propagation delay from OE&CS both asserted until the three-state

o/p drivers have left the hi-z state. The o/p data may or may not be valid at that

point.

10. What is the o/p-disable time (toz)?

It is the delay from the time oe or cs are negated until the three-state o/p

drivers have entered the Hi-z state.

11. What is the o/p-hold time (toh)?

It is the length of time that the output remains valid after a change in the

address input or after OE-l or CS-l is negated.

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12. What is the digital attenuator?

A digital attenuator must produce a different PCM byte that represents the

original analog signal multiplied by a specified attenuation factor.

13. Write the advantages of ROM based circuits?

Faster than FPGA

Easily to handles

Easily modified

Problems can be solved with a single chip.

14. Write the disadvantages of ROM based circuits?

More cost

More power

Run slower

More than 25inputs

Required billions & billions of bits.

18. What is SRAM?Once a word is written at a location, it remains stored as long as power is

applied to the chip, unless the same location is written again is called the static

RAM.

19. What is the dynamic Ram?

The data stored at each location must be refreshed periodically by reading it

& then writing it back again, or else it disappears.

20. What is the volatile memory &non-volatile memory?Most RAMs lose their m/y when power is removed is called the volatile

memory.

Some RAMs retain their m/y even when power is removed is called the non-

volatile memory.

21. What is the Write-Enable (WE) input?

The control inputs are comparable to those of a ROM with the additional is

called the WE input.

22. Explain the 2 define access operations &also explain for static Ram?

2 Types:

1. Read

2. Write

8/10/2019 Adsd 2 Marks Q&A 2014-15

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1. Read:

An address is placed on the address inputs while CS&OE are asserted. The

latch outputs for the selected memory location are delivered to DOUT.

2.

Write:

An address is placed on the address inputs data word is placed on DIN then

CS & WE is asserted. The latch in the selected m/y location open and the input

word is stored.(Static-Ram timing)

23. What is the output-hold time (toh)?

It is the parameter specifies how long the output data remains valid after a

change in the address inputs. (Timing parameter)

24. What is the address setup time before write (tas)?

All of the address inputs must be stable at this time before both CS&OE are

asserted. Otherwise, the data stored at unpredictable locations may be corrupted.

25. What is the chip select setup before end of write (tcsw)?

Cs must be asserted at least long before the end of the write a cycle in order

to select a cell.

Prepared by,

2014 Batch ME Students

KNCET

TRICHY

Any correction please inform us through mail: 9rubies14@googlegroups.com