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![Page 1: ADS DDR4 Test Benches with Waverform Bridge to Instrument ... · ADS DDR4 Test Benches with Waverform Bridge to Instrument Certified DDR Test Compliance Author: Keysight EEsof EDA](https://reader034.vdocuments.us/reader034/viewer/2022050608/5fafc0fd7ff5b64cb367d276/html5/thumbnails/1.jpg)
ADS DDR Test Benches with Waveform Bridge to Instrument Certified DDR Test Compliance
Jian Yang R&D Engineer Nilesh Kamdar Applications Engineer
Sept 16, 2014
New Keysight EEsof EDA Simulation Tools for
Signal Integrity, Power Integrity, and EMI/EMC
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– Introduction to DDR4
– “DDR4 Simulation -> Compliance Test” Flow
– DDR4 Compliance Test Bench Demo
– Summary
Keysight EEsof EDA Simulation
Tools for Signal Integrity, Pow er
Integrity, and EMI/EMC
2
Agenda
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Page Keysight EEsof EDA Simulation
Tools for Signal Integrity, Pow er
Integrity, and EMI/EMC
3
Introduction: DDR4 memory ramping up in electronic systems
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Page Keysight EEsof EDA Simulation
Tools for Signal Integrity, Pow er
Integrity, and EMI/EMC
4
DDR4 Memory in the News
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DDR4 High Speed => Less Timing Margin
Keysight EEsof EDA Simulation
Tools for Signal Integrity, Pow er
Integrity, and EMI/EMC
5
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Shrinking Eye due to Package, PCB and Connectors
Keysight EEsof EDA Simulation
Tools for Signal Integrity, Pow er
Integrity, and EMI/EMC
6
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ADS 2014 “DDR4 Simulation=>Compliance Test” User Story
Keysight EEsof EDA Simulation
Tools for Signal Integrity, Pow er
Integrity, and EMI/EMC
7
Copyright 2014 Agilent Technologies,
Inc. 7
1. As a DDR controller designer at an IC company, I need to swap out the
simulated testbench’s generic controller model with my controller I/O
model…
2. As a PCB/package/DIMM designer at an OEM or IC company, I need to
swap out parts of the simulated testbench’s generic channel cascade with
the post-layout EM-based model of my package (or PCB or DIMM)…
3. As a DRAM I/O designer at an IC company, I need to swap out the
simulated testbench’s generic DRAM model with my DRAM I/O model….
(for all three)…then I want to run a sign-off compliance test on the simulated
test bench waveforms before committing to fabrication. I want to run the exact
same tests on the simulated testbench that I will run on my ‘scope in the test
lab when get my prototypes back from fab.
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ADS 2014 “DDR4 Simulation=>Compliance Test” Flow
Keysight EEsof EDA Simulation
Tools for Signal Integrity, Pow er
Integrity, and EMI/EMC
8
Copyright 2014 Agilent Technologies,
Inc. 8
Simulated test bench in ADS
Real test bench Infiniium
oscilloscope
ADS “Waveform
Bridge”: Script that
writes file format
that ‘scope
compliance app
understands
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ADS DDR4 Simulation Setup
Keysight EEsof EDA Simulation
Tools for Signal Integrity, Pow er
Integrity, and EMI/EMC
9
Copyright 2014 Agilent Technologies,
Inc. 9
Simulation Setup for Data and Strobe Signals in WRITE Cycle
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Driver and Receiver IBIS models
Keysight EEsof EDA Simulation
Tools for Signal Integrity, Pow er
Integrity, and EMI/EMC
10
Copyright 2014 Agilent Technologies,
Inc. 10
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Channel Model
Keysight EEsof EDA Simulation
Tools for Signal Integrity, Pow er
Integrity, and EMI/EMC
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Copyright 2014 Agilent Technologies,
Inc. 11
– Use multilayer transmission
line models and S-
parameters to build the
channel model
– Can import a PCB layout to
build an EM model using
Momentum or FEM
– Can import S-parameters
from other EM tools or
VNA/TDR measurements
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Pattern Generator
Keysight EEsof EDA Simulation
Tools for Signal Integrity, Pow er
Integrity, and EMI/EMC
12
Copyright 2014 Agilent Technologies,
Inc. 12
– Use PRBS sources to
generate random DQ pattern
and repetitive DQS pattern
– Use pulse sources as input
to IBIS Enable Pin to
generate DQ and DQS
bursts
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ADS Transient Simulation Controller and Netlist Include
Keysight EEsof EDA Simulation
Tools for Signal Integrity, Pow er
Integrity, and EMI/EMC
13
Copyright 2014 Agilent Technologies,
Inc. 13
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Save ADS waveforms to .h5 files for analysis in Infiniium Offline
Keysight EEsof EDA Simulation
Tools for Signal Integrity, Pow er
Integrity, and EMI/EMC
14
Copyright 2014 Agilent Technologies,
Inc. 14
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DDR4 Compliance Test
Keysight EEsof EDA Simulation
Tools for Signal Integrity, Pow er
Integrity, and EMI/EMC
15
Copyright 2014 Agilent Technologies,
Inc. 15
– What are we testing?
• Clock Tests
• Electrical
• Timing
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DDR4 Electrical and Timing Tests
Keysight EEsof EDA Simulation
Tools for Signal Integrity, Pow er
Integrity, and EMI/EMC
16
Copyright 2014 Agilent Technologies,
Inc. 16
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Load ADS waveforms to perform DDR4 compliance tests
Keysight EEsof EDA Simulation
Tools for Signal Integrity, Pow er
Integrity, and EMI/EMC
17
Copyright 2014 Agilent Technologies,
Inc. 17
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Generate measurement results and HTML report
Keysight EEsof EDA Simulation
Tools for Signal Integrity, Pow er
Integrity, and EMI/EMC
18
Copyright 2014 Agilent Technologies,
Inc. 18
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DDR4 Compliance Test Bench demo
Keysight EEsof EDA Simulation
Tools for Signal Integrity, Pow er
Integrity, and EMI/EMC
19
Copyright 2014 Agilent Technologies,
Inc. 19
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Summary
Keysight EEsof EDA Simulation
Tools for Signal Integrity, Pow er
Integrity, and EMI/EMC
20
Copyright 2014 Agilent Technologies,
Inc. 20
• ADS simulates the physical channel effects of I/O drivers/receivers and
package/PCB/connectors between MCH and DDR4 memory
• Simulated waveforms are used to run DDR4 compliance test
• Compliance sign-off report is generated from the simulated waveforms before
committing to fabrication. Exact same tests can be run in the test lab when
hardware prototypes come back from fabrication
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Call to Action
Keysight EEsof EDA Simulation
Tools for Signal Integrity, Pow er
Integrity, and EMI/EMC
21
Copyright 2014 Agilent Technologies,
Inc. 21
Download “DDR4 Compliance Test Bench” software:
http://www.keysight.com/main/software.jspx?cc=US&lc=eng&ckey=2504328&id=2504328
Watch “DDR4 Compliance Test Bench” video :
http://www.keysight.com/en/pd-2423419-pn-W2351EP/ddr4-compliance-test-bench