adp3208d - 7-bit, programmable, dual-phase, mobile, cpu

© Semiconductor Components Industries, LLC, 2010

February, 2010 − Rev. 01 Publication Order Number:

ADP3208D/D

ADP3208D

7-Bit, Programmable,Dual-Phase, Mobile, CPU,Synchronous BuckController

The ADP3208D is a highly efficient, multiphase, synchronous buckswitching regulator controller. With its integrated drivers, theADP3208D is optimized for converting the notebook battery voltageinto the core supply voltage required by high performance Intelprocessors. An internal 7−bit DAC is used to read a VID code directlyfrom the processor and to set the CPU core voltage to a value withinthe range of 0.3 V to 1.5 V. The phase relationship of the output signalsensures interleaved 2−phase operation.

The ADP3208D uses a multi−mode architecture run at aprogrammable switching frequency and optimized for efficiencydepending on the output current requirement. The ADP3208Dswitches between single− and dual−phase operation to maximizeefficiency with all load conditions. The chip includes a programmableload line slope function to adjust the output voltage as a function of theload current so that the core voltage is always optimally positioned fora load transient. The ADP3208D also provides accurate and reliableshort−circuit protection, adjustable current limiting, and a delayedpower−good output. The IC supports On−The−Fly (OTF) outputvoltage changes requested by the CPU.

The ADP3208D is specified over the extended commercialtemperature range of −10°C to 100°C and is available in a 48−leadLFCSP.

Features

• Single−Chip Solution

• Fully Compatible with the Intel® IMVP−6+Specifications

• Integrated MOSFET Drivers

• Input Voltage Range of 3.3 V to 22 V

• Selectable 1− or 2−Phase Operation with Up to 1 MHzper Phase Switching Frequency

• Guaranteed ±8 mV Worst−Case Differentially SensedCore Voltage Error Overtemperature

• Automatic Power−Saving Mode Maximizes Efficiencywith Light Load During Deeper Sleep Operation

• Soft Transient Control Reduces Inrush Current andAudio Noise

• Active Current Balancing Between Output Phases

• Independent Current Limit and Load Line SettingInputs for Additional Design Flexibility

• Built−In Power−Good Blanking Supports VoltageIdentification (VID) OTF Transients

• 7−Bit, Digitally Programmable DAC with 0.3 V to1.5 V Output

• Short−Circuit Protection with Latchoff Delay

• Clock Enable Output Delays the CPU Clock Until theCore Voltage is Stable

• Output Load Current Monitor

• This is a Pb−Free Device

Applications• Notebook Power Supplies for Next Generation

Intel® Processors

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See detailed ordering and shipping information in the packagedimensions section on page 36 of this data sheet.

ORDERING INFORMATION

LFCSP48CASE 932AD

ADP3208DAWLYYWWG

A = Assembly LocationWL = Wafer LotYYWW = Date CodeG = Pb−Free Package

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Figure 1. Functional Block Diagram

+−

VIDDAC

VID

6V

ID5

VID

4

VID

3

VID

2V

ID1

VID

0

FBRTN

CLKEN

Delay

CLKENStartupDelay

CLKENOpenDrain

CLKENOpenDrain

PWRGDStartupDelay

CLKEN

PWRGD

PWRGDOpenDrain

+−+−

CSREF

DAC − 300mV

SoftTransient

Delay

DelayDisable

DAC

−+−+ CSREF

CSSUM

CSCOMP

ILIMN

ThermalThrottleControl

ThermalThrottleControl

TTSNS

VRTT

+−+−

OVPCSREF

1.7V

+−+−

Σ _+LLINE

REF

REFΣ

+

+

VEAFB

COMP

UVLOShutdownand Bias

UVLOShutdownand Bias

VCC ENGND RPM RT RAMP

CurrentBalancing

Circuit

CurrentBalancing

Circuit

IMON

DPRSLPDPRSLP

Logic

IRE

F

PSIPSI

CurrentMonitor

BST1

DRVH1

CurrentLimit

Circuit

OCPShutdown

Delay

SW1

PGND1

DRVL1

PVCC1

BST2

DRVH2

SW2

DRVL2

PGND2

DriverLogic

PrecisionReferencePrecisionReference

Soft−StartSoft Transient

VARFREQ

PVCC2

DAC − 200mV

ILIMP

DPRSTPDPRSTPDPRSTPDPRSTP

Oscillator

SP

ABSOLUTE MAXIMUM RATINGS

Parameter Rating Unit

VCC, PVCC1, PVCC2 −0.3 to +6.0 V

FBRTN, PGND1, PGND2 −0.3 to +0.3 V

BST1, BST2DCt < 200 ns

−0.3 to +28−0.3 to +33

V

BST1 to SW1, BST2 to SW2 −0.3 to +6.0 V

SW1, SW2DCt < 200 ns

−5.0 to +22−10 to +28

V

DRVH1 to SW1, DRVH2 to SW2 −0.3 to +6.0 V

DRVL1 to PGND1, DRVL2 to PGND2DCt < 200 ns

−0.3 to +6.0−5.0 to +6.0

V

RAMP (In Shutdown) DC −0.3 to +22 V

All Other Inputs and Outputs −0.3 to +6.0 V

Storage Temperature −65 to +150 °COperating Ambient Temperature Range −10 to 100 °COperating Junction Temperature 125 °C

Thermal Impedance (JA) 2−Layer Board 40 °C/W

Lead TemperatureSoldering (10 sec)Infrared (15 sec)

300260

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above theRecommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affectdevice reliability.NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.

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Figure 2. Closed−Loop Output Voltage Accuracy Figure 3. Current Sense Amplifier, VOS

Figure 4. Positioning Accuracy

TEST CIRCUITS

ADP3208DDRVL2

PGND2

PGND1

DRVL1

PVCC1

SW1

DRVH1

BST1

SW2

PVCC2

VID

3

VID

2

VID

0

DP

RS

LP

VID

1

VID

6

VID

5

VID

4

PWRGD

NC

CLKEN#

FB

FBRTN

COMP

NC

NC

EN

VARFREQ

RP

M

IRE

F

LLIN

E

CS

CO

MP

CS

RE

F

CS

SU

M

RA

MP

ILIM

N

IMO

N

ILIM

P

1

48

7-BIT CODE

5.0 V

1.05 V

1 k

80 k 20 k

100 nF

S P

VC

C

DRVH2

BST2

RT

GN

D

VRTT

TTSNS

DP

RS

TP

PS

I

ADP3208D

VCC37

CSCOMP

CSSUM

CSREF

GND

+

-

1.0 V

1 k

39 k 100 nF

5.0 V

Vos =CSCOMP - 1.0 V

40 V

17

18

19

24

ADP3208D

VCC

COMP

FB

LLINE

+

-

1.0 V

10 k

5.0 V

CSREF VID DACΔ V

37

7

6

16

18

24 GND

VFB = FB V = V − FB V=0mV

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PIN FUNCTION DESCRIPTIONS

Pin No Mnemonic Description

1 EN Enable Input. Driving this pin low shuts down the chip, disables the driver outputs, pulls PWRGD and VRTTlow, and pulls CLKEN high.

2 PWRGD Power−Good Output. Open−drain output. A low logic state means that the output voltage is outside of theVID DAC defined range.

3 NC Not Connected.

4 CLKEN Clock Enable Output. Open−drain output. A low logic state enables the CPU internal PLL clock to lock to theexternal clock.

5 FBRTN Feedback Return Input/Output. This pin remotely senses the CPU core voltage. It is also used as the groundreturn for the VID DAC and the voltage error amplifier blocks.

6 FB Voltage Error Amplifier Feedback Input. The inverting input of the voltage error amplifier.

7 COMP Voltage Error Amplifier Output and Frequency Compensation Point.

8 NC Not Connected.

9 IRPM/NC RPM Mode Timing Control Input. A resistor between this pin or RPM pin to ground sets the RPM modeturn−on threshold voltage. If a resistor is connected between this pin to ground, RPM pin must remainfloating and not connected.

10 VARFREQ Variable Frequency Enable Input. A high logic state enables the PWM clock frequency to vary with VID code.

11 VRTT Voltage Regulator Thermal Throttling Output. Logic high state indicates that the voltage regulatortemperature at the remote sensing point exceeded a set alarm threshold level.

12 TTSNS Thermal Throttling Sense and Crowbar Disable Input. A resistor divider where the upper resistor isconnected to VCC, the lower resistor (NTC thermistor) is connected to GND, and the center point isconnected to this pin and acts as a temperature sensor half bridge. Connecting TTSNS to GND disables thethermal throttling function and disables the crowbar, or Overvoltage Protection (OVP), feature of the chip.

13 IMON Current Monitor Output. This pin sources a current proportional to the output load current. A resistor toFBRTN sets the current monitor gain.

14 RPM RPM Mode Timing Control Input. A resistor between this pin or IRPM pin to ground sets the RPM modeturn−on threshold voltage. If a resistor is connected between this pin to ground, IRPM pin must remainfloating.

15 IREF This pin sets the internal bias currents. A 80 k resistor is connected from this pin to ground.

16 LLINE Load Line Programming Input. The center point of a resistor divider connected between CSREF andCSCOMP can be tied to this pin to set the load line slope.

17 CSCOMP Current Sense Amplifier Output and Frequency Compensation Point.

18 CSREF Current Sense Reference Input. This pin must be connected to the common point of the output inductors.The node is shorted to GND through an internal switch when the chip is disabled to provide soft stoptransient control of the converter output voltage.

19 CSSUM Current Sense Summing Input. External resistors from each switch node to this pin sum the inductor currentsto provide total current information.

20 RAMP PWM Ramp Slope Setting Input. An external resistor from the converter input voltage node to this pin setsthe slope of the internal PWM stabilizing ramp used for phase−current balancing.

21 ILIMN Current Limit Set. An external resistor from ILIMN to ILIMP sets the current limit threshold of the converter.

22 ILIMP Current Limit Set. An external resistor from ILIMN to ILIMP sets the current limit threshold of the converter.

23 RT PWM Oscillator Frequency Setting Input. An external resistor from this pin to GND sets the PWM oscillatorfrequency.

24 GND Analog and Digital Signal Ground.

25 BST2 High−Side Bootstrap Supply for Phase 2. A capacitor from this pin to SW2 holds the bootstrapped voltagewhile the high−side MOSFET is on.

26 DRVH2 High−Side Gate Drive Output for Phase 2.

27 SW2 Current Balance Input for Phase 2 and Current Return for High−Side Gate Drive.

28 PVCC2 Power Supply Input/Output of Low−Side Gate Driver for Phase 2.

29 DRVL2 Low−Side Gate Drive Output for Phase 2.

30 PGND2 Low−Side Driver Power Ground for Phase 2.

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Pin No DescriptionMnemonic

31 PGND1 Low−Side Driver Power Ground for Phase 1.

32 DRVL1 Low−Side Gate Drive Output for Phase 1.

33 PVCC1 Power Supply Input/Output of Low−Side Gate Driver for Phase 1.

34 SW1 Current Balance Input for Phase 1 and Current Return For High−Side Gate Drive.

35 DRVH1 High−Side Gate Drive Output for Phase 1.

36 BST1 High−Side Bootstrap Supply for Phase 1. A capacitor from this pin to SW1 holds the bootstrapped voltagewhile the high−side MOSFET is on.

37 VCC Power Supply Input/Output of the Controller.

38 SP Single−Phase Select Input. Logic high state sets single−phase configuration.

39 to45

VID6 toVID0

Voltage Identification DAC Inputs. A 7−bit word (the VID code) programs the DAC output voltage, thereference voltage of the voltage error amplifier without a load (see the VID code Table 3).

46 PSI Power State Indicator Input. Driving this pin low forces the controller to operate in single−phase mode.

47 DPRSTP Deeper Stop Control Input. The logic state of this pin is usually complementary to the state of the DPRSLPpin; however, during slow deeper sleep exit, both pins are logic low.

48 DPRSLP Deeper Sleep Control Input.

Figure 5. Pin Configuration(Top View)

EN

PWRGD

IMO

N

CLKEN

FBRTN

FB

COMP

TTSNS

VRTT

IRE

F

GN

D

ILIM

IN RT

RA

MP

LLIN

E

CS

RE

F

CS

SU

M

CS

CO

MP

BST2

DRVH2

SW2

DRVL2

PGND2

DRVL1

PVCC1

SW1

DRVH1

BST1V

CC

VARFREQ

VID

6

PS

I

VID

5

VID

4

VID

3

VID

2

VID

1

VID

0

NC

IRPM/NC

NC

RP

M

ILIM

P

SP

DP

RS

TP

DP

RS

LP

PVCC2

PGND1

1

ADP3208D

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ELECTRICAL CHARACTERISTICS VCC = PVCC1 = PVCC2 = BST1 = BST2 = High = 5.0V, FBRTN = GND = SW1 = SW2 = PGND1= PGND2 = Low = 0 V, EN = VATFREQ = High, DPRSLP = 0 V, PSI = 1.05 V, VVID = 1.2000 V, TA = −40°C to 100°C, unless otherwisenoted (Note 1). Current entering a pin (sunk by the device) has a positive sign. RREF = 80 k.

Parameter Symbol Conditions Min Typ Max Unit

VOLTAGE CONTROL − Voltage Error Amplifier (VEAMP)

FB, LLINE Voltage Range(Note 2)

VFB, VLLINE Relative to CSREF = VDAC −200 +200 mV

FB, LLINE Offset Voltage(Note 2)

VOSVEA Relative to CSREF = VDAC −0.5 +0.5 mV

FB LLINE Bias Current(Note 2)

IFB −100 100 A

LLINE Positioning Accuracy VFB − VVID Measured on FB relative to VVID, LLINEforced 80 mV below CSREF

−78 −80 −82 mV

COMP Voltage Range VCOMP Operating Range 0.85 4.0 V

COMP Current ICOMP COMP = 2.0 V, CSREF = VDACFB forced 200 mV below CSREFFB forced 200 mV above CSREF

−0.756.0

mA

COMP Slew Rate SRCOMP CCOMP = 10 pF, CSREF = VDAC, Open loop configurationFB forced 200 mV below CSREFFB forced 200 mV above CSREF

15−20

V/s

Gain Bandwidth (Note 2) GBW Non−inverting unit gain configuration,RFB = 1 k

20 MHz

VID DAC VOLTAGE REFERENCE

VDAC Voltage Range (Note 3) See VID Code Table 0 1.5 V

VDAC Accuracy VFB − VVID Measured on FB (includes offset),relative to VVID, for VID table see Table 3,VVID = 1.2125 V to 1.5000 VVVID = 0.3000 V to 1.2000 V

−9.0−7.5

+9.0+7.5

mV

VDAC Differential Non−linearity (Note 2) −1.0 +1.0 LSB

VDAC Line Regulation VFB VCC = 4.75 V to 5.25 V 0.05 %

VDAC Boot Voltage (Note 2) VBOOTFB Measured during boot delay period 1.200 V

Soft−Start Delay (Note 2) tDSS Measured from EN pos edge to FB = 50 mV 200 s

Soft−Start Time tSS Measured from EN pos edge to FB settles toVBOOT = 1.2 V within −5%

1.7 ms

Boot Delay tBOOT Measured from FB settling to VBOOT = 1.2 Vwithin −5% to CLKEN neg edge

150 s

VDAC Slew Rate Soft−StartNon−LSB VID step, DPRSLP = H,Slow C4 Entry/ExitNon−LSB VID step, DPRSLP = L,Fast C4 Exit

0.06250.25

1.0

LSB/s

FBRTN Current IFBRTN 90 200 A

VOLTAGE MONITORING AND PROTECTION − Power Good

CSREF UndervoltageThreshold

VUVCSREF Relative to DAC Voltage: = 0.5 V to 1.5 V= 0.3 V to 0.4875 V

−360−360

−300−300

−240−160

mV

CSREF OvervoltageThreshold

VOVCSREF Relative to nominal DAC Voltage 150 200 250 mV

CSREF Crowbar VoltageThreshold

VCBCSREF Relative to FBRTN 1.57 1.7 1.78 V

CSREF Reverse VoltageThreshold

VRVCSREF Relative to FBRTN, Latchoff mode:CSREF FallingCSREF Rising

−350 −300−70 −5.0

mV

1. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).2. Guaranteed by design or bench characterization, not production tested.3. Timing is referenced to the 90% and 10% points, unless otherwise noted.

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Parameter UnitMaxTypMinConditionsSymbol

VOLTAGE MONITORING AND PROTECTION − Power Good

PWRGD Low Voltage VPWRGD IPWRGD(SINK) = 4 mA 50 150 mV

PWRGD High, LeakageCurrent

IPWRGD VPWRDG = 5.0 V 0.1 A

PWRGD Startup Delay TSSPWRGD Measured from CLKEN neg edge toPWRGD Pos Edge

8.0 ms

PWRGD Latchoff Delay TLOFFPWRGD Measured from Out−off−Good−Windowevent to Latchoff (switching stops)

8.0 ms

PWRGD Propagation Delay(Note 3)

TPDPWRGD Measured from Out−off−Good−Windowevent to PWRGD neg edge

200 ns

Crowbar Latchoff Delay(Note 2)

TLOFFCB Measured from Crowbar event to Latchoff(switching stops)

200 ns

PWRGD Masking Time Triggered by any VID change or OCP event 100 s

CSREF Soft−StopResistance

EN = L or Latchoff condition 70

CURRENT CONTROL − Current Sense Amplifier (CSAMP)

CSSUM, CSREF Common−Mode Range(Note 2)

Voltage range of interest 0 2.0 V

CSSUM, CSREF OffsetVoltage

VOSCSA TA = 25°CCSREF − CSSUM, TA = −10°C to 85°CCSREF − CSSUM, TA = −40°C to 85°C

−0.5−1.7−1.8

+0.5+1.7+1.8

mV

CSSUM Bias Current IBCSSUM −50 +50 nA

CSREF Bias Current IBCSREF −120 +120 nA

CSCOMP Voltage Range (Note 2) Operating Range 0.05 2.0 V

CSCOMP CurrentICSCOMPsourceICSCOMPsink

CSCOMP = 2.0 VCSSUM forced 200 mV below CSREFCSSUM forced 200 mV above CSREF

−7501.0

AmA

CSCOMP Slew Rate CCSCOMP = 10 pF, Open Loop ConfigurationCSSUM forced 200 mV below CSREFCSSUM forced 200 mV above CSREF

10−10

V/s

Gain Bandwidth (Note 2) GBWCSA Non−inverting unit gain configurationRFB = 1 k

20 MHz

CURRENT MONITORING AND PROTECTION

Current ReferenceIREF Voltage VREF RREF = 80 k to set IREF = 20 A 1.55 1.6 1.65

V

Current Limiter (OCP)Current Limit Threshold VLIMTH Measured from CSCOMP to CSREF,

RLIM = 4.5 k,2−ph configuration, PSI = H2−ph configuration, PSI = L1−ph configurationMeasured from CSCOMP to CSREF,RLIM = 4.5 k, 3−ph configuration, PSI = H3−ph configuration, PSI = L1−ph configuration

−70−32−70

−70−15−70

−95−47.5−95

−90−30−90

−115−65−115

−115−50−115

mV

Current Limit Latchoff Delay Measured from OCP event to PWRGDdeassertion

8.0 ms


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CURRENT MONITOR

Current Gain Accuracy IMON/ILIM Measured from ILIMP to IMONILIM = −20 AILIM = −10 AILIM = −5 A

9.59.39.0

101010

10.510.711.0

IMON Clamp Voltage VMAXMON Relative to FBRTN, ILIMP = −30 A 1.0 1.05 V

PULSE WIDTH MODULATOR − Clock Oscillator

RT Voltage VRT VARFREQ = High, RT = 125 k,VVID = 1.5000 VVARFREQ = Low, See also VRT(VVID) formula

1.22

0.98

1.25

1.0

1.27

1.02

V

PWM Clock FrequencyRange (Note 2)

fCLK Operating Range 0.3 3.0 MHz

PWM Clock Frequency fCLK TA = 25°C, VVID = 1.2000 VRT = 73 kRT = 125 kRT = 180 k

1200680400

1470920640

17201120840

kHz

RAMP GENERATOR

RAMP Voltage VRAMP EN = high, IRAMP = 30 AEN = low

0.9 1.0VIN

1.1 V

RAMP Current Range(Note 2)

IRAMP EN = highEN = low, RAMP = 19 V

1.0−0.5

100+0.5

A

PWM COMPARATOR

PWM Comparator Offset(Note 2)

VOSRPM VRAMP − VCOMP −3.0 3.0 mV

RPM COMPARATOR

RPM Current IRPM VVID = 1.2 V, RT = 125 kVARFREQ = High, See also IRPM(RT) formula

−8.8 A

RPM Comparator Offset(Note 2)

VOSRPM VCOMP − (1 +VRPM) −3.0 3.0 mV

EPWM CLOCK SYNC

Trigger Threshold (Note 2) Relative to COMP sampled TCLK earlier2−phase configuration1−phase configuration

400450

mV

SWITCH AMPLIFIER

SW Common Mode Range(Note 2)

VSW(X)CM Operating Range for current sensing −600 +200 mV

SW Resistance RSW_PGND(X) Measured from SW to PGND 3.0 k

ZERO CURRENT SWITCHING COMPARATOR

SW ZCS Threshold VDCM(SW1) DCM mode, DPRSLP = 3.3 V −6.0 mV

Masked Off Time tOFFMSKD Measured from DRVH neg edge to DRVHpos edge at max frequency of operation

700 ns

SYSTEM I/O BUFFERS VID[6:0], PSI INPUTS

Input Voltage Refers to driving signal levelLogic low, Isink 1 ALogic high, Isource −5 A 0.7

0.3V

Input Current V = 0.2 VVID[6:0], DPRSLP (active pulldown to GND)PSI (active pullup to VCC)

−1.0+1.0

A

VID Delay Time (Note 2) Any VID edge to FB change 10% 200 ns


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DPRSLP


1.0V

Input Current DPRSLP = lowDPRSLP = high

−1.0+2.0

A

DPRSTP


0.3V

Input Current 1.0 A

VARFREQ, SP


0.7V

Input Current 1.0 A

EN INPUT


1.0V

Input Current EN = L or EN = H (Static)0.8 V < EN < 1.6 V (During Transition)

1070

nAA

CLKEN OUTPUT

Output Low Voltage Logic low, Isink = 4 mA 50 100 mV

Output High, LeakageCurrent

Logic high, VCLKEN = VCC 1.0 A

THERMAL MONITORING AND PROTECTION

TTSNS Voltage Range(Note 2)

0 5.0 V

TTSNS Threshold VCC = 5.0 V, TTSNS is falling 2.45 2.5 2.55 V

TTSNS Hysteresis 50 110 mV

TTSNS Bias Current TTSNS = 2.6 V −2.0 2.0 A

VRTT Output Voltage VVRTT Logic low, IVRTT(SINK) = 400 ALogic high, IVRTT(SOURCE) = −400 A 4.0

105.0

100 mVV

SUPPLY

Supply Voltage Range VCC 4.5 5.5 V

Supply Current EN = HEN = 0 V

6.015

1050

mAA

VCC OK Threshold VCCOK VCC is Rising 4.3 4.5 V

VCC UVLO Threshold VCCUVLO VCC is Falling 4.0 4.1 V

VCC Hysteresis (Note 2) 210 mV

HIGH−SIDE MOSFET DRIVER

Pullup Resistance, SourcingCurrent

BST = PVCC 1.8 3.3

Pulldown Resistance, SinkingCurrent

BST = PVCC 1.0 3.0


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HIGH−SIDE MOSFET DRIVER

Transition Times trDRVHtfDRVH

BST = PVCC, CL = 3 nF, Figure 6BST = PVCC, CL = 3 nF, Figure 6

1513

3531

ns

Dead Delay Times tpdhDRVH BST = PVCC, Figure 6 39 50 ns

BST Quiescent Current EN = L (Shutdown)EN = H, no switching

0.615

5.0 A

LOW−SIDE MOSFET DRIVER

Pullup Resistance, SourcingCurrent

BST = PVCC 1.6 3.3

Pulldown Resistance, SinkingCurrent

BST = PVCC 0.8 2.5

Transition Times trDRVLtfDRVL

CL = 3 nF, Figure 6CL = 3 nF, Figure 6

1514

3535

ns

Progation Delay Times tpdhDRVL CL = 3 nF, Figure 6 10 45 ns

SW Transition Times tTOSW DRVH = L, SW = 2.5 V 210 250 450 ns

SW Off Threshold VOFFSW 1.6 V

PVCC Quiescent Current EN = L (Shutdown)EN = H, no switching

1.0240

15 A

BOOTSTRAP RECTIFIER SWITCH

On Resistance EN = L or EN = H and DRVL = H 3.0 6.0 1.0


Figure 6. Timing Diagram (Note 3)

IN

DRVH(WITH RESPECT TO SW)

DRVL

SW

tpdlDRVL tfDRVLtrDRVLtpdlDRVH

tfDRVHtpdhDRVH trDRVH

VTH VTH

1.0 V

tpdhDRVL

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TYPICAL PERFORMANCE CHARACTERISTICSVVID = 1.5 V, TA = 20°C to 100°C, unless otherwise noted.

Figure 7. PWM Mode Efficiency vs. Load Current Figure 8. Load Transient with 2−Phases

Figure 9. Load Transient with 2 Phases Figure 10. Switching Waveforms in 2 Phase

Figure 11. Switching Waveforms in 2−Phase Figure 12. Switching Frequency vs. VID OutputVoltage in PWM Mode

50

55

60

65

70

75

80

85

90

95

0 5 10 15 20 25 30 35 40 45

LOAD CURRENT (A)

EF

FIC

IEN

CY

(%

)

VIN = 9.0 V

VIN = 9.0 V

fSW = 305 kHz

VOUT = 1.2 VOUTPUT VOLTAGE

SW1

SW2

Input = 12 V, Output = 1.0 V44 A to 9 A Load Step

OUTPUT VOLTAGE

SW1

SW2

Input = 12 V, Output = 1.0 V9 A to 44 A Load Step

OUTPUT RIPPLE

SW1

SW2

CSREF to CSCOMP

Input = 12 V, Output = 1.1 VNo Load

OUTPUT RIPPLE

SW1

SW2

COMP

Input = 12 V, Output = 1.1 VNo Load

0

50

100

150

200

250

300

350

400

0.25 0.5 0.75 1 1.25 1.5

VID OUTPUT VOLTAGE (V)

VARFREQ = 5.0 V

VARFREQ = 0 V

2−Phase ModeRT = 187 kΩ

PE

R P

HA

SE

SW

ITC

HIN

G F

RE

QU

EN

CY

(kH

z)

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TYPICAL PERFORMANCE CHARACTERISTICSVVID = 1.5 V, TA = 20°C to 100°C, unless otherwise noted.

Figure 13. Switching Frequency vs. OutputVoltage in RPM Mode

Figure 14. IMON Voltage vs. Output Current

Figure 15. Per Phase Switching Frequency vs. RTResistance

Figure 16. Load Line Accuracy

Figure 17. VCC Current vs. VCC Voltage withEnable Low

Figure 18. Startup Waveforms

EN

PWRGND

CLKEN

OUTPUT VOLTAGE

350

00 1.5

OUTPUT VOLTAGE (V)

SW

ITC

HIN

G F

RE

QU

EN

CY

(kH

z)

300

250

200

150

100

50

0.5 1.0

RT = 237 kRPM = 80.5 k

1200

00 80

OUTPUT POWER ( )

PM

ON

VO

LTA

GE

(m

V)

1000

800

600

400

200

20 40 60

100

1000

10 100 1000

Rt RESISTANCE (k )

Sw

itch

ing

Fre

qu

ency

(kH

z)

VID = 0.6125

VID = 0.8125

VID = 1.1 V

VID = 1.2125 V

VID = 1.4125 V

2−Phase Configuration

0.85

0.9

0.95

1

1.05

0 10 20 30 40 50

Load (A)

Ou

tpu

t (V

)

-2%

+2%2-Phase

PSI = High

1-PhasePSI = Low

0

0.2

0.4

0.6

0.8

0 1 2 3 4 5 6

VCC VOLTAGE (V)

VC

C C

UR

RE

NT

(m

A)

VDC = 12 V

EN = LOW

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TYPICAL PERFORMANCE CHARACTERISTICS

VVID = 1.5 V, TA = 20°C to 100°C, unless otherwise noted.

Figure 19. Dual−Phase, Interleaved PWM Waveform, 20 A Load

Figure 20. PSI Transition Figure 21. PSI Transition

SWITCH NODE 2

OUTPUT VOLTAGE

PSI

CH1 10.0VCH3 5.00AREF1 10.0V 1.00s

CH2 5.00ACH4 20.0mV

A CH3 8.00AM1.00s

T 20.00%

1

R1

2

4

OUTPUT VOLTAGE

L2 CURRENT L1 CURRENT

SWITCH NODE 1

SWITCH NODE 2

SWITCH NODE 1

SWITCH NODE 2

OUTPUT VOLTAGE

SWITCH NODE 1

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TYPICAL PERFORMANCE CHARACTERISTICS

VVID = 1.5 V, TA = 20°C to 100°C, unless otherwise noted.

Figure 22. DPRSLP Transition Figure 23. DPRSLP Transition

Figure 24. DPRSLP Transition Figure 25. DPRSLP Transition

OUTPUT VOLTAGE

= HIGHLOAD = 2 A

DPRSLP

SWITCH NODE 2

OUTPUT VOLTAGE

SWITCH NODE 1

PSI = HIGHLOAD = 2 APSI

DPRSLP

SWITCH NODE 2

SWITCH NODE 1

OUTPUT VOLTAGE

= LOWLOAD = 2 A

DPRSLP

SWITCH NODE 2

OUTPUT VOLTAGE

SWITCH NODE 1

PSI = LOWLOAD = 2 APSI

DPRSLP

SWITCH NODE 2SWITCH NODE 1

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Theory of OperationThe ADP3208D combines multi−mode Pulse Width

Modulated (PWM) control and Ramp Pulse Modulated(RPM) control with multi−phase logic outputs for use insingle− and dual−phase synchronous buck CPU core supplypower converters. The internal 7−bit VID DAC conforms tothe Intel IMVP−6+ specifications.

Multiphase operation is important for producing the highcurrents and low voltages demanded by today’smicroprocessors. Handling high currents in a single−phaseconverter would put too high of a thermal stress on systemcomponents such as the inductors and MOSFETs.

The multi−mode control of the ADP3208D is a stable,high performance architecture that includes• Current and thermal balance between phases• High speed response at the lowest possible switching

frequency and minimal count of output decouplingcapacitors

• Minimized thermal switching losses due to lowerfrequency operation

• High accuracy load line regulation• High current output by supporting 2−phase operation• Reduced output ripple due to multiphase ripple

cancellation• High power conversion efficiency with heavy and light

loads• Increased immunity from noise introduced by PC board

layout constraints• Ease of use due to independent component selection• Flexibility in design by allowing optimization for either

low cost or high performance

Number of PhasesThe number of operational phases can be set by the user.

Tying the SP pin to the VCC pin forces the chip intosingle−phase operation. Otherwise, dual−phase operation isautomatically selected, and the chip switches betweensingle− and dual−phase modes as the load changes tooptimize power conversion efficiency.

In dual−phase configuration, SP is low and the timingrelationship between the two phases is determined byinternal circuitry that monitors the PWM outputs. Becauseeach phase is monitored independently, operationapproaching 100% duty cycle is possible. In addition, more

than one output can be active at a time, permittingoverlapping phases.

Operation ModesThe number of phases can be static (see the Number of

Phases section) or dynamically controlled by system signalsto optimize the power conversion efficiency with heavy andlight loads.

If SP is set low (user−selected dual−phase mode) duringa VID transient or with a heavy load condition (indicated byDPRSLP being low and PSI being high), the ADP3208Druns in 2−phase, interleaved PWM mode to achieve minimalVCORE output voltage ripple and the best transientperformance possible. If the load becomes light (indicated byPSI being low or DPRSLP being high), ADP3208D switchesto single−phase mode to maximize the power conversionefficiency.

In addition to changing the number of phases, theADP3208D is also capable of dynamically changing thecontrol method. In dual−phase operation, the ADP3208Druns in PWM mode, where the switching frequency iscontrolled by the master clock. In single−phase operation(commanded by the PSI low state), the ADP3208D runs inRPM mode, where the switching frequency is controlled bythe ripple voltage appearing on the COMP pin. In RPMmode, the DRVH1 pin is driven high each time the COMPpin voltage rises to a voltage limit set by the VID voltage andan external resistor connected from the RPM to GND. If thedevice is in single−phase mode and the system signalDPRSLP is asserted high during the deeper sleep mode ofCPU operation, the ADP3208D continues running in RPMmode but offers the option of turning off the low−side(synchronous rectifier) MOSFET when the inductor currentdrops to 0. Turning off the low−side MOSFETs at the zerocurrent crossing prevents reversed inductor current build upand breaks synchronous operation of high− and low−sideswitches. Due to the asynchronous operation, the switchingfrequency becomes slower as the load current decreases,resulting in good power conversion efficiency with verylight loads.

Table 1 summarizes how the ADP3208D dynamicallychanges the number of active phases and transitions theoperation mode based on system signals and operatingconditions.

Table 1. Phase Number and Operation Modes

PSI DPRSLPVID Transient

(Note 1) Current LimitNo. of Phases

Selected by UserNo. of Phases in Operation Operation Mode (Note 2)

* * Yes * N [2 or 1] N PWM, CCM only

1 0 No * N [2 or 1] N PWM, CCM only

0 0 No No * 1 RPM, CCM only

0 0 No Yes * 1 PWM, CCM only

* 1 No No * 1 RPM, automatic CCM/DCM

* 1 No Yes * 1 PWM, CCM only

* = Don’t Care1. VID transient period is the time following any VID change, including entry into and exit from deeper sleep mode. The duration of VID transient

period is the same as that of PWRGD masking time.2. CCM stands for continuous current mode, and DCM stands for discontinuous current mode.

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Figure 26. Single−Phase RPM Mode Operation

IR = AR IRAMP QS

RD

FLIP−FLOP

1V

QS

RD

FLIP−FLOP

RA

CFB RB

CA CB

VDC

VCS

RCS

CCS

RPH

RPH

DRVH

DRVL

GATE DRIVER

SW

VCC

LRI

LRI

LOAD

COMP FB FBRTN CSCOMPCSSUM

CSREF

DRVL1

SW1

DRVH1CR

VRMP

BST

BST1

5V

VCC

DRVL2

SW2

DRVH2

BST2

5V

Q

400ns

Q

R2

R1

R1R2

1V

30mV

INDCM

LLINE

+ –

+

–

+

+

06374-024

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Figure 27. Dual−Phase PWM Mode Operation

IR = AR IRAMP

AD

0.2V

CLOCKOSCILLATOR QS

RD

FLIP−FLOP

IR = AR IRAMP

AD

0.2V

CLOCKOSCILLATOR QS

RD

FLIP−FLOP

VCC

LRI

LRI

LOADCR

CR

DRVH

DRVL

GATE DRIVER

SW

VCC

DRVL1

SW1

DRVH1

BST

BST1

5V

IN

DRVH

DRVL

GATE DRIVER

SW

VCC

DRVL2

SW2

DRVH2

BST

BST2

5V

RAMP

RA

CFB RB

CA CB

VDC

VCS

RCS

CCS

RPH

RPH

COMP FB FBRTN CSCOMPCSSUM

CSREF

LLINE

+

+ –

+

–

+

06374-025

Setting Switch FrequencyMaster Clock Frequency in PWM Mode

When the ADP3208D runs in PWM, an external resistorconnected from the RT pin to GND sets the clock frequency.The frequency is constant at a given VID code but varieswith the VID voltage: the lower the VID voltage, the lowerthe clock frequency. The variation of clock frequency withVID voltage maintains constant VCORE ripple and improvespower conversion efficiency at lower VID voltages.Figure 15 shows the relationship between clock frequencyand VID voltage, parametrized by RT resistance.

To determine the switching frequency per phase, dividethe clock by the number of phases in use.

Switching Frequency in RPM Mode — Single−PhaseOperation

In single−phase RPM mode, the switching frequency iscontrolled by the ripple voltage on the COMP pin, ratherthan by the master clock. Each time the COMP pin voltageexceeds the RPM pin voltage threshold level determined bythe VID voltage and the external resistor connected fromRPM to GND, an internal ramp signal is started and DRVH1is driven high. The slew rate of the internal ramp isprogrammed by the current entering the RAMP pin.One−third of the RAMP current charges an internal ramp

capacitor (5 pF typical) and creates a ramp. When theinternal ramp signal intercepts the COMP voltage, theDRVH1 pin is reset low.

In continuous current mode, the switching frequency ofRPM operation is almost constant. While in discontinuouscurrent conduction mode, the switching frequency isreduced as a function of the load current.

Differential Sensing of Output VoltageThe ADP3208D combines differential sensing with a high

accuracy VID DAC, referenced by a precision band gapsource and a low offset error amplifier, to meet the rigorousaccuracy requirement of the Intel IMVP−6+ specification.In steady−state mode, the combination of the VID DAC anderror amplifier maintain the output voltage for a worst−casescenario within ±8 mV of the full operating output voltageand temperature range.

The CPU core output voltage is sensed between the FBand FBRTN pins. FB should be connected through a resistorto the positive regulation point; the VCC remote sensing pinof the microprocessor. FBRTN should be connected directlyto the negative remote sensing point; the VSS sensing pointof the CPU. The internal VID DAC and precision voltagereference are referenced to FBRTN and have a maximumcurrent of 200 A for guaranteed accurate remote sensing.

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Output Current SensingThe ADP3208D includes a dedicated Current Sense

Amplifier (CSA) to monitor the total output current of theconverter for proper voltage positioning vs. load current andfor over current detection. Sensing the current delivered tothe load is an inherently more accurate method thandetecting peak current or sampling the current across a senseelement, such as the low−side MOSFET. The CSA can beconfigured several ways, depending on system optimizationobjectives, and the current information can be obtained by:• Output inductor ESR sensing without the use of a

thermistor for the lowest cost• Output inductor ESR sensing with the use of a

thermistor that tracks inductor temperature to improveaccuracy

• Discrete resistor sensing for the highest accuracyAt the positive input of the CSA, the CSREF pin is

connected to the output voltage. At the negative input (thatis, the CSSUM pin of the CSA), signals from the sensingelement (in the case of inductor DCR sensing, signals fromthe switch node side of the output inductors) are summedtogether by series summing resistors. The feedback resistorbetween the CSCOMP and CSSUM pins sets the gain of theCSA, and a filter capacitor is placed in parallel with thisresistor. The current information is then given as the voltagedifference between the CSCOMP and CSREF pins. Thissignal is used internally as a differential input for the currentlimit comparator.

An additional resistor divider connected between theCSCOMP and CSREF pins with the midpoint connected tothe LLINE pin can be used to set the load line required by themicroprocessor specification. The current information to setthe load line is then given as the voltage difference betweenthe LLINE and CSREF pins. This configuration allows theload line slope to be set independent from the current limitthreshold. If the current limit threshold and load line do nothave to be set independently, the resistor divider between theCSCOMP and CSREF pins can be omitted and theCSCOMP pin can be connected directly to LLINE. Todisable voltage positioning entirely (that is, to set no loadline), LLINE should be tied to CSREF.

To provide the best accuracy for current sensing, the CSAhas a low offset input voltage and the sensing gain is set byan external resistor ratio.

Active Impedance Control ModeTo control the dynamic output voltage droop as a function

of the output current, the signal that is proportional to thetotal output current, converted from the voltage differencebetween LLINE and CSREF, can be scaled to be equal to therequired droop voltage. This droop voltage is calculated bymultiplying the droop impedance of the regulator by theoutput current. This value is used as the control voltage ofthe PWM regulator. The droop voltage is subtracted from theDAC reference output voltage, and the resulting voltage is

used as the voltage positioning setpoint. The arrangementresults in an enhanced feed−forward response.

Current Control Mode and Thermal BalanceThe ADP3208D has individual inputs for monitoring the

current of each phase. The phase current information iscombined with an internal ramp to create acurrent−balancing feedback system that is optimized forinitial current accuracy and dynamic thermal balance. Thecurrent balance information is independent from the totalinductor current information used for voltage positioningdescribed in the Active Impedance Control Mode section.

The magnitude of the internal ramp can be set so that thetransient response of the system is optimal. The ADP3208Dmonitors the supply voltage to achieve feed forward controlwhenever the supply voltage changes. A resistor connectedfrom the power input voltage rail to the RAMP pindetermines the slope of the internal PWM ramp. More detailabout programming the ramp is provided in the ApplicationInformation section.

The ADP3208D should not require external thermalbalance circuitry if a good layout is used. However, ifmismatch is desired due to uneven cooling in phase, externalresistors can be added to individually control phase currentsas long as the phase currents are mismatched by less than30%. If unwanted mismatch exceeds 30%, a new layout thatimproves phase symmetry should be considered.

Figure 28. Optional Current Balance Resistors

20RAMP

ADP3208D

R1C R2R SW1

R SW2

SWITCH NODE 1

SWITCH NODE 2

VDC

Reserved for Thermal Balance Tune

In 2−phase operation, alternate cycles of the internal rampcontrol the duty cycle of the separate phases. Figure 28shows the addition of two resistors from each switch nodeto the RAMP pin; this modifies the ramp−charging currentindividually for each phase. During Phase 1, SW Node 1 ishigh (practically at the input voltage potential) and SWNode 2 is low (practically at the ground potential). As aconsequence, the RAMP pin, through the R2 resistor, seesthe tap point of a divider connected to the input voltage,where RSW1 is the upper element and RSW2 is the lowerelement of the divider. During Phase 2, the voltages on SWNode 1 and SW Node 2 switch and the resistors swapfunctions. Tuning RSW1 and RSW2 allows the current to beoptimally set for each phase. To increase the current for agiven phase, decrease RSW for that phase.

Voltage Control ModeA high−gain bandwidth error amplifier is used for the

voltage mode control loop. The noninverting input voltage

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is set via the 7−bit VID DAC. The VID codes are listed in theVID Code table. The noninverting input voltage is offset bythe droop voltage as a function of current, commonly knownas active voltage positioning. The output of the erroramplifier is the COMP pin, which sets the terminationvoltage of the internal PWM ramps.

At the negative input, the FB pin is tied to the output senselocation using RB, a resistor for sensing and controlling theoutput voltage at the remote sensing point. The main loopcompensation is incorporated in the feedback networkconnected between the FB and COMP pins.

Power−Good MonitoringThe power−good comparator monitors the output voltage

via the CSREF pin. The PWRGD pin is an open−drainoutput that can be pulled up through an external resistor toa voltage rail, not necessarily the same VCC voltage rail thatis running the controller. A logic high level indicates that theoutput voltage is within the voltage limits defined by a rangearound the VID voltage setting. PWRGD goes low when theoutput voltage is outside of this range.

Following the IMVP−6+ specification, the PWRGDrange is defined to be 300 mV less than and 200 mV greaterthan the actual VID DAC output voltage. For any DACvoltage less than 300 mV, only the upper limit of thePWRGD range is monitored. To prevent a false alarm, thepower−good circuit is masked during various systemtransitions, including a VID change and entrance into or exitout of deeper sleep. The duration of the PWRGD mask is setto approximately 130 s by an internal timer. If the voltagedrop is greater than 200 mV during deeper sleep entry orslow deeper sleep exit, the duration of PWRGD masking isextended by the internal logic circuit.

Powerup Sequence and Soft−StartThe power−on ramp−up time of the output voltage is set

internally. The powerup sequence, including the soft−start isillustrated in Figure 29.

After EN is asserted high, the soft−start sequence starts.The core voltage ramps up linearly to the boot voltage. TheADP3208D regulates at the boot voltage for 100 s. Afterthe boot time is completed, CLKEN is asserted low. AfterCLKEN is asserted low for 9ms, PWRGD is asserted high.

In VCC UVLO or in shutdown, a small MOSFET turns onconnecting the CSREF to GND. The MOSFET on theCSREF pin has a resistance of approximately 100. WhenVCC ramps above the upper UVLO threshold and EN isasserted high, the ADP3208D enables internal bias andstarts a reset cycle that lasts about 50 s to 60 s. Next, wheninitial reset is over, the chip detects the number of phases setby the user, and gives a go signal to start soft−start. TheADP3208D reads the VID codes provided by the CPU onVID0 to VID6 input pins after CLKEN is asserted low. ThePWRGD signal is asserted after a tCPU_PWRGD delay ofabout 9 ms, as specified by IMVP−6+. The power−gooddelay is programmed internally.

Figure 29. Powerup Sequence of ADP3208D

VCC

EN

VCORE

CLKEN

PWRGD

t BOOT

t CPU _PWRGD

If EN is taken low or VCC drops below the VCC UVLOthreshold, both the SS capacitor and the PGDELAYcapacitor are reset to ground to prepare the chip for asubsequent soft−start cycle.

Soft TransientWhen a VID input changes, the ADP3208D detects the

change but ignores new code for a minimum of 400 ns. Thisdelay is required to prevent the device from reacting todigital signal skew while the 7−bit VID input code is intransition. Additionally, the VID change triggers a PWRGDmasking timer to prevent a PWRGD failure. Each VIDchange resets and retriggers the internal PWRGD maskingtimer.

The ADP3208D provides a soft transient function toreduce inrush current during VID transitions. Reducing theinrush current helps decrease the acoustic noise generatedby the MLCC input capacitors and inductors.

The soft transient feature is implemented internally. Whena new VID code is detected, the ADP3208D stepssequentially through each VID voltage to the final VIDvoltage. There is a PWRGD masking time of 100s after thelast VID code is changed internally. Table 2 lists the softtransient slew rate.

Table 2. Soft Transient Slew Rate

VID Transient DPRSLP Slew Rate

Entrance to Deeper Sleep HIGH −3.125mV/s

Fast Exit from Deeper Sleep LOW +12.5mV/s

Slow Exit from Deeper Sleep HIGH +3.125mV/s

Transient from VBOOT to VID DNC1 ±3.125mV/s

1. DNC = Do Not Care.

Current LimitThe ADP3208D compares the differential output of a

current sense amplifier to a programmable current limitsetpoint to provide current limiting function. The currentlimit set point is set with a resistor connected from ILIM pinto CSCOMP pin. This is the Rlim resistor. During normal

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operation, the voltage on the ILIM pin is equal to the CSREFpin. The voltage across RLIM is equal to the voltage acrossthe CSA (from CSREF pin to CSCOMP pin). This voltageis proportional to output current. The current through RLIMis proportional to the output inductor current. The currentthrough RLIM is compared with an internal referencecurrent. When the RLIM current goes above the internalreference current, the ADP3208D goes into current limit.The current limit circuit is shown in Figure 30.

Figure 30. Current Limit Circuit

+

-

20 μA

R R

ILIM

+-

+-

CSA

CLAVI CONV

LDCR

ILIM CSSUMCSCOMP

CSREF

ILIM

RLIM

RCS

CCS

RPH CBULK

During startup when the output voltage is below 200 mV,a secondary current limit is activated. This is necessarybecause the voltage swing on CSCOMP cannot extendbelow ground. The secondary current limit circuit clampsthe internal COMP voltage and sets the internalcompensation ramp termination voltage at 1.5 V level. Theclamp actually limits voltage drop across the low sideMOSFETs through the current balance circuitry.

An inherent per phase current limit protects individualphases in case one or more phases stop functioning becauseof a faulty component. This limit is based on the maximumnormal mode COMP voltage.

After 9 ms in current limit, the ADP3208D will latchoff.The latchoff can be reset by removing and reapplying VCC,or by recycling the EN pin low and high for a short time.

The latchoff can be reset by removing and reapplyingVCC, or by recycling the EN pin low and high for a shorttime.

Figure 31. Current Overload

PWRGD 2.0 V/DIV

OUTPUT 0.5 V/DIV

2 ms/DIV

CURRENT LIMITAPPLIED

LATCHEDOFF

Changing VID OTFThe ADP3208D is designed to track dynamically

changing VID code. As a consequence, the CPU VCCvoltage can change without the need to reset the controlleror the CPU. This concept is commonly referred to as VIDOTF transient. A VID OTF can occur with either light orheavy load conditions. The processor alerts the controllerthat a VID change is occurring by changing the VID inputsin LSB incremental steps from the start code to the finishcode. The change can be either upwards or downwards steps.

When a VID input changes, the ADP3208D detects thechange but ignores new code for a minimum of 400 ns. Thisdelay is required to prevent the device from reacting todigital signal skew while the 7−bit VID input code is intransition. Additionally, the VID change triggers a PWRGDmasking timer to prevent a PWRGD failure. Each VIDchange resets and retriggers the internal PWRGD maskingtimer.

As listed in Table 3, during a VID transient, theADP3208D forces PWM mode regardless of the state of thesystem input signals. For example, this means that if the chipis configured as a dual−phase controller but is running insingle−phase mode due to a light load condition, a currentoverload event causes the chip to switch to dual−phase modeto share the excessive load until the delayed current limitlatchoff cycle terminates.

In user−set single−phase mode, the ADP3208D usuallyruns in RPM mode. When a VID transition occurs, however,the ADP3208D switches to dual−phase PWM mode.

Light Load RPM DCM OperationIn single−phase normal mode, DPRSLP is pulled low and

the APD3208 operates in Continuous Conduction Mode(CCM) over the entire load range. The upper and lowerMOSFETs run synchronously and in complementary phase.See Figure 32 for the typical waveforms of the ADP3208Drunning in CCM with a 7 A load current.

Figure 32. Single−Phase Waveforms in CCM

3

1

2

4

400 ns/DIV

OUTPUT VOLTAGE 20 mV/DIV

INDUCTOR CURRENT 5 A/DIV

SWITCH NODE 5.0 V/DIV

LOW−SIDE GATE 5.0 V/DIV

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If DPRSLP is pulled high, the ADP3208D operates inRPM mode. If the load condition is light, the chip entersDiscontinuous Conduction Mode (DCM). Figure 33 showsa typical single−phase buck with one upper FET, one lowerFET, an output inductor, an output capacitor, and a loadresistor. Figure 34 shows the path of the inductor currentwith the upper FET on and the lower FET off. In Figure 35the high−side FET is off and the low−side FET is on. InCCM, if one FET is on, its complementary FET must be off;however, in DCM, both high− and low−side FETs are off andno current flows into the inductor (see Figure 36). Figure 37shows the inductor current and switch node voltage in DCM.

In DCM with a light load, the ADP3208D monitors theswitch node voltage to determine when to turn off thelow−side FET. Figure 38 shows a typical waveform in DCMwith a 1 A load current. Between t1 and t2, the inductor currentramps down. The current flows through the source drain ofthe low−side FET and creates a voltage drop across the FETwith a slightly negative switch node. As the inductor currentramps down to 0 A, the switch voltage approaches 0 V, as seenjust before t2. When the switch voltage is approximately−6 mV, the low−side FET is turned off.

Figure 37 shows a small, dampened ringing at t2. This iscaused by the LC created from capacitance on the switchnode, including the CDS of the FETs and the output inductor.This ringing is normal.

The ADP3208D automatically goes into DCM with a lightload. Figure 38 shows the typical DCM waveform of theADP3208D. As the load increases, the ADP3208D entersinto CCM. In DCM, frequency decreases with load current.Figure 39 shows switching frequency vs. load current for atypical design. In DCM, switching frequency is a functionof the inductor, load current, input voltage, and outputvoltage.

Figure 33. Buck Topology

SWITCHNODE L

DRVL

DRVH

Q1

Q2

C

OUTPUTVOLTAGE

LOAD

INPUTVOLTAGE

Figure 34. Buck Topology Inductor Current Duringt0 and t1

L

C

ON

OFF LOAD


L

CON

OFF

LOAD


L

COFF

OFF

LOAD

Figure 37. Inductor Current and Switch Node in DCM

INDUCTORCURRENT

SWITCHNODE

VOLTAGE

t0 t1 t2 t3 t4

Figure 38. Single−Phase Waveforms in DCM with 1 ALoad Current

3

1

2

4

2 s/DIV

SWITCH NODE 5.0 V/DIV

LOW−SIDE GATE DRIVE 5.0 V/DIV

OUTPUT VOLTAGE20 mV/DIV

INDUCTOR CURRENT5 A/DIV

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Figure 39. Single−Phase CCM/DCM Frequency vs.Load Current

400

00 14

LOAD CURRENT (A)

FR

EQ

UE

NC

Y (

kHz)

350

300

250

200

150

100

50

2 4 6 8 10 12

19 V INPUT

9.0 V INPUT

Output CrowbarTo prevent the CPU and other external components from

damage due to overvoltage, the ADP3208D turns off theDRVH1 and DRVH2 outputs and turns on the DRVL1 andDRVL2 outputs when the output voltage exceeds the OVPthreshold (1.7 V typical).

Turning on the low−side MOSFETs forces the outputcapacitor to discharge and the current to reverse due tocurrent build up in the inductors. If the output overvoltageis due to a drain−source short of the high−side MOSFET,turning on the low−side MOSFET results in a crowbaracross the input voltage rail. The crowbar action blows thefuse of the input rail, breaking the circuit and thus protectingthe microprocessor from destruction.

When the OVP feature is triggered, the ADP3208D islatched off. The latchoff function can be reset by removingand reapplying VCC to the ADP3208D or by briefly pullingthe EN pin low.

Pulling TTSNS to less than 1.0 V disables the overvoltageprotection function. In this configuration, VRTT should betied to ground.

Reverse Voltage ProtectionVery large reverse current in inductors can cause negative

VCORE voltage, which is harmful to the CPU and otheroutput components. The ADP3208D provides a reversevoltage protection (RVP) function without additionalsystem cost. The VCORE voltage is monitored through theCSREF pin. When the CSREF pin voltage drops to less than−300 mV, the ADP3208D triggers the RVP function bydisabling all PWM outputs and driving DRVL1 and DRVL2low, thus turning off all MOSFETs. The reverse inductorcurrents can be quickly reset to 0 by discharging the built−upenergy in the inductor into the input dc voltage source via theforward−biased body diode of the high−side MOSFETs. TheRVP function is terminated when the CSREF pin voltagereturns to greater than −100 mV.

Sometimes the crowbar feature inadvertently causesoutput reverse voltage because turning on the low−sideMOSFETs results in a very large reverse inductor current. To

prevent damage to the CPU caused from negative voltage,the ADP3208D maintains its RVP monitoring function evenafter OVP latchoff. During OVP latchoff, if the CSREF pinvoltage drops to less than −300 mV, the low−side MOSFETsis turned off. DRVL outputs are allowed to turn back onwhen the CSREF voltage recovers to greater than −100 mV.

Figure 40 shows a typical OVP test. FB pin is shorted toground causing the control to command a large duty cycle.The output voltage climbs up. When the output voltage isclimbs 200 mV above the DAC voltage, the PWRGD signalde−asserts. When the output voltage climbs to 1.7V, OVP isenabled. In OVP, the phase 1 and phase 2 low side drive turnson the low side power MOSFETs. The low side MOSFETspull the output voltage low through the power inductor.When the output voltage falls below −300 mV, ReverseVoltage Protection is enabled. In Reverse VoltageProtection, all power MOSFETs are turned off. This protectsthe CPU from seeing a large negative voltage.

Figure 40. Overvoltage Protection and ReverseVoltage Protection

OUTPUT VOLTAGE

PWRGD

PHASE 2LOW SIDE GATE

PHASE 1LOW SIDE GATE

Output Enable and UVLOFor the ADP3208D to begin switching the VCC supply

voltage to the controller must be greater than the VCCOthreshold and the EN pin must be driven high. If the VCCvoltage is less than the VCCUVLO threshold or the EN pin isa logic low, the ADP3208D shuts off. In shutdown mode, thecontroller holds the PWM outputs low, shorts the capacitorsof the SS and PGDELAY pins to ground, and drives theDRVH and DRVL outputs low.

The user must adhere to proper power supply sequencingduring startup and shutdown of the ADP3208D. All inputpins must be at ground prior to removing or applying VCC,and all output pins should be left in high impedance statewhile VCC is off.

Thermal Throttling ControlThe ADP3208D includes a thermal monitoring circuit to

detect whether the temperature of the VR has exceeded auser−defined thermal throttling threshold. The thermalmonitoring circuit requires an external resistor dividerconnected between the VCC pin and GND. The dividerconsists of an NTC thermistor and a resistor. To generate a

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voltage that is proportional to temperature, the midpoint ofthe divider is connected to the TTSNS pin. An internalcomparator circuit compares the TTSNS voltage to half theVCC threshold and outputs a logic level signal at the VRTToutput when the temperature trips the user−set alarmthreshold. The VRTT output is designed to drive an externaltransistor that in turn provides the high current, open−drainVRTT signal required by the IMVP−6+ specification. Theinternal VRTT comparator has a hysteresis of approximately

100 mV to prevent high frequency oscillation of VRTTwhen the temperature approaches the set alarm point.

Current Monitor FunctionThe ADP3208D has an output current monitor. The

IMON pin sources a current proportional to the inductorcurrent. A resistor from IMON pin to FBRTN sets the gain.A 0.1 F is added in parallel with RMON to filter the inductorripple. The IMON pin is clamped to prevent it from goingabove 1.15V

Table 3. VID Code Table

VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output (V)

0 0 0 0 0 0 0 1.5000

0 0 0 0 0 0 1 1.4875

0 0 0 0 0 1 0 1.4750

0 0 0 0 0 1 1 1.4625

0 0 0 0 1 0 0 1.4500

0 0 0 0 1 0 1 1.4375

0 0 0 0 1 1 0 1.4250

0 0 0 0 1 1 1 1.4125

0 0 0 1 0 0 0 1.4000

0 0 0 1 0 0 1 1.3875

0 0 0 1 0 1 0 1.3750

0 0 0 1 0 1 1 1.3625

0 0 0 1 1 0 0 1.3500

0 0 0 1 1 0 1 1.3375

0 0 0 1 1 1 0 1.3250

0 0 0 1 1 1 1 1.3125

0 0 1 0 0 0 0 1.3000

0 0 1 0 0 0 1 1.2875

0 0 1 0 0 1 0 1.2750

0 0 1 0 0 1 1 1.2625

0 0 1 0 1 0 0 1.2500

0 0 1 0 1 0 1 1.2375

0 0 1 0 1 1 0 1.2250

0 0 1 0 1 1 1 1.2125

0 0 1 1 0 0 0 1.2000

0 0 1 1 0 0 1 1.1875

0 0 1 1 0 1 0 1.1750

0 0 1 1 0 1 1 1.1625

0 0 1 1 1 0 0 1.1500

0 0 1 1 1 0 1 1.1375

0 0 1 1 1 1 0 1.1250

0 0 1 1 1 1 1 1.1125

0 1 0 0 0 0 0 1.1000

0 1 0 0 0 0 1 1.0875

0 1 0 0 0 1 0 1.0750

0 1 0 0 0 1 1 1.0625

0 1 0 0 1 0 0 1.0500

0 1 0 0 1 0 1 1.0375

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VID6 Output (V)VID0VID1VID2VID3VID4VID5

0 1 0 0 1 1 0 1.0250

0 1 0 0 1 1 1 1.0125

0 1 0 1 0 0 0 1.0000

0 1 0 1 0 0 1 0.9875

0 1 0 1 0 1 0 0.9750

0 1 0 1 0 1 1 0.9625

0 1 0 1 1 0 0 0.9500

0 1 0 1 1 0 1 0.9375

0 1 0 1 1 1 0 0.9250

0 1 0 1 1 1 1 0.9125

0 1 1 0 0 0 0 0.9000

0 1 1 0 0 0 1 0.8875

0 1 1 0 0 1 0 0.8750

0 1 1 0 0 1 1 0.8625

0 1 1 0 1 0 0 0.8500

0 1 1 0 1 0 1 0.8375

0 1 1 0 1 1 0 0.8250

0 1 1 0 1 1 1 0.8125

0 1 1 1 0 0 0 0.8000

0 1 1 1 0 0 1 0.7875

0 1 1 1 0 1 0 0.7750

0 1 1 1 0 1 1 0.7625

0 1 1 1 1 0 0 0.7500

0 1 1 1 1 0 1 0.7375

0 1 1 1 1 1 0 0.7250

0 1 1 1 1 1 1 0.7125

1 0 0 0 0 0 0 0.7000

1 0 0 0 0 0 1 0.6875

1 0 0 0 0 1 0 0.6750

1 0 0 0 0 1 1 0.6625

1 0 0 0 1 0 0 0.6500

1 0 0 0 1 0 1 0.6375

1 0 0 0 1 1 0 0.6250

1 0 0 0 1 1 1 0.6125

1 0 0 1 0 0 0 0.6000

1 0 0 1 0 0 1 0.5875

1 0 0 1 0 1 0 0.5750

1 0 0 1 0 1 1 0.5625

1 0 0 1 1 0 0 0.5500

1 0 0 1 1 0 1 0.5375

1 0 0 1 1 1 0 0.5250

1 0 0 1 1 1 1 0.5125

1 0 1 0 0 0 0 0.5000

1 0 1 0 0 0 1 0.4875

1 0 1 0 0 1 0 0.4750

1 0 1 0 0 1 1 0.4625

1 0 1 0 1 0 0 0.4500

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VID6 Output (V)VID0VID1VID2VID3VID4VID5

1 0 1 0 1 0 1 0.4375

1 0 1 0 1 1 0 0.4250

1 0 1 0 1 1 1 0.4125

1 0 1 1 0 0 0 0.4000

1 0 1 1 0 0 1 0.3875

1 0 1 1 0 1 0 0.3750

1 0 1 1 0 1 1 0.3625

1 0 1 1 1 0 0 0.3500

1 0 1 1 1 0 1 0.3375

1 0 1 1 1 1 0 0.3250

1 0 1 1 1 1 1 0.3125

1 1 0 0 0 0 0 0.3000

1 1 0 0 0 0 1 0.2875

1 1 0 0 0 1 0 0.2750

1 1 0 0 0 1 1 0.2625

1 1 0 0 1 0 0 0.2500

1 1 0 0 1 0 1 0.2375

1 1 0 0 1 1 0 0.2250

1 1 0 0 1 1 1 0.2125

1 1 0 1 0 0 0 0.2000

1 1 0 1 0 0 1 0.1875

1 1 0 1 0 1 0 0.1750

1 1 0 1 0 1 1 0.1625

1 1 0 1 1 0 0 0.1500

1 1 0 1 1 0 1 0.1375

1 1 0 1 1 1 0 0.1250

1 1 0 1 1 1 1 0.1125

1 1 1 0 0 0 0 0.1000

1 1 1 0 0 0 1 0.0875

1 1 1 0 0 1 0 0.0750

1 1 1 0 0 1 1 0.0625

1 1 1 0 1 0 0 0.0500

1 1 1 0 1 0 1 0.0375

1 1 1 0 1 1 0 0.0250

1 1 1 0 1 1 1 0.0125

1 1 1 1 0 0 0 0.0000

1 1 1 1 0 0 1 0.0000

1 1 1 1 0 1 0 0.0000

1 1 1 1 0 1 1 0.0000

1 1 1 1 1 0 0 0.0000

1 1 1 1 1 0 1 0.0000

1 1 1 1 1 1 0 0.0000

1 1 1 1 1 1 1 0.0000

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Application InformationThe design parameters for a typical IMVP−6+ compliant

CPU core VR application are as follows:• Maximum input voltage (VINMAX) = 19 V

• Minimum input voltage (VINMIN) = 8.0 V

• Output voltage by VID setting (VVID) = 1.4375 V

• Maximum output current (IO) = 40 A

• Droop resistance (RO) = 2.1 m

• Nominal output voltage at 40 A load (VOFL) = 1.3535 V

• Static output voltage drop from no load to full load (V) = VONL − VOFL = 1.4375 V − 1.3535 V = 84 mV

• Maximum output current step (IO) = 27.9 A

• Number of phases (n) = 2

• Switching frequency per phase (fSW) = 300 kHz

• Duty cycle at maximum input voltage (DMAX) = 0.18 V

• Duty cycle at minimum input voltage (DMIN) = 0.076 V

Setting the Clock Frequency for PWMIn PWM operation, the ADP3208D uses a

fixed−frequency control architecture. The frequency is setby an external timing resistor (RT). The clock frequency andthe number of phases determine the switching frequency perphase, which relates directly to the switching losses and thesizes of the inductors and input and output capacitors. For adual−phase design, a clock frequency of 600 kHz sets theswitching frequency to 300 kHz per phase. This selectionrepresents the trade−off between the switching losses andthe minimum sizes of the output filter components. Toachieve a 600 kHz oscillator frequency at a VID voltage of1.2 V, RT must be 187 k. Alternatively, the value for RT canbe calculated by using the following equation:

RT VVID 1.0 V

2 n fSW 9 pF 16 k

(eq. 1)

where: 9 pF and 16 k are internal IC component values.VVID is the VID voltage in volts.n is the number of phases.fSW is the switching frequency in hertz for each phase.

For good initial accuracy and frequency stability, it isrecommended to use a 1% resistor.

When VARFREQ pin is connected to ground, theswitching frequency does not change with VID. The valuefor RT can be calculated by using the following equation.

RT 1.0 V

n fSW 9 pF 16 k

(eq. 2)

For good initial accuracy and frequency stability, it isrecommended to use a 1% resistor.

Setting the Switching Frequency for RPM Operation ofPhase 1

During the RPM mode operation of Phase 1, theADP3208D runs in pseudo constant frequency, given thatthe load current is high enough for continuous current mode.While in discontinuous current mode, the switching

frequency is reduced with the load current in a linearmanner. When considering power conversion efficiency inlight load, lower switching frequency is usually preferredfor RPM mode. However, the VCORE ripple specification inthe IMVP−6 sets the limitation for lowest switchingfrequency. Therefore, depending on the inductor and outputcapacitors, the switching frequency in RPM mode can beequal, larger, or smaller than its counterpart in PWM mode.

A resistor from RPM to GND sets the pseudo constantfrequency as following:

PS(MF) 2 fSW VCC IO

nMF RG

nMF

n CISS (eq. 3)

where: AR is the internal ramp amplifier gain.CR is the internal ramp capacitor value.RR is an external resistor on the RAMPADJ pin to set theinternal ramp magnitude.

Because RR = 280 k, the following resistance sets up300 kHz switching frequency in RPM operation.

PS(MF) 2 fSW VCC IO

nMF RG

nMF

n CISS (eq. 4)

Inductor SelectionThe choice of inductance determines the ripple current of

the inductor. Less inductance results in more ripple current,which increases the output ripple voltage and the conductionlosses in the MOSFETs. However, this allows the use ofsmaller−size inductors, and for a specified peak−to−peaktransient deviation, it allows less total output capacitance.Conversely, a higher inductance results in lower ripplecurrent and reduced conduction losses, but it requireslarger−size inductors and more output capacitance for thesame peak−to−peak transient deviation. For a multiphaseconverter, the practical value for peak−to−peak inductorripple current is less than 50% of the maximum dc currentof that inductor. Equation 5 shows the relationship betweenthe inductance, oscillator frequency, and peak−to−peakripple current. Equation 6 can be used to determine theminimum inductance based on a given output ripple voltage.

IR VVID 1 DMIN

fSW L (eq. 5)

L VVID RO (1 (n DMIN))

fSW VRIPPLE (eq. 6)

Solving Equation 6 for a 16 mV peak−to−peak outputripple voltage yields

L 1.4375 V 2.1 m (1 (2 0.076)

300 kHz 16 mV 533 nH

(eq. 7)

If the resultant ripple voltage is less than the initiallyselected value, the inductor can be changed to a smallervalue until the ripple value is met. This iteration allowsoptimal transient response and minimum output decoupling.

The smallest possible inductor should be used to minimizethe number of output capacitors. Choosing a 490 nHinductor is a good choice for a starting point, and it provides

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a calculated ripple current of 9.0 A. The inductor should notsaturate at the peak current of 24.5 A, and it should be ableto handle the sum of the power dissipation caused by thewinding’s average current (20 A) plus the ac core loss. In thisexample, 330 nH is used.

Another important factor in the inductor design is theDCR, which is used for measuring the phase currents. Toolarge of a DCR causes excessive power losses, whereas toosmall of a value leads to increased measurement error. Forthis example, an inductor with a DCR of 0.8 m is used.

Selecting a Standard InductorAfter the inductance and DCR are known, select a

standard inductor that best meets the overall design goals. Itis also important to specify the inductance and DCRtolerance to maintain the accuracy of the system. Using 20%tolerance for the inductance and 15% for the DCR at roomtemperature are reasonable values that most manufacturerscan meet.

Power Inductor ManufacturersThe following companies provide surface−mount power

inductors optimized for high power applications uponrequest:• Vishay Dale Electronics, Inc.• Panasonic• Sumida Corporation• NEC Tokin Corporation

Output Droop ResistanceThe design requires that the regulator output voltage

measured at the CPU pins decreases when the output currentincreases. The specified voltage drop corresponds to thedroop resistance (RO).

The output current is measured by summing the currentsof the resistors monitoring the voltage across each inductorand by passing the signal through a low−pass filter. Thesumming is implemented by the CS amplifier that isconfigured with resistor RPH(x) (summer) and resistors RCSand CCS (filters). The output resistance of the regulator is setby the following equations:

RO RCS

RPH(x) RSENSE

(eq. 8)

CCS L

RSENSE RCS (eq. 9)

where RSENSE is the DCR of the output inductors.Either RCS or RPH(x) can be chosen for added flexibility.

Due to the current drive ability of the CSCOMP pin, the RCSresistance should be greater than 100 k. For example,initially select RCS to be equal to 200 k, and then useEquation 9 to solve for CCS:

CCS 330 nH

0.8 m 200 k 2.1 nF

(eq. 10)

If CCS is not a standard capacitance, RCS can be tuned. Forexample, if the optimal CCS capacitance is 1.5 nF, adjust RCSto 280 k. For best accuracy, CCS should be a 5% NPO

capacitor. In this example, a 220 k is used for RCS toachieve optimal results.

Next, solve for RPH(x) by rearranging Equation 8 asfollows:

(eq. 11)RPH(X)

0.8 m

2.1 m 220 k 83.8 k

The standard 1% resistor for RPH(x) is 86.6 k.

Inductor DCR Temperature CorrectionIf the DCR of the inductor is used as a sense element and

copper wire is the source of the DCR, the temperaturechanges associated with the inductor’s winding must becompensated for. Fortunately, copper has a well−knowntemperature coefficient (TC) of 0.39%/°C.

If RCS is designed to have an opposite but equalpercentage of change in resistance, it cancels thetemperature variation of the inductor’s DCR. Due to thenonlinear nature of NTC thermistors, series resistors RCS1and RCS2 (see Figure 42) are needed to linearize the NTC andproduce the desired temperature coefficient tracking.

Figure 42. Temperature−Compensation CircuitValues

ADP3208D

17

19

18

CSCOMP

CSSUM

CSREF+

-

CCS2

R R

RTH

Place as close as possibleto nearest inductor

R R R

To Switch NodesTo V

SenseOUT

Keep This Path As Short

As Possible And Well Away

From Switch Node Lines

CCS1

CS2CS1

PH2PH1 PH3

The following procedure and expressions yield values forRCS1, RCS2, and RTH (the thermistor value at 25°C) for agiven RCS value.

1. Select an NTC to be used based on its type andvalue. Because the value needed is not yetdetermined, start with a thermistor with a valueclose to RCS and an NTC with an initial toleranceof better than 5%.

2. Find the relative resistance value of the NTC attwo temperatures. The appropriate temperatureswill depend on the type of NTC, but 50°C and90°C have been shown to work well for most typesof NTCs. The resistance values are called A (A isRTH(50°C)/RTH(25°C)) and B (B isRTH(90°C)/RTH(25°C)). Note that the relativevalue of the NTC is always 1 at 25°C.

3. Find the relative value of RCS required for each ofthe two temperatures. The relative value of RCS isbased on the percentage of change needed, whichis initially assumed to be 0.39%/°C in thisexample. The relative values are called r1 (r1 is 1/(1+ TC ×(T1 − 25))) and r2 (r2 is 1/(1 + TC × (T2 − 25))),where TC is 0.0039, T1 is 50°C, and T2 is 90°C.

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4. Compute the relative values for rCS1, rCS2, and rTHby using the following equations:

(A B) r1 r2 A (1 B) r2 B (1 A) r1

A (1 B) r1 B (1 A) r2 (A B)

(eq. 12)

rCS2

rCS1 (1 A)

11rCS2

1r1rCS2

rTH 1

11rCS2

1rCS1

5. Calculate RTH = rTH × RCS, and then select athermistor of the closest value available. Inaddition, compute a scaling factor k based on theratio of the actual thermistor value used relative tothe computed one:

k RTH(ACTUAL)

RTH(CALCULATED) (eq. 13)

6. Calculate values for RCS1 and RCS2 by using thefollowing equations:

RCS1 RCS k rCS1

(eq. 14)RCS2 RCS ((1 k) (k rCS2))

For example, if a thermistor value of 100 k is selectedin Step 1, an available 0603−size thermistor with a valueclose to RCS is the Vishay NTHS0603N04 NTC thermistor,which has resistance values of A = 0.3359 and B = 0.0771.Using the equations in Step 4, rCS1 is 0.359, rCS2 is 0.729,and rTH is 1.094. Solving for rTH yields 241 k, so athermistor of 220 k would be a reasonable selection,making k equal to 0.913. Finally, RCS1 and RCS2 are foundto be 72.1 k and 166 k. Choosing the closest 1% resistorfor RCS2 yields 165 k. To correct for this approximation,73.3 k is used for RCS1.

COUT SelectionThe required output decoupling for processors and

platforms is typically recommended by Intel. For systemscontaining both bulk and ceramic capacitors, however, thefollowing guidelines can be a helpful supplement.

Select the number of ceramics and determine the totalceramic capacitance (CZ). This is based on the number andtype of capacitors used. Keep in mind that the best locationto place ceramic capacitors is inside the socket; however, thephysical limit is twenty 0805−size pieces inside the socket.Additional ceramic capacitors can be placed along the outeredge of the socket. A combined ceramic capacitor value of200 F to 300 F is recommended and is usually composedof multiple 10 F or 22 F capacitors.

Ensure that the total amount of bulk capacitance (CX) iswithin its limits. The upper limit is dependent on the VIDOTF output voltage stepping (voltage step, VV, in time, tV,with error of VERR); the lower limit is based on meeting thecritical capacitance for load release at a given maximum loadstep, IO. The current version of the IMVP−6+ specification

allows a maximum VCORE overshoot (VOSMAX) of 10 mVmore than the VID voltage for a step−off load current.

Cx(MIN)

L IO

n RO VOSMAX

IO VVID

Cz

(eq. 15)

CX(MAX) L

n k2 RO2

Vv

VVID

(eq. 16)

1 tv

VVID

Vv

n k RO

L2 1

Cz

where:

k −1n VERR

VV

(eq. 17)

To meet the conditions of these expressions and thetransient response, the ESR of the bulk capacitor bank (RX)should be less than two times the droop resistance, RO. If theCX(MIN) is greater than CX(MAX), the system does not meetthe VID OTF and/or the deeper sleep exit specifications andmay require less inductance or more phases. In addition, theswitching frequency may have to be increased to maintainthe output ripple.

For example, if 30 pieces of 10 F, 0805−size MLCcapacitors (CZ = 300 F) are used, the fastest VID voltagechange is when the device exits deeper sleep, during whichthe VCORE change is 220 mV in 22 s with a setting error of10 mV. If k = 3.1, solving for the bulk capacitance yields:

CX(MIN)

330 nH 27.9 A

2 2.1 m10 mV

27.9 A 1.4375 V

300 F

1.0 mF

CX(MAX) 330 nH 220 mV

2 3.12 (2.1 m)2 1.4375 V

1 22 s 1.4375 V 2 3.1 2.1 m

220 mV 490 nH2 1

300 F 21 mF

Using six 330 F Panasonic SP capacitors with a typicalESR of 7 m each yields CX = 1.98 mF and RX = 1.2 m.

Ensure that the ESL of the bulk capacitors (LX) is lowenough to limit the high frequency ringing during a loadchange. This is tested using:

LX 300 F (2.1 m)2 2 2 nH (eq. 18)

LX CZ RO2 Q2

where: Q is limited to the square root of 2 to ensure a criticallydamped system.

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LX is about 150 pH for the six SP capacitors, which is lowenough to avoid ringing during a load change. If the LX ofthe chosen bulk capacitor bank is too large, the number ofceramic capacitors may need to be increased to preventexcessive ringing.

For this multi−mode control technique, an all ceramiccapacitor design can be used if the conditions of Equations16, 17, and 18 are satisfied.

Power MOSFETsFor typical 20 A per phase applications, the N−channel

power MOSFETs are selected for two high−side switchesand two or three low−side switches per phase. The mainselection parameters for the power MOSFETs are VGS(TH),QG, CISS, CRSS, and RDS(ON). Because the voltage of thegate driver is 5.0 V, logic−level threshold MOSFETs must beused.

The maximum output current, IO, determines the RDS(ON)requirement for the low−side (synchronous) MOSFETs. Inthe ADP3208D, currents are balanced between phases; thecurrent in each low−side MOSFET is the output currentdivided by the total number of MOSFETs (nSF). Withconduction losses being dominant, the following expressionshows the total power that is dissipated in each synchronousMOSFET in terms of the ripple current per phase (IR) andthe average total output current (IO):

PSF (1 D) IOnSF2

112

n IRnSF2 RDS(SF)

(eq. 19)

where:D is the duty cycle and is approximately the output voltagedivided by the input voltage. IR is the inductor peak−to−peak ripple current and isapproximately:

IR (1 D) VOUT

L fSW(eq. 20)

Knowing the maximum output current and the maximumallowed power dissipation, the user can calculate the requiredRDS(ON) for the MOSFET. For 8−lead SOIC or 8−leadSOIC−compatible MOSFETs, the junction−to−ambient(PCB) thermal impedance is 50°C/W. In the worst case, thePCB temperature is 70°C to 80°C during heavy loadoperation of the notebook, and a safe limit for PSF is about 0.8W to 1.0 W at 120°C junction temperature. Therefore, for thisexample (40 A maximum), the RDS(SF) per MOSFET is lessthan 8.5 m for two pieces of low−side MOSFETs. ThisRDS(SF) is also at a junction temperature of about 120°C;therefore, the RDS(SF) per MOSFET should be less than 6 m

at room temperature, or 8.5 m at high temperature.Another important factor for the synchronous MOSFET

is the input capacitance and feedback capacitance. The ratioof the feedback to input must be small (less than 10% isrecommended) to prevent accidentally turning on thesynchronous MOSFETs when the switch node goes high.

The high−side (main) MOSFET must be able to handletwo main power dissipation components: conduction lossesand switching losses. Switching loss is related to the time forthe main MOSFET to turn on and off and to the current andvoltage that are being switched. Basing the switching speedon the rise and fall times of the gate driver impedance andMOSFET input capacitance, the following expressionprovides an approximate value for the switching loss permain MOSFET:

RRPM 2 RT

VVID 1.0 V

AR (1 D) VVID

RR CR fSW 0.5 k

(eq. 21)

where: nMF is the total number of main MOSFETs.RG is the total gate resistance.CISS is the input capacitance of the main MOSFET.

The most effective way to reduce switching loss is to uselower gate capacitance devices.

The conduction loss of the main MOSFET is given by thefollowing equation:

RRPM 2 280 k

1.150 V 1.0 V

0.5 (1 0.061) 1.150

462 k 5 pF 300 kHz

(eq. 22)

500 k 202 k

where RDS(MF) is the on resistance of the MOSFET.Typically, a user wants the highest speed (low CISS)

device for a main MOSFET, but such a device usually hashigher on resistance. Therefore, the user must select a devicethat meets the total power dissipation (about 0.8 W to 1.0 Wfor an 8−lead SOIC) when combining the switching andconduction losses.

For example, an IRF7821 device can be selected as themain MOSFET (four in total; that is, nMF = 4), withapproximately CISS = 1010 pF (max) and RDS(MF) = 18 m

(max at TJ = 120°C), and an IR7832 device can be selectedas the synchronous MOSFET (four in total; that is, nSF = 4),with RDS(SF) = 6.7 m (max at TJ = 120°C). Solving for thepower dissipation per MOSFET at IO = 40 A and IR = 9.0 Ayields 630 mW for each synchronous MOSFET and590 mW for each main MOSFET. A third synchronousMOSFET is an option to further increase the conversionefficiency and reduce thermal stress.

Finally, consider the power dissipation in the driver foreach phase. This is best described in terms of the QG for theMOSFETs and is given by the following equation:PDRV

(eq. 23)

fSW

2 n nMF QGMF nSF QQSF

ICC VCC

where QGMF is the total gate charge for each main MOSFET,and QGSF is the total gate charge for each synchronousMOSFET.

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The previous equation also shows the standby dissipation(ICC times the VCC) of the driver.

Ramp Resistor SelectionThe ramp resistor (RR) is used to set the size of the internal

PWM ramp. The value of this resistor is chosen to providethe best combination of thermal balance, stability, andtransient response. Use the following expression todetermine a starting value:

RR AR L

3 AD RDS CR

RR 0.5 360 nH

3 5 5.2 m 5 pF 462 k

(eq. 24)

where:AR is the internal ramp amplifier gain.AD is the current balancing amplifier gain.RDS is the total low−side MOSFET ON−resistance;CR is the internal ramp capacitor value.

Another consideration in the selection of RR is the size ofthe internal ramp voltage (see Equation 25). For stability andnoise immunity, keep the ramp size larger than 0.5 V. Takingthis into consideration, the value of RR in this example isselected as 280 k.

The internal ramp voltage magnitude can be calculated asfollows:

VR AR (1 D) VVID

RR CR fSW

VR 0.5 (1 0.061) 1.150 V

462 k 5 pF 280 kHz 0.83 V

(eq. 25)

The size of the internal ramp can be increased ordecreased. If it is increased, stability and transient responseimproves but thermal balance degrades. Conversely, if theramp size is decreased, thermal balance improves butstability and transient response degrade. In the denominatorof Equation 24, the factor of 3 sets the minimum ramp sizethat produces an optimal combination of good stability,transient response, and thermal balance.

COMP Pin RampIn addition to the internal ramp, there is a ramp signal on

the COMP pin due to the droop voltage and output voltageramps. This ramp amplitude adds to the internal ramp toproduce the following overall ramp signal at the PWMinput:

VRT VR

1 2(1nD)

nfSWCXRO (eq. 26)

where CX is the total bulk capacitance, and RO is the droopresistance of the regulator.

For this example, the overall ramp signal is 1.85 V.

Current Limit SetpointTo select the current limit setpoint, the resistor value for

RCLIM must be determined. The current limit threshold for

the ADP3208D is set with RCLIM. RCLIM can be found usingthe following equation:

RLIM ILIM RO

60 A (eq. 27)

where:RLIM is the current limit resistor. RO is the output load line. ILIM is the current limit set point.

When the ADP3208D is configured for 2−phaseoperation, the equation above is used to set the current limit.When the ADP3208D switches from 2−phase to 1−phaseoperation by PSI or DPRSLP signal, the current issingle−phase is one half of the current limit in 2−phase.

When the ADP3208D is configured for 1−phaseoperation, the equation above is used to set the current limit.

Output Current MonitorThe ADP3208D has output current monitor. The IMON

pin sources a current proportional to the total inductorcurrent. A resistor, RMON, from IMON to FBRTN sets thegain of the output current monitor. A 0.1 F is placed inparallel with RMON to filter the inductor current ripple andhigh frequency load transients. Since the IMON pin isconnected directly to the CPU, it is clamped to prevent itfrom going above 1.15V.

The IMON pin current is equal to the RLIM times a fixedgain of 10. RMON can be found using the following equation:

RMON 1.15 V RLIM

10 RO IFS (eq. 28)

where:RMON is the current monitor resistor. RMON is connectedfrom IMON pin to FBRTN.RLIM is the current limit resistor.RO is the output load line resistance.IFS is the output current when the voltage on IMON is at fullscale.

Feedback Loop Compensation DesignOptimized compensation of the ADP3208D allows the best

possible response of the regulator’s output to a load change.The basis for determining the optimum compensation is tomake the regulator and output decoupling appear as an outputimpedance that is entirely resistive over the widest possiblefrequency range, including dc, and that is equal to the droopresistance (RO). With the resistive output impedance, theoutput voltage droops in proportion with the load current atany load current slew rate, ensuring the optimal position andallowing the minimization of the output decoupling.

With the multi−mode feedback structure of theADP3208D, it is necessary to set the feedback compensationso that the converter’s output impedance works in parallelwith the output decoupling. In addition, it is necessary tocompensate for the several poles and zeros created by theoutput inductor and decoupling capacitors (output filter).

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A Type III compensator on the voltage feedback isadequate for proper compensation of the output filter.Figure 43 shows the Type III amplifier used in theADP3208D. Figure 44 shows the locations of the two polesand two zeros created by this amplifier.

Figure 43. Voltage Error Amplifier

RA

CB RFB

CA CFB

COMP FB

REFERENCEVOLTAGE

VOLTAGE ERRORAMPLIFIER

ADP3208D

OUTPUTVOLTAGE

Figure 44. Poles and Zeros of Voltage Error Amplifier

GAIN

0dB

FREQUENCYfP1 fZ2 fP2fZ1

–20dB/DEC

–20dB/DEC

The following equations give the locations of the polesand zeros shown in Figure 44:

fZ1 1

2 CA RA (eq. 29)

(eq. 30)

(eq. 31)

(eq. 32)

fZ2 1

2 CFB RFB

fP1 1

2CA CB RFB

fP2 CA CB

2 RA CB CA

The expressions that follow compute the time constantsfor the poles and zeros in the system and are intended to yieldan optimal starting point for the design; some adjustmentsmay be necessary to account for PCB and componentparasitic effects (see the Tuning Procedure for ADP3208Dsection):

RE n RO AD RDS RL VRT

VID

(eq. 33)

2 L (1 (n D)) VRT

n CX RO VVID

TA CX (RO R) LX

RO

RO R

RX (eq. 34)

TB (RX R RO) CX (eq. 35)

TC

VRT L ADRDS

2fSW

VVID RE (eq. 36)

TD CX CZ RO

2

CX (RO R) CZ RO (eq. 37)

where: R’ is the PCB resistance from the bulk capacitors to theceramics and is approximately 0.4 m (assuming an 8−layermotherboard). RDS is the total low−side MOSFET for on resistance perphase. AD is 5.VRT is 1.25 V.LX is 150 pH for the six Panasonic SP capacitors.

The compensation values can be calculated as follows:

CA n RO TA

RE RB (eq. 38)

RA TC

CA (eq. 39)

CB TB

RB (eq. 40)

CFB TD

RA (eq. 41)

The standard values for these components are subject tothe tuning procedure described in the Tuning Procedure forADP3208D section.

CIN Selection and Input Current DI/DT ReductionIn continuous inductor−current mode, the source current

of the high−side MOSFET is approximately a square wavewith a duty ratio equal to n × VOUT/VIN and amplitude thatis one−nth of the maximum output current. To prevent largevoltage transients, use a low ESR input capacitor sized forthe maximum RMS current. The maximum RMS capacitorcurrent occurs at the lowest input voltage and is given by:

ICRMS D IO 1

n D 1

(eq. 42)

ICRMS 0.18 40 A 1

2 0.18 1 9.6 A

where IO is the output current.In a typical notebook system, the battery rail decoupling

is achieved by using MLC capacitors or a mixture of MLCcapacitors and bulk capacitors. In this example, the inputcapacitor bank is formed by eight pieces of 10 F, 25 V MLCcapacitors, with a ripple current rating of about 1.5 A each.

ADP3208D

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Selecting Thermal Monitor ComponentsTo monitor the temperature of a single−point hot spot, set

RTTSET1 equal to the NTC thermistor’s resistance at thealarm temperature. For example, if the alarm temperaturefor VRTT is 100°C and a Vishey thermistor(NTHS−0603N011003J) with a resistance of 100 k at25°C, or 6.8 k at 100°C, is used, the user can set RTTSET1equal to 6.8 k (the RTH1 at 100°C).

Figure 45. Single−Point Thermal Monitoring

ADP3208D

31

30TTSN

+

-

CTT

RTTSET1

RTH

VCC

5.0 V

VRTT

R

R

To monitor the temperature of multiple−point hot spots,use the configuration shown in Figure 46. If any of themonitored hot spots reaches the alarm temperature, theVRTT signal is asserted. The following calculation sets thealarm temperature:

RTTSET1

1

2

VFDVREF

12

VFDVREF

RTH1ALARMTEMPERATURE

(eq. 43)

where VFD is the forward drop voltage of the parallel diode.Because the forward current is very small, the forward

drop voltage is very low, that is, less than 100 mV. Assumingthe same conditions used for the single−point thermalmonitoring example, that is, an alarm temperature of 100°Cand use of an NTHS−0603N011003J Vishay thermistor;solving Equation 43 gives a RTTSET of 7.37 k, and theclosest standard resistor is 7.32 k (1%).

Figure 46. Multiple−Point Thermal Monitoring

ADP3208D31

30TTSN

+

-

CTT

RTTSET1

R TH1

VCC

5.0 V

VRTT

R

R

RTTSET2

R TH2

RTTSET3

R TH3

The number of hot spots monitored is not limited. Thealarm temperature of each hot spot can be individually set byusing different values for RTTSET1, RTTSET2, ... RTTSETn.

Tuning Procedure for ADP3208DSet Up and Test the Circuit

1. Build a circuit based on the compensation valuescomputed from the design spreadsheet.

2. Connect a dc load to the circuit.3. Turn on the ADP3208D and verify that it operates

properly.4. Check for jitter with no load and full load

conditions.

Set the DC Load Line1. Measure the output voltage with no load (VNL)

and verify that this voltage is within the specifiedtolerance range.

2. Measure the output voltage with a full load whenthe device is cold (VFLCOLD). Allow the board torun for ~10 minutes with a full load and thenmeasure the output when the device is hot(VFLHOT). If the difference between the twomeasured voltages is more than a few millivolts,adjust RCS2 using Equation 44.

RCS2(NEW) RCS2(OLD) VNL VFLCOLD

VNL VFLHOT (eq. 44)

3. Repeat Step 2 until no adjustment of RCS2 is needed.4. Compare the output voltage with no load to that

with a full load using 5 A steps. Compute the loadline slope for each change and then find theaverage to determine the overall load line slope(ROMEAS).

5. If the difference between ROMEAS and RO is morethan 0.05 m, use the following equation to adjustthe RPH values:

RPH(NEW) RPH(OLD) ROMEAS

RO (eq. 45)

6. Repeat Steps 4 and 5 until no adjustment of RPH isneeded. Once this is achieved, do not change RPH,RCS1, RCS2, or RTH for the rest of the procedure.

7. Measure the output ripple with no load and with afull load with scope, making sure both are withinthe specifications.

Set the AC Load Line1. Remove the dc load from the circuit and connect a

dynamic load.2. Connect the scope to the output voltage and set it

to dc coupling mode with a time scale of100 s/div.

3. Set the dynamic load for a transient step of about40 A at 1 kHz with 50% duty cycle.

4. Measure the output waveform (note that use of adc offset on the scope may be necessary to see thewaveform). Try to use a vertical scale of100 mV/div or finer.

ADP3208D

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5. The resulting waveform will be similar to thatshown in Figure 47. Use the horizontal cursors tomeasure VACDRP and VDCDRP, as shown in Figure47. Do not measure the undershoot or overshootthat occurs immediately after the step.

Figure 47. AC Loadline Waveform

VDCDRP

VACDRP

6. If the difference between VACDRP and VDCDRP ismore than a couple of millivolts, use Equation 46to adjust CCS. It may be necessary to try severalparallel values to obtain an adequate one becausethere are limited standard capacitor valuesavailable (it is a good idea to have locations fortwo capacitors in the layout for this reason).

CCS(NEW) CCS(OLD) VACDRP

VDCDRP (eq. 46)

7. Repeat Steps 5 and 6 until no adjustment of CCS isneeded. Once this is achieved, do not change CCSfor the rest of the procedure.

8. Set the dynamic load step to its maximum step size(but do not use a step size that is larger thanneeded) and verify that the output waveform issquare, meaning VACDRP and VDCDRP are equal.

9. Ensure that the load step slew rate and thepowerup slew rate are set to ~150 A/s to250 A/s (for example, a load step of 50 A shouldtake 200 ns to 300 ns) with no overshoot. Somedynamic loads have an excessive overshoot atpowerup if a minimum current is incorrectly set(this is an issue if a VTT tool is in use).

Set the Initial Transient1. With the dynamic load set at its maximum step

size, expand the scope time scale to 2 s/div to5 s/div. This results in a waveform that may havetwo overshoots and one minor undershoot beforeachieving the final desired value after VDROOP(see Figure 48).

Figure 48. Transient Setting Waveform, Load Step

VDROOP

VTRAN1VTRAN2

2. If both overshoots are larger than desired, try thefollowing adjustments in the order shown.a. Increase the resistance of the ramp resistor(RRAMP) by 25%.b. For VTRAN1, increase CB or increase theswitching frequency.c. For VTRAN2, increase RA by 25% and decreaseCA by 25%.If these adjustments do not change the response, itis because the system is limited by the outputdecoupling. Check the output response and theswitching nodes each time a change is made toensure that the output decoupling is stable.

3. For load release (see Figure 49), if VTRANREL islarger than the value specified by IMVP−6+, agreater percentage of output capacitance is needed.Either increase the capacitance directly or decreasethe inductor values. (If inductors are changed,however, it will be necessary to redesign thecircuit using the information from the spreadsheetand to repeat all tuning guide procedures).

Figure 49. Transient Setting Waveform, Load Release

VDROOP

VTRANREL

ADP3208D

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Layout and Component PlacementThe following guidelines are recommended for optimal

performance of a switching regulator in a PC system.

General Recommendations1. 1. For best results, use a PCB of four or more

layers. This should provide the needed versatilityfor control circuitry interconnections with optimalplacement; power planes for ground, input, andoutput; and wide interconnection traces in the restof the power delivery current paths. Keep in mindthat each square unit of 1 oz copper trace has aresistance of ~0.53 m at room temperature.

2. When high currents must be routed between PCBlayers, vias should be used liberally to createseveral parallel current paths so that the resistanceand inductance introduced by these current paths isminimized and the via current rating is notexceeded.

3. If critical signal lines (including the output voltagesense lines of the ADP3208D) must cross throughpower circuitry, it is best if a signal ground planecan be interposed between those signal lines andthe traces of the power circuitry. This serves as ashield to minimize noise injection into the signalsat the expense of increasing signal ground noise.

4. An analog ground plane should be used aroundand under the ADP3208D for referencing thecomponents associated with the controller. Thisplane should be tied to the nearest ground of theoutput decoupling capacitor, but should not be tiedto any other power circuitry to prevent powercurrents from flowing into the plane.

5. The components around the ADP3208D should belocated close to the controller with short traces.The most important traces to keep short and awayfrom other traces are those to the FB and CSSUMpins. Refer to Figure 42 for more details on thelayout for the CSSUM node.

6. The output capacitors should be connected as closeas possible to the load (or connector) that receivesthe power (for example, a microprocessor core). Ifthe load is distributed, the capacitors should alsobe distributed and generally placed in greaterproportion where the load is more dynamic.

7. Avoid crossing signal lines over the switchingpower path loop, as described in the PowerCircuitry section.

Power Circuitry1. The switching power path on the PCB should be

routed to encompass the shortest possible length tominimize radiated switching noise energy (that is,EMI) and conduction losses in the board. Failureto take proper precautions often results in EMI

problems for the entire PC system as well asnoise−related operational problems in thepower−converter control circuitry. The switchingpower path is the loop formed by the current paththrough the input capacitors and the powerMOSFETs, including all interconnecting PCBtraces and planes. The use of short, wideinterconnection traces is especially critical in thispath for two reasons: it minimizes the inductancein the switching loop, which can cause high energyringing, and it accommodates the high currentdemand with minimal voltage loss.

2. When a power−dissipating component (forexample, a power MOSFET) is soldered to a PCB,the liberal use of vias, both directly on themounting pad and immediately surrounding it, isrecommended. Two important reasons for this areimproved current rating through the vias andimproved thermal performance from vias extendedto the opposite side of the PCB, where a plane canmore readily transfer heat to the surrounding air.To achieve optimal thermal dissipation, mirror thepad configurations used to heat sink the MOSFETson the opposite side of the PCB. In addition,improvements in thermal performance can beobtained using the largest possible pad area.

3. The output power path should also be routed toencompass a short distance. The output power pathis formed by the current path through the inductor,the output capacitors, and the load.

4. For best EMI containment, a solid power groundplane should be used as one of the inner layers andextended under all power components.

Signal Circuitry1. The output voltage is sensed and regulated

between the FB and FBRTN pins, and the traces ofthese pins should be connected to the signalground of the load. To avoid differential modenoise pickup in the sensed signal, the loop areashould be as small as possible. Therefore, the FBand FBRTN traces should be routed adjacent toeach other, atop the power ground plane, and backto the controller.

2. The feedback traces from the switch nodes shouldbe connected as close as possible to the inductor.The CSREF signal should be Kelvin connected tothe center point of the copper bar, which is theVCORE common node for the inductors of all thephases.

3. On the back of the ADP3208D package, there is ametal pad that can be used to heat sink the device.Therefore, running vias under the ADP3208D isnot recommended because the metal pad maycause shorting between vias.

ADP3208D

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ORDERING INFORMATION

Device Temperature Range Package Package Option Shipping†

ADP3208DJCPZ−RL −10°C to 100°C 48−Lead Frame Chip ScalePackage [LFCSP_VQ]

CP−48−1 2500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011/D.

*The “Z” suffix indicates Pb−Free part.

All brand names and product names appearing in this document are registered trademarks or trademarks of their respective holders.

LFCSP48 7x7, 0.5PCASE 932AD−01

ISSUE ADATE 23 JAN 2009

SCALE 2:1

SEATING

NOTE 4

M

0.20 C

(A3)

A

A1

D2

b

1

13

25

48

E2

48X

4X

L48X

BOTTOM VIEW

INDICATOR

TOP VIEW

SIDE VIEW

D AB

E

0.20 C

PIN ONEREFERENCE

0.10 C

0.08 C

C

37

eA0.10 BC

0.05 C

NOTES:1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.2. CONTROLLING DIMENSIONS: MILLIMETERS.3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN0.15 AND 0.30mm FROM THE TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSEDPAD AS WELL AS THE TERMINALS.

DIM MIN MAXMILLIMETERS

A 0.80 1.00A1 0.00 0.05A3 0.20 REFb 0.18 0.30D 7.00 BSC

D2 4.95 5.25E 7.00 BSC

5.25E2 4.95e 0.50 BSCH −−− 12K 0.20 −−−

PLANE

DIMENSIONS: MILLIMETERS

0.50

5.14

0.28

5.14

48X

0.6348X

7.30

7.30

*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

1

L 0.30 0.50M −−− 0.60

D1 6.75 BSC

E1 6.75 BSC

D1

E1

H

PITCH

PACKAGEOUTLINE

PIN 1

M4X

K

°

NOTE 3

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.

98AON26683DDOCUMENT NUMBER:

DESCRIPTION:

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