CA - IV - D&IF - 1

HUMBOLDT-UNIVERSITÄT ZU BERLININSTITUT FÜR INFORMATIK

COMPUTER ARCHITECTURELecture 4

DATA AND INSTRUCTION FORMATS,ADDRESSING METHODS

AND MACHINE PROGRAMMING CONCEPTS

Sommersemester 2002

Leitung: Prof. Dr. Miroslaw Malek

www.informatik.hu-berlin.de/rok/ca

CA - IV - D&IF - 2

TYPES OF INFORMATION, DATA AND INSTRUCTION FORMATS, ADDRESSING METHODS,

AND MACHINE PROGRAMMING CONCEPTS

INFORMATION TYPES

FORMATS (PDP-11, PowerPC, MOTOROLA 68000, Pentium examples)

ADDRESSES

ADDRESSING MODES

SIMPLE I/O PROGRAMMING

PUSHDOWN STACK vs. REGISTER ORGANIZATION

CA - IV - D&IF - 3

SOME BASIC INFORMATION TYPESInformation

Data Instructions

Numbers

Nonnumeric Data

Fixed-point Floating-point

Binary DecimalDecimalBinary

CA - IV - D&IF - 4

DATA FORMATS

In selecting the number representation the following factors should be taken into account.

1. TYPES of NUMBERS to be represented e.g., integers, real numbers, complex numbers

2. The RANGE of VALUES to be encountered

3. The PRECISION of the NUMBER

4. THE COST of HARDWARE required to store and process the numbers

ASCII – American Standard Committee on Information Interchange (7bits)EBCDIC – Extended Binary-Coded Decimal Interchange Code (8 bits)

CA - IV - D&IF - 5

INSTRUCTION FORMATS

In selecting the instruction format(s) the following factors should be considered.

1. The number of instructions to be represented.

2. The addressability and addressing modes.

3. The ease of decoding.

4. Type of instruction field (fixed or variable)

5. The cost of hardware required to decodeand execute instructions.

OP-CODE ADDRESS(ES)

0-, 1-, 2- or 3-addressable instruction formats

CA - IV - D&IF - 6

INSTRUCTION FORMATSOP-CODE

1-ADDRESS 10 BITS 3 BITS 3 BITS

OP-CODE

2-ADDRESS 4 BITS 3 BITS 3 BITS

SRC DST

BRANCH

OP-CODE OFFSET

8 BITS 8 BITS

BRANCH ADDRESS = + 2 x OFFSET

DATA FORMAT16 BITS

2' s COMPLEMENT

8 BITS 8 BITS

CHARACTER CHARACTER

[ UPDATED PC ]

INSTRUCTION AND DATA FORMATS FOR PDP - 11

Mode Rn

Mode Rn Mode Rn

3 BITS 3 BITS

CA - IV - D&IF - 7

BASIC INSTRUCTION FORMAT& PDP-11 ADDRESS FIELD

OP CODE ADDRESS

ADDRESS

MODE Rn

15 6 5 0

MODE 5 4 3 2 1 0

RN

(RN)+

-(RN)

X(RN)

Register

Autoinc.

Autodec.

Index

(0)

(2)

(4)

(6)

0 0 0 0 0 0

0 1 0 0 0 1

1 0 0

1 1 0 1 1 1

R 0

R 1

R 7

If "1" Indirect

CA - IV - D&IF - 8

INSTRUCTION FORMATS for PowerPC0 6 11 16 31

OP code RD/RS RA I16/X(1)

0 6 11 16 31

OP code RD/RS RA Sub OP code(2) RB OE Rc

0 6 11 16 31

OP code CRD RB I16(3) OPc

0 6 11 16 31

OP code CRD RA(4) OPc

9

9 21

RB 0

0 6 11 16 31

OP code crbD crbA(5)

21

crbB

0 6 11 16 31

OP code RS RA(6)

21

SH MB ME

Sub OP code

Sub OP code

RD – Destination Register, RS – Source Register, RA – Additional Register, I16 – Immediate Operand, X –offset value, RB – third Register, CR – Condition Register, XER – Exeption Register, OE/Rc – setting flags, MB – Mask Begin, ME – Mask End, SH – Shift/Rotate, crb – Conditional Register Bit, CDR – Comparing field

0

Rc

26

21 22

Two operand general instruction format

Three operand general instruction format

Instruction formatfor comparing I

Instruction formatfor comparing II

Instruction format forlogical operations with the use of crb

Instruction format for Shift/Rotate operations

CA - IV - D&IF - 9

DATA FORMAT for PowerPC

0 8 16 24 6332 40 48 56

Byte 0 Byte 1 Byte 7

Half word 0 Half word 2

Word 0 Word 4

Double word 0

•The big-endian ordering is default mode, the little-endian mode is also possible.

CA - IV - D&IF - 10

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INSTRUCTION FORMAT for MOTOROLA 68000

Operation Word (First Word specifies Operation and Modes)

Immediate Operand (If Any, One or Two Words)

Source Effective Address Extension (If Any, One or Two Words)

Destination Effective Address Extension (If Any, One or Two Words)

SINGLE - EFFECTIVE - ADDRESSINSTRUCTION OPERATION WORD

GENERAL FORMAT

X X X X X X X X X X Mode RegisterEffective Address

CA - IV - D&IF - 11

PENTIUM INTEGER DATA FORMATSByte Signed Integer

7 6 0Sign

Word Signed Integer

15 14 0Sign

Doubleword Signed Integer

31 30 0Sign

Byte Unsigned Integer

7 0Word Unsigned Integer

15 0Doubleword Unsigned Integer

31 0

BCDXBCDXBCDX ...7 4 3 0

BCD Integers

BCDBCDBCDBCDBCDBCD ...Packed BCD Integers

Near Pointer

31 0Offset or Linear Address

Far Pointer or Logical Address

47 32 31 0OffsetSegment Selector

7 4 3 0

CA - IV - D&IF - 12

PENTIUM GENERAL INSTRUCTION FORMAT

Opcode

Smaller encoding fields can be defined within the primary opcode. These fields define the direction of the operation, the size of displace-ments, the register encoding, condition codes, or sign extension. The encoding of fields in the opcode depends on the class of operation.ModR/M and SIB Bytes

• The mod and the r/m form 32 possible values: 8 registers and 24 addressing modes.• The reg/opcode field is either a register number or 3 more opcode bits.

It’s is specified in the primary opcode.• The r/m field can specify a register as an operand or can be combined

with the mod field to encode an addressing mode.Certain encodings of the ModR/M byte require a second addressing byte, the SIB byte, to fully specify the addressing form. The base-plus-index and scale-plus-index forms of 32-bit addressing require the SIB byte. The SIB byte includes the following fields:• The scale field specifies the scale factor.• The index field specifies the register number of the index register.• The base field specifies the register number of the base register.

InstructionPrefixes Opcode ModR/M SIB Displacement Immediate

Up to fourprefixes of1 byte each(optional)

1 or 2 byte 1 byte (ifrequired)

1 byte (ifrequired)

Addressdisplacement1, 2 or 4 bytesor none

Immediate data1, 2, or 4 bytesor none

7 6 5 3 2 0Mod Reg/

OpcodeR/M

7 6 5 3 2 0Scale Index Base

CA - IV - D&IF - 13

NUMBER OF ADDRESSESONE - AND TWO - ADDRESS MACHINES

Instruction Comments

LOAD AMULTIPLY BSTORE TLOAD CMULTIPLY CADD TSTORE X

Transfer A to accumulator ACAC AC x BTransfer AC to memory location TTransfer C to accumulator ACAC AC x CAC AC + TTransfer result to memory location X

Instruction Comments

MOVE A, TMULTIPLY B,TMOVE C, XMULTIPLY C, XADD T,X

T AT T x BX CX X x CX X + T

X = A x B + C x C

CA - IV - D&IF - 14

THREE - AND ZERO-ADDRESS MACHINES

Instruction Comments

MULTIPLY A, B,T

MULTIPLY C, C, XADD X, T,X

T A x B

X C x CX X + T

Instruction Comments

PUSH APUSH BMULTIPLYPUSH CPUSH CMULTIPLYADDPOP X

Transfer A to top of stackTransfer B to top of stackRemove A, B from stack and replace by A x BTransfer C to top of stackTransfer second copy of C to top of stackRemove C, C from stack and replace by C x CRemove CxC, AxB from stack, replace by their sumTransfer result from top of stack to X

X = A x B + C x C

CA - IV - D&IF - 15

ADDRESSING METHODS

ABSOLUTE (DIRECT) ADRESSING - The address of operand is given explicity as part of the instruction

IMPLIED ADDRESSING - The address is implied by the instruction (e.g.,in one-address machine, the address

of the second operand is implied as being accumulator)

IMMEDIATE ADDRESSING - The operand is given explicitly as the instruction. No memory

access is required. Also operand could follow immediately after the instruction.

INDIRECT ADDRESSING - The effective address of the operand is in the register or main memory location

whose address appears in the instruction. It can have more than one level.

INDEXED ADDRESSING- The effective address (EA) of the operand is generated by adding an index register

value (X) to the direct address (DA)- EA = X + DA

BASE ADDRESSING - The effective address of the operand is generated by adding base register value (B)

to the address- EA = B + DA

CA - IV - D&IF - 16

SELF-RELATIVE ADDRESSING - Effective address is a sum of a direct address and a program counter contents (PC).

EA = DA + PC

AUGMENTED ADDRESSING - Effective address is a concatenation of the contents of the augmented address

register (AAR) and direct address.

EA = AAR || DA

(AAR often specifies a page and DA is an address within this particular page)

BLOCK ADDRESSING - Address of the first word in the block is given. Length of the block is usually specified

in the instruction; or also the last address can be given; or special end-of-blockcharacter can be given; or blocks may have fixed length. Very useful in the secondary storage management.

CA - IV - D&IF - 17

PowerPC Family - Consortium of Apple, IBM and Motorola (announced in 1991)

CPU Speed* Instructions L1 cache601 60-120 MHz 3 per cycle 32 KB603 75-160 MHz 2 per cycle 2x8 KB603e 100-300 MHz 2 per cycle 2x16 KB604 120-180 MHz 4 per cycle 2x16 KB604e 150-350 MHz 4 per cycle 2x32 KBG3 200-450 MHz 3 per cycle 2x32 KB 8-10x bus multiplier750CX 366-466 MHz 3 per cycle 2x32 KB+ 8x bus multiplier750CXe 400-700 MHz 3 per cycle 2x32 KB+ 10x bus multiplierG4 350-600 MHz 19 per cycle** 2x32 KB plus 2 MB L2 cache7410 466-533 MHz 20 per cycle** 2x32 KB plus 1 MB L2 cache7450 667-733 MHz unknown 2x32 KB+ 256K L2+2 MB L3

cache* as used in Apple ** AltiVec can do up to 16 simultaneous calculations + integrated 256 KB level 2

cache

CA - IV - D&IF - 18

GENERAL METHODS OF ADDRESSING OF PowerPC

IMMEDIATE INDEX ADDRESSING MODE-The effective address of the operand is the sum of the contents of a register named in

the instruction and a signed 16-bit offset, X, that is also given in the instruction. In assembly language, the operand is specified in the form X(Rsrc), and the effective address is computed as Aeff = X + [Rsrc], where Rsrc is any of the general purpose registers R1 through R32.

REGISTER INDEX ADDRESSING MODE- The effective address of the operand is the sum of the contents of two general

purpose registers named in the instruction. The effective address is computed as Aeff = [Ri] + [Rj]. If zero is used in place of Ri, the value 0 is used instead of the contents of R0. In this case the effective address is [Rj].

CA - IV - D&IF - 19

METHODS OF ADDRESSING MODES FOR BRANCH INSTRUCTIONS OF PowerPC

ABSOLUTE- The target address is given in the instruction

RELATIVE- The distance between the branch instruction and the target address is given in the

instruction

REGISTER INDIRECT- The target address is the contents of a register specified by the instruction OP code.

Instructions that use this mode are called branch to register, for simplicity.

CA - IV - D&IF - 20

PDP-11 ADDRESSING MODESB5B4B3 Decim. NAME SYNTAX MEANING

000 0 REGISTER Rn EA = Rn(THAT IS,OPERAND = [Rn ])

010 2 AUTOINCREMENT ( Rn )+ EA = [Rn ];INCREMENT Rn

100 4 AUTODECREMENT - ( Rn ) DECREMENT EA = [Rn

110 6 INDEX X( Rn ) FETCH X; INCREMENT PCEA = X + [Rn];

001 1 REGISTERINDIRECT

@Rn EA = [ Rn];

011 3 AUTOINCREMENTINDIRECT

@( R n )+ EA = [[Rn ]];INCREMENT Rn;

101 5 AUTODECREMENTINDIRECT

@-( R n ) DECREMENT Rn;EA = [[Rn ]];

111 7 INDEX INDIRECT @X(R n ) FETCH X;INCREMENT PCEA = [X+[Rn]]

EA = effective address[L] = contents of the location whose address is L (the address L can be that of a main

memory location or a register Rn)[[L]] = L points to a location where the effective address can be found

];

CA - IV - D&IF - 21

PDP-11 ADDRESSING MODES WITH Rn = PC

010 2 IMMEDIATE(AUTOINCREMENT)

#N EA = [PC];Increment PC (That is, operand N follows the intstruction)

011 3 A BSOLUTE(AUTOINCREMENTINDIRECT)

@#A EA = [[PC]];Increment PC (that is, EA, which is A, follows the intstr.)

110 6 RELATIVE( INDEX )

A F ETCH X;INCREMENT PC;EA = X + [PC](THAT IS, EA IS A,IT IS SPECIFIEDRELATIVE TO PC BY DISPLACEMENT X INWORD FOLLOWINGINSTRUCTION)

111 7 RELATIVEINDIRECT(INDEX INDIRECT)

@A FETCH X;INCREMENT PC;EA = [X+[PC]];(THAT IS THE ADDRESSA OF LOCATIONCONTAINING EA ISSPECIFIED RELATIVETO [PC] BYDISPLACEMENT X INWORD FOLLOWINGINSTRUCTION)

EA = effective address[L] = contents of the location whose address is L (the address L can be that of a main

memory location or a register Rn or PC)[[L]] = L points to a location where the effective address can be found

B5B4B3 Decim. NAME SYNTAX MEANING

CA - IV - D&IF - 22

THE 68000 MICROPROCESSORADDRESSING MODES & INSTRUCTIONS

68000, 68020, 68030, 68040 & 68060 (two architectures)

•16-bit external & 32-bit internal - (16 data, 24 address) 64 pins(other models have 32 data and 32 address)•32, 16 & 8 bit words (operands)

31 16 15 7 0

byte

word

long word

8 DATA REGISTERS, 8 ADDRESS REGISTERS (A USER STACK POINTER, SUPERVISOR STACK POINTER) PROGRAM COUNTER STATUS REGISTER (supervisor or trace mode select, interrupt mask, X extended, N negative, Z zero, V overflow, C carry)

byte 0 byte 1byte 2 byte 3

byte 224 - 2 byte 224 - 1

long word 0

long word 4

02

2 24 - 2

CA - IV - D&IF - 23

PENTIUM ADDRESSING MODES

Process or Word and Bus Widths of some16, 16/32 and 64/32 Bit CISC Microprocessors

1) Immediate Operands2) I/O Port Addressing3) Register Operands4) Memory Operands