addr
DESCRIPTION
mux. ADD. ADD. +4. shift 2. BRANCH CTRL. rs. PC. R1. R Data 1. zero. addr. rt. R2. ALU. addr. instr. R Data 2. mux. mux. r data. rd. WR. INSTR MEM. w data. W Data. DATA MEM. Single Cycle Datapath. immed. ALU CTRL. sign extend. 16. 32. op. Multicycle Datapath. - PowerPoint PPT PresentationTRANSCRIPT
![Page 1: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/1.jpg)
PC addr
instr
INSTR MEM
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
DATA MEM
ALU CTRLALU CTRL
rs
rt
op
+4
shift 2
zero
BRANCH CTRL
mux
sign extendimmed
16 32
ADD
ADD
Single Cycle
Datapath
mux
mux
addr
w data
r datard
![Page 2: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/2.jpg)
PC
addr
REGISTERS
MEMORY
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
data
ALU CTRLALU CTRL
rs
rt
rd
fctnop shamt
Multicycle Datapath
A
B
w data
immed sign extend
shift 2
+4
IR
MR
z
alu out
shift 2jump addr
fetch
decode
execute (1..3)
![Page 3: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/3.jpg)
PC
addr
REGISTERS
MEMORY
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
data
CONTROLCONTROL
rs
rt
rd
fctnop shamt
Multicycle with Exception/Interrupt Handling
A
B
w data
immed sign extend
shift 2
+4
IR
MR
zero
alu out
shift 2jump addr
EPC
CAUSE
PC - 4
handler addr
00
01
10
11
to?
overflow
to?
![Page 4: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/4.jpg)
Pipelined Datapath
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
IF ID EX MEM WB
![Page 5: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/5.jpg)
add rd, rt, rs: Fetch
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
Instruction Fetch: Load IR, PC = PC + 4 IF Register
Contains IR and PC, and other values
![Page 6: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/6.jpg)
add rd, rt, rs: Decode
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
Instruction Decode: Load data1, data2 into A, B (part of ID)
ID register contains A, B, and other values
![Page 7: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/7.jpg)
add rd, rt, rs: Execute
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
Execute: sum of A, B into ALUout (part of EX)
![Page 8: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/8.jpg)
add rd, rt, rs: MEM
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
MEM: (no memory access) save ALU result in MEM
![Page 9: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/9.jpg)
add rd, rt, rs: WB
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
Write Back: write sum to register rd
![Page 10: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/10.jpg)
sw rt, offset(rs): Fetch
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
![Page 11: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/11.jpg)
sw rt, offset(rs): Decode
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
ID gets rs, rt, and immed+sign ext
![Page 12: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/12.jpg)
sw rt, offset(rs): Execute
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
EX gets rs+offset, and rt
![Page 13: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/13.jpg)
sw rt, offset(rs): MEM
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
Write Data Memory [address] with rt value; nothing of interest in WD
![Page 14: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/14.jpg)
sw rt, offset(rs): WB
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
Registers not written in this instruction
![Page 15: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/15.jpg)
A program fragment with 6 instructions
1. add r1, r2, r3
2. sw r4, 2232 ( r5 )
3. addi r6, 55
4. lw r7, 1001 (r8)
5. bneq r7, r6, -3
6. add r1, r7, r0
![Page 16: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/16.jpg)
A program fragment with 6 instructions
1. add r1, r2, r3
2. sw r4, 2232 ( r5 )
3. addi r6, 55
4. lw r7, 1001 (r8)
5. slti r7, r6, -3
6. add r1, r7, r0
![Page 17: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/17.jpg)
Six instructions 1,2,3,4,5,6: Step 1
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
Fetch 1
![Page 18: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/18.jpg)
Six instructions 1,2,3,4,5,6: Step 2
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
Fetch 2 Decode 1
![Page 19: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/19.jpg)
Six instructions 1,2,3,4,5,6: Step 3
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
Fetch 3 Decode 2 Execute 1
![Page 20: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/20.jpg)
Six instructions 1,2,3,4,5,6: Step 4
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
Fetch 4 Decode 3 Execute 2 Mem 1
![Page 21: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/21.jpg)
Six instructions 1,2,3,4,5,6: Step 5
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
Fetch 5 Decode 4 Execute 3
WB 1 (add)
Mem 2 (sw)
![Page 22: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/22.jpg)
Six instructions 1,2,3,4,5,6: Step 6
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
Fetch 6 Decode 5Execute 4 Mem 3
(addi)
WB 2 (sw: no write)
![Page 23: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/23.jpg)
Six instructions 1,2,3,4,5,6: Step 7
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
Decode 6 Execute 5 Mem 4 (lw)
WB 3 (addi)
![Page 24: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/24.jpg)
Six instructions 1,2,3,4,5,6: Step 8
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
Execute 6 Mem 5 (slti)
WB 4 (lw)
![Page 25: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/25.jpg)
Six instructions 1,2,3,4,5,6: Step 9
PC
Instruction Memory
addr
out
Registers
read1
read2
write
w data
data1
data2
sign extend
add+4
shift
add
ALU
Data Memory
addr
w data
r data
mux
mux
mux
Mem 6 (add)
WB 5 (slti)
![Page 26: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/26.jpg)
PC
addr
REGISTERS
MEMORY
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
data
ALU CTRLALU CTRL
rs
rt
rd
fctnop shamt
add rd, rs, rt
fetch: load ir, pc=pc+4
decode
execute
A
B
w data
immed sign extend
shift 2
+4
IR
MR
z
alu out
shift 2jump addr
![Page 27: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/27.jpg)
PC
addr
REGISTERS
MEMORY
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
data
ALU CTRLALU CTRL
rs
rt
rd
fctnop shamt
Multicycle Datapath
A
B
w data
immed sign extend
shift 2
+4
IR
MR
z
alu out
shift 2jump addr
fetch
decode
execute
![Page 28: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/28.jpg)
PC
addr
REGISTERS
MEMORY
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
data
ALU CTRLALU CTRL
rs
rt
rd
fctnop shamt
add rd, rs, rt
fetch
decode:load A,B registers
execute
A
B
w data
immed sign extend
shift 2
+4
IR
MR
z
alu out
shift 2jump addr
![Page 29: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/29.jpg)
PC
addr
REGISTERS
MEMORY
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
data
ALU CTRLALU CTRL
rs
rt
rd
fctnop shamt
add rd, rs, rt
fetch
decode
execute (2 cycles) load alu out; load register
A
B
w data
immed sign extend
shift 2
+4
IR
MR
z
alu out
shift 2jump addr
![Page 30: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/30.jpg)
PC
addr
REGISTERS
MEMORY
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
data
ALU CTRLALU CTRL
rs
rt
rd
fctnop shamt
bne rs, rt, addr
fetch: load IR, pc=pc+4
decode
execute
A
B
w data
immed sign extend
shift 2
+4
IR
MR
z
alu out
shift 2jump addr
![Page 31: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/31.jpg)
PC
addr
REGISTERS
MEMORY
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
data
ALU CTRLALU CTRL
rs
rt
rd
fctnop shamt
bne rs, rt, addr
fetch
decode: load A B, aluout = immediate (extendx2)+pc
execute
A
B
w data
immed sign extend
shift 2
+4
IR
MR
z
alu out
shift 2jump addr
![Page 32: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/32.jpg)
PC
addr
REGISTERS
MEMORY
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
data
ALU CTRLALU CTRL
rs
rt
rd
fctnop shamt
bne rs, rt, addr
fetch:
decode:
execute: (1 cycle) compare A, B (holding rs, rt); if neq, load pc with aluout (holding branch addr)
A
B
w data
immed sign extend
shift 2
+4
IR
MR
z
alu out
shift 2jump addr
![Page 33: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/33.jpg)
PC
addr
REGISTERS
MEMORY
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
data
ALU CTRLALU CTRL
rs
rt
rd
fctnop shamt
lw rt, offset ( rs)
fetch: load IR, pc=pc+4
decode
execute
A
B
w data
immed sign extend
shift 2
+4
IR
MR
z
alu out
shift 2jump addr
![Page 34: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/34.jpg)
PC
addr
REGISTERS
MEMORY
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
data
ALU CTRLALU CTRL
rs
rt
rd
fctnop shamt
lw rt, offset ( rs)
fetch
decode: load A B; offset is ready
execute
A
B
w data
immed sign extend
shift 2
+4
IR
MR
z
alu out
shift 2jump addr
![Page 35: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/35.jpg)
PC
addr
REGISTERS
MEMORY
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
data
ALU CTRLALU CTRL
rs
rt
rd
fctnop shamt
lw rt, offset ( rs)
fetch
decode
execute: (3 cycles): load aluout with addr, load mr with data, load register rt
A
B
w data
immed sign extend
shift 2
+4
IR
MR
z
alu out
shift 2jump addr
![Page 36: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/36.jpg)
PC
addr
REGISTERS
MEMORY
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
data
ALU CTRLALU CTRL
rs
rt
rd
fctnop shamt
Multicycle Datapath
A
B
w data
immed sign extend
shift 2
+4
IR
MR
z
alu out
shift 2jump addr
Try these:
sw rt, off(rs)
j addr
andi rd,rs,rt
![Page 37: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/37.jpg)
PC
addr
REGISTERS
MEMORY
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
data
ALU CTRLALU CTRL
rs
rt
rd
fctnop shamt
Multicycle Datapath
A
B
w data
immed sign extend
shift 2
+4
IR
MR
z
alu out
![Page 38: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/38.jpg)
PC addr
instr
INSTR MEM
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
DATA MEM
ALU CTRLALU CTRL
rs
rt
rd
fctn
op
shamt
R-Format: add, slt, sll
![Page 39: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/39.jpg)
PC addr
instr
INSTR MEM
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
DATA MEM
ALU CTRLALU CTRL
rs
rt
op
+4
shift 2
zero
BRANCH CTRL
mux
sign extendimmed
16 32
ADD
ADD
I-Format bne
![Page 40: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/40.jpg)
PC addr
instr
INSTR MEM
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
DATA MEM
ALU CTRLALU CTRL
rs
rt
op
zero
sign extendimmed
16 32
I-Format lw, sw
addr
W Data
mux
R Data
![Page 41: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/41.jpg)
PC addr
instr
INSTR MEM
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
DATA MEM
ALU CTRLALU CTRL
op
+4
shift 2
zero
BRANCH CTRL
mux
ADD
ADD
J-Format
address
![Page 42: addr](https://reader035.vdocuments.us/reader035/viewer/2022062423/5681449a550346895db14595/html5/thumbnails/42.jpg)
PC
addr
REGISTERS
MEMORY
R1
R2
WR
W Data
R Data 1
R Data 2
ALU
data
ALU CTRLALU CTRL
rs
rt
rd
fctnop shamt
Multicycle Datapath
A
B
w data
immed sign extend
shift 2
+4
IR
MR
z
alu out
shift 2jump addr
fetch
decode
execute