adc_1

Design of a Very Low Power SAR Analog to Digital Converter

Giulia Beanato

Master Thesis Lausanne, 14 August 2009

Microelectronic Systems Laboratory (LSM)

Supervisor: Prof. Yusuf Leblebici

Coadvisors: Armin Tajalli

Vahid Majidzadeh

Design of a Very Low Power SAR ADC

II


Abstract

Nowadays, a larger percentage of mixed-signal applications require energy limited

system solutions. Analog to Digital Converters (ADCs) are critical component in

most of such systems, hence the stringent requirements on energy consumption

requests the ADC design to be low power. Among various ADC architectures, we

chose to implement a Successive Approximation Register (SAR) ADC that is one of

the best suited for low power. We target a resolution of 8-bit and a power

consumption of few micro Watts. The SAR ADC is implemented in UMC 90nm

CMOS technology with a power supply of 1.2V.

The use of a differential input structure allows avoiding common-mode errors. A

comparison between different DAC topologies led us to choose a binary weighted

switched capacitor array topology for the D/A converter to have less power

consumption. A new approach using Source-Coupled Logic operating in subthreshold

regime (STSCL) is used in order to implement an ultra low power comparator. The

comparator has two preamplifier stages and a latch, it can discriminate voltage

differences as small as 2mV, half of the LSB. The SAR control logic is implemented

with a top down approach, starting from the VHDL code and finally obtaining the

layout of the block. Front end Track and Hold circuit is avoided to decrease the power

consumed at the price of a lower conversion rate.

The simulations show that the converter has no missing codes working with a bias

current of 50nA and sampling at a frequency of 1.4 kS/s. Adding a Track and Hold

the sampling frequency would increase considerably without deteriorating the non-

linearity of the system over 1LSB. The power consumption for this sampling

frequency remains in the order 14uW.

III


Contents Abstract ....................................................................................................................... III Contents ...................................................................................................................... IV List of Figures .............................................................................................................. V List of Tables .............................................................................................................. VI

1 Introduction...................................................................................................- 1 - 1.1 Thesis Organization ..............................................................................- 1 -

2 ADC Architectures........................................................................................- 2 - 2.1 Topologies Comparison ........................................................................- 3 - 2.2 Successive Approximation Register ADC............................................- 6 -

3 Behavioural Model........................................................................................- 8 - 3.1 ADC Parameters ...................................................................................- 8 - 3.2 Simulink Model ....................................................................................- 9 - 3.3 Simulations Results.............................................................................- 12 -

4 SAR ADC Building Blocks ........................................................................- 13 - 4.1 90nm CMOS Technology ...................................................................- 13 - 4.2 Fully Differential vs. Single Ended ....................................................- 14 - 4.3 Digital to Analog Converter DAC Topologies ...................................- 15 -

4.3.1 Binary Weighted Switched Capacitor Array DAC.....................- 15 - 4.3.2 Junction-Splitting Capacitor Array .............................................- 17 - 4.3.3 Energy Efficient Charge-Redistribution DAC............................- 19 - 4.3.4 Serial Charge Redistribution D/A Converter..............................- 20 - 4.3.5 Circuit Choice and Design ..........................................................- 21 -

4.4 Comparator .........................................................................................- 24 - 4.4.1 Subthreshold Source-Coupled Logic ..........................................- 25 - 4.4.2 Design Approach ........................................................................- 26 - 4.4.3 Matching Considerations ............................................................- 28 - 4.4.4 Circuit implementation ...............................................................- 30 -

4.5 Level shifter ........................................................................................- 33 - 4.6 Track and Hold ...................................................................................- 33 - 4.7 Delay Cell ...........................................................................................- 35 - 4.8 SAR Logic ..........................................................................................- 36 -

4.8.1 VHDL Code ................................................................................- 36 - 4.8.2 Synthesis .....................................................................................- 41 - 4.8.3 Place & Route .............................................................................- 44 -

5 Experimental Results ..................................................................................- 45 - 5.1 Comparator .........................................................................................- 45 - 5.2 Mismatch effects on ADC parameters................................................- 47 - 5.3 Signal to Noise Ratio ..........................................................................- 48 - 5.4 DAC ....................................................................................................- 49 - 5.5 Input/Output Characteristic.................................................................- 50 - 5.6 Current and power considerations ......................................................- 52 -

6 Conclusions.................................................................................................- 55 - 6.1 Future work.........................................................................................- 56 -

References...............................................................................................................- 57 -

IV


Appendix I……………………………….…………………………………………-60- Appendix II……………………………….…………….……...…………………..-63- Appendix III……………………………………...…..…………………………….-67- Appendix IV………………….…………………………………………………….-70- Appendix V…………….………….……………………………………………….-71- Appendix VI…………….………………………………………………………….-75-

List of Figures Figure 1: Analog-Digital Conversion .......................................................................- 2 - Figure 2: Flash ADC Block Diagram .......................................................................- 3 - Figure 3: SAR ADC Block Diagram ........................................................................- 4 - Figure 4: Delta Sigma ADC Block Diagram ............................................................- 4 - Figure 5: Folding and Interpolating ADC Block Diagram .......................................- 5 - Figure 6: Simplified N-bit SAR ADC architecture...................................................- 6 - Figure 7: SAR operation (4-bit ADC example). .......................................................- 7 - Figure 8: input/output characteristics........................................................................- 8 - Figure 9: Simulink Model.......................................................................................- 10 - Figure 10: SAR Logic Simulink Model..................................................................- 10 - Figure 11: Comparator Simulink Model.................................................................- 11 - Figure 12: Capacitor Array Simulink Model ..........................................................- 11 - Figure 13: Monte Carlo simulation results for capacitance mismatch ...................- 12 - Figure 14: Performances vs. leakage power in 90nm technology ..........................- 13 - Figure 15: Waveforms for single ended signal and fully differential signal ..........- 14 - Figure 16: Single ended binary weighted switched capacitor array DAC..............- 15 - Figure 17: (a) SAR ADC using J_S capacitor array. (b) the ith sub-capacitor section of

the J_S capacitor array ....................................................................................- 17 - Figure 18: How to make the desired capacitance ratio for the J_S capacitor array- 17 - Figure 19: Energy efficient charge redistribution DAC for SAR application ........- 19 - Figure 20: Serial charge-redistribution DAC..........................................................- 20 - Figure 21: Illustration of A/D conversion sequence for Vx/Vref=13/16..................- 21 - Figure 22: DAC Circuit Schematic.........................................................................- 22 - Figure 23: Equivalent sub-circuit of MOM Capacitor Model ................................- 23 - Figure 24: Switch Circuit Schematic ......................................................................- 23 - Figure 25: On-state conductance of MOS switch vs. input signal for a low supply

voltage.............................................................................................................- 24 - Figure 26: Power vs. Frequency [] (left) and Normalized ADC Energy vs. Supply

Voltage [] (right). ............................................................................................- 24 - Figure 27: STSCL circuit of the comparator, and replica bias circuit ....................- 25 - Figure 28: Sigma vs. Size for differential pair and PMOS load .............................- 29 - Figure 29: Sigma vs. Size for the current mirror ....................................................- 30 - Figure 30: Comparator circuit schematic................................................................- 31 - Figure 31: Simplified Schematic of the Preamplifier .............................................- 31 - Figure 32: N-mirror circuit schematic ....................................................................- 32 - Figure 33: P-load circuit schematic ........................................................................- 32 - Figure 34: Level Shifter circuit schematic..............................................................- 33 - Figure 35: External driving circuit for the analog differential input ......................- 34 - Figure 36: Delay Cell circuit schematic..................................................................- 35 -

V


Figure 37: Transient Response of the delay cell.....................................................- 36 - Figure 38: SAR logic block ....................................................................................- 37 - Figure 39: State diagram corresponding to the SAR logic behavior ......................- 39 - Figure 40: Simulated logic behavior-Waveforms...................................................- 40 - Figure 41: Synthesized gate level schematic ..........................................................- 41 - Figure 43: SAR logic after Place & Route..............................................................- 44 - Figure 44: Gain and Phase of the preamplifier .......................................................- 46 - Figure 45: Comparator Transient Response for a differential input of 400mV and

4mV.................................................................................................................- 46 - Figure 46: DNL and INL - real capacitors..............................................................- 47 - Figure 47: DNL and INL - real switches ................................................................- 48 - Figure 48: Power spectrum for the real circuit. ......................................................- 48 - Figure 49: Transient response of the output of the DAC........................................- 49 - Figure 50: DNL working with 50nA of bias current at a frequency of 8kHz........- 50 - Figure 51: Input-Output Characteristic...................................................................- 51 - Figure 52:INL for 100 points per LSB ...................................................................- 51 - Figure 53: INL/DNL working with 10nA of bias current at a frequency of 20kHz - 52

-

List of Tables Table 1: Comparison between published data ..........................................................- 5 - Table 2: 90nm vs. STSCL after synthesis...............................................................- 43 - Table 3: Current versus a change in frequency.......................................................- 53 - Table 4: Current versus a change in bias current for different frequencies ............- 53 - Table 5: Current versus a change in bias current for different frequencies ............- 54 -

VI

Design of a Very Low Power SAR ADC Introduction

1 Introduction In the past few years, more and more applications are built with very stringent

requirements on power consumption. For electronic systems, such as wireless systems

or implantable devices, the power consumption is becoming one of the most critical

factors. The stringent requirements on the energy consumption increase the need for

the development of low voltage and low power circuit techniques and system building

blocks.

Analog-to-Digital Converters (ADCs) translate the analog quantities into digital

language, used in information processing, computing, data transmission and control

systems. ADCs are key components for the design of power limited systems, in order

to keep the power consumption as low as possible.

In this work, we describe the design of a very low power Successive Approximation

Register (SAR) Analog-to-Digital data Converter and its peripheral circuits (bias

generator, current mirrors, etc.). The goal is to reach a total power consumption of

few µ-Watts.

The ADC is implemented in a deep sub-micron CMOS technology. At circuit level,

we also use a new circuit technique, the Sub-Threshold Source Coupled Logic,

STSCL logic, in order to decrease the current density. This topology allows adjusting

the power consumption playing on the bias conditions.

1.1 Thesis Organization

The report starts explaining the working principle of an Analog to Digital Converter

and the comparison of different possible topologies of ADCs. Then the operation of a

SAR ADC is described. The behavioral model implemented in Matlab is described in

Chapter 3, together with the simulations that show how the converter is affected by

the most important non-idealities of the circuit.

In Chapter 4 we talk about the building blocks of the proposed SAR ADC. It is also

explained how to choose the topology, and the design approach is explained. Then we

talk about the digital block describing the code and the steps to obtain the final layout.

The results of the simulations on the entire circuit are explained in Chapter 5 and at

the end, in chapter 6, the conclusion and future improvements are presented.

- 1 -

Design of a Very Low Power SAR ADC ADC Architectures

2 ADC Architectures

Analog to Digital Converter (ADC), is an electronic circuit that converts continuous

analog signals into discrete values.

An analog signal needs to be quantized in order to be converted in a digital one. An

analog signal can take infinite values; quantization consists in the substitution of these

infinite values into discrete and finite amounts of values. In Figure 1 is shown an

example of conversion. The input signal varies between 0 and FS (full scale), and it’s

converted in a digital word of N-bits.

Figure 1: Analog-Digital Conversion

The resolution of an ADC is the number of discrete levels that it can produce at the

output. The resolution is expressed in bits, for a resolution of N-bits, there are

digital values allowed. The resolution is also defined as the minimum voltage

difference between two analog signals coded into two adjacent levels (LSB).

2N

- 2 -


2.1 Topologies Comparison

In this chapter we compare some different topologies to choose the most suitable for

us. In ADC design, the trade off between speed and power consumption is one of the

most important.

• Flash ADC

Flash ADC (Figure 2, [1]), sometimes called parallel ADC, is the fastest type of

converter, but has limited resolution, high power dissipation and relatively large chip

size [2]. The main reason for the high power consumption is the large number of

comparators. For an N-bit converter, we would need (2N-1) comparators, this means

that the number of comparators increases exponentially with the number of bits. The

comparator is one of the most power hungry components in ADC.

Focusing the attention on limit the power dissipation, different topologies that

decrease the number of comparators needed, or avoid that block, should be taken in

consideration.

Figure 2: Flash ADC Block Diagram

- 3 -


• SAR ADC

Successive Approximation Register ADC (Figure 3) represents the majority of the

ADC market for medium to high resolution. This topology requires just one

comparator; an N-bit SAR ADC will require N comparison periods and will not be

ready for the next conversion until the current one is complete. This topology is

expected to allow the lowest power dissipation, but paying the price with the slowest

sampling rate [3].

Figure 3: SAR ADC Block Diagram

• Sigma-Delta ADC

A Sigma-Delta ADC (Figure 4) contains very simple analog electronics (a

comparator, voltage reference, a switch and one or more integrators and analog

summing circuits), and quite complex digital computational circuitry. Sigma-delta

converters trade speed for resolution. The need to sample many times (at least 16

times and often more) to produce one final sample dictates that the internal analog

components in the sigma-delta modulator operate much faster than the final data rate.

The digital decimation filter is also a challenge to design and generally consumes a

larger silicon area than a simple output decoder.

Figure 4: Delta Sigma ADC Block Diagram

- 4 -


• Folding and Interpolating ADC

Folding and Interpolating ADC (Figure 5) have been applied in moderate to high-

resolution and high-speed applications. The folding ADC is a type of analog pre-

processing to reduce the number of comparators used in flash ADC. The number of

comparators is reduced by the number of fold repetitions [4]. The interpolating ADC

can reduce the number of the input amplifiers and lower the input capacitance.

In this topology the mismatch in the input differential amplifier induces a large offset,

which destroys the linearity of the ADC and limits the resolution. This can be avoided

using transistors of large area and large bias currents [5], but in this way, power

consumption increases.

Figure 5: Folding and Interpolating ADC Block Diagram

• Comparison between published data

Table 1: Comparison between published data

Topology Ref. Bits Sampling

Rate Power Vdd Technology

Ref [6] 8 70 MS/s 45 mW 3.3 V 0.8 µm Ref [7] 10 40 MS/s 65 mW 5 V 0.6 µm Ref [8] 8 30 MS/s 18 mW 1.8 V 0.18 µm

Folding and/or

Interpolating ADC Ref [9] 6 50 MS/s 20 mW 1 V 0.35 µm

Ref [10] - 4 MS/s 140 µW 1 V 90 nm Ref [11] - 1.5 MS/s 40 µW 0.9 V 0.5 µm

Sigma Delta ADC

Ref [12] - 1 MS/s 80 µW 0.7 V 0.18 µm Ref [13] 6 1.2 GS/s 90 mW 1.5 V 0.13 µm Flash

ADC Ref [14] 6 1.3 GS/s 600 mW 1.8 V 0.25 µm Ref [15] 6 1 MS/s 7 µW 0.5 V 90 nm Ref [16] 8 200 kS/s 2.5 µW 0.9 V 0.18 µm Ref [17] 10 1 MS/s 1.9 µW 1 V 65 nm

SAR ADC

Ref [18] 5 250 MS/s 1.2 mW 0.8 V 65 nm

- 5 -


The data in the table shows that the SAR ADC is the one that allows the lower power

consumption. The price to pay is the sampling rate, that is the lowest with respect to

the other topologies.

2.2 Successive Approximation Register ADC Comparing Successive Approximation Register, Flash, Folding and Interpolating and

Sigma-Delta ADCs, the SAR ADC seems allowing the lowest-power consumption.

This architecture has the advantage to be very simple; it implements the binary search

algorithm.

Power dissipation scales with the sample rate, unlike flash ADCs that usually have

constant power dissipation versus sample rate. This is especially useful in low-power

applications. Moreover SAR ADC does not contain an operational amplifier; that are

generally power-hungry, it needs just one comparator that consume much less power

than operational amplifiers.

SAR ADC has four mains building blocks (Figure 6, [2]):

- Sample-and-Hold Stage (S/H)

- Digital-to-Analog Converter (DAC)

- Comparator

- Successive Approximation Register (SAR)

Figure 6: Simplified N-bit SAR ADC architecture.

The basic functionality of a SAR ADC is very simple (Figure 7). The analog input

voltage VIN is sampled by the Track & Hold block. To implement the binary search

algorithm, the N-bit register is first set to midscale setting the MSB to '1' and all other

- 6 -


bits to ‘0’. This forces the DAC output, VDAC, to be half of the reference voltage,

VREF/2. VIN is then compared with VDAC, if VIN is greater than VDAC, the comparator

output is logic 1 and the MSB of the N-bit register remains at 1. Conversely, if VIN is

less than VDAC, the comparator output is logic 0 and the MSB of the register is cleared

to 0. The SAR control logic then moves to the next bit down, forces that bit high, and

does another comparison. The sequence continues all the way down to the LSB. Once

this is done, the conversion is completed, and the N-bit digital word is available in the

register [19].

Figure 7: SAR operation (4-bit ADC example).

SAR ADC works with two different clock frequencies. The first clock is an input of

the chip, and its frequency, fint, is the one at which the internal circuit works. The

second clock drives the Sample and Hold in order to sample the analog input value.

This second clock is internally created by a frequency divider; it should be X times

slower the first one, where X is the number of comparison periods needed from the

control logic to complete a conversion. The conversion rate is determined by this

second clock, an N-bit SAR ADC will require minimum N periods and will not be

ready for the next conversion until the current one is complete.

- 7 -

Design of a Very Low Power SAR ADC Behavioural Model

3 Behavioural Model 3.1 ADC Parameters

In an ADC there are several important parameters that allow evaluating its

performances. In our project we mainly focus our attention on some of them.

Figure 8: input/output characteristics

• DNL

Differential Non-Linearity error is defined as the difference between an actual step

width and the ideal value of 1LSB.

_ __ _

full scale rangeLSBnumber of bits

= (3.1)

If an ideal ADC is considered, its differential non-linearity is 0LSB, this means that

each analog step equals 1LSB and the transition values are spaced exactly 1LSB

apart. When the DNL error is less than or is equal to ±1LSB, a monotonic transfer

function with no missing codes is guaranteed. DNL errors of less than –1LSB or

larger than +1LSB correspond to a missing code.

DNL can be defined as:

1 1d da aDNLLSB+ −⎛ ⎞= −⎜

⎝ ⎠⎟ (3.2)

where is the physical value corresponding to the digital output code . a d

• INL

Integral Non-Linearity error is most relevant parameter for the overall accuracy of the

converter. INL is the maximum deviation of a transition point of a conversion to the

- 8 -


corresponding transition point of an ideal conversion. It means the deviation, in LSB,

of the real transfer function from a straight line.

INL represents cumulative DNL errors. It summarizes the total non linearity of the

converter.

1

1

j

ji

iINL DNL−

=

= ∑ (3.3)

. • SNR

The Signal to Noise Ratio of an ADC is the ratio of the signal power to the non-signal

power:

10 log signal

noise

PSNR

P= ⋅ (3.4)

Non-signal power includes thermal noise, quantization noise, and other residual errors

measured in the Nyquist bandwidth (fsample/2) of the ADC. SNR is typically defined

for a continuous sine wave signal applied to the ADC input. The ADC converts the

signal into discrete output levels, but there is a difference (or error) between the

actual sine wave value and the quantized level. For an ideal converter

( )1.763 6.02SNR b dB= + × (3.5) where b is the number of bits of the data converter.

• SFDR

Injecting a pure sine wave into the system, the output displays a number of peaks.

The Spurious Free Dynamic Range measures the ratio between the power of the

fundamental and the power in the largest non-fundamental peak.

3.2 Simulink Model

As first step of the project, a MATLAB-based system level analysis is performed. A

Simulink model of the ADC has been implemented in order to simulate its behavior

and extract some parameters.

This model (Figure 9) simulates the behavior of a single ended SAR ADC; the input

is compared with the output of the DAC, than the result of the comparison is used by

the SAR to elaborate the next step.

- 9 -


Figure 9: Simulink Model

The logic block (Figure 10) has been implemented using two shift register in order to

perform the successive approximation routine [20]. Each shift register is composed by

a chain of nine D Flip-Flops. The shift register on the top is used as a sequencer and

is synchronous with the internal clock. The bottom register stores the conversion

value.

Figure 10: SAR Logic Simulink Model

- 10 -


The non-idealities of the real ADC with respect to the ideal one that mostly affect his

performances are the offset of the comparator, the capacitor mismatch and the non-

ideal reference voltage.

In the comparator model (Figure 11), the two inputs are subtracted, and then a

constant value is added to their difference to model the offset of the real comparator.

The result is than multiplied by a gain that represents the amplification stage. Then

the result is saturated to full logic levels and compared to zero to define which of the

two inputs is the highest one.

Figure 11: Comparator Simulink Model

In the DAC model (Figure 12) each capacitor has been modeled as a gain which is

equal to the capacitor value. The mismatch between capacitors has been modeled as a

small random value added to each gain. The output of the DAC is created by adding

the contribution of each stage.

Figure 12: Capacitor Array Simulink Model

- 11 -


3.3 Simulations Results

For our 8bits ADC, ideally

( )1.763 6.02 49.92SNR b dB= + × = (3.6) For SNR and SFDR calculations, a low frequency sinusoidal signal is injected in the

circuit. While for INL and DNL calculation, at the input of the converter we give a

ramp with a very low slope, in order to have more than 10 samples per each LSB.

In order to see the effect of the non-idealities of the ADC, comparator offset, non-

ideal reference voltage and capacitor mismatch, Monte Carlo simulations have been

performed using Matlab. In Appendix I the Matlab codes for INL, DNL, calculations

can be found, while the one for SNR and SFDR is in Appendix II.

The error is modeled as a random value added to the ideal one. Ten points are taken

into account, corresponding to a linear increase of the variance of the random error

from zero to 1%. The code performs 100 simulations per each point, than takes the

mean value of all the result. In Figure 13 is shown how INL, DNL, SNR and SFDR

changes with the increasing mismatch of the capacitors.

Figure 13: Monte Carlo simulation results for capacitance mismatch In Appendix III are collected all the graphs that show the results for the simulations

of the three non idealities. As predicted by theory, increasing the mismatch cause a

almost linear increase in the differential and integral non-linearity, INL and DNL;

while the SNR and the SFDR decreases.

- 12 -

Design of a Very Low Power SAR ADC SAR ADC Building Blocks

4 SAR ADC Building Blocks

4.1 90nm CMOS Technology

The whole circuit is implemented in 90nm technology [21]. In order to limit the

current flowing through the circuit, MOS devices working in subthreshold region are

used.

At 90nm, leakage power management starts to be an essential issue in design process.

As geometries scale down, also voltages scale down, but the gain in performance can

be obtained just decreasing also the threshold voltage. The drawback comes from the

leakage current, which increases exponentially as threshold voltage, Vth, reduces. In

90nm technology the gate oxide gets thinner, it decreases as low as 12Å, and it causes

an increase in leakage current as well. Decreasing thickness to such value leads to the

need to reduce the voltage across the gate or the electric field would be too high for

the insulating material. The relationship between performance and leakage power for

typical 90nm processes is shown in Figure 14.

Figure 14: Performances vs. leakage power in 90nm technology

The sub-threshold leakage current increases exponentially with every 65mV decrease

in threshold voltage. This increase in leakage directly affect the power dissipation,

hence, new design methodologies are needed in order to reduce leakage power. This

is the reason for which in 90nm technology, different threshold types of PMOS and

- 13 -


NMOS transistors are available. Creating separate cells using these different

transistor types allows to have the same functionality but with different speed and

leakage characteristics. Low Vth transistors led to higher leakage, while high Vth

decrease the leakage current through the transistor.

In the technology library that we are using, the UMC90, several types of NMOS and

PMOS can be found. In our design we mostly use LLHVT12 transistors, which are

high Vth transistors with low leakage, which work with a supply voltage of 1.2V.

4.2 Fully Differential vs. Single Ended

From the input signal point-of-view, an ADC can be either a single ended signal or a

fully differential signal. A fully differential analog signal path has been chosen due to

several advantages with respect to the single ended one.

In single-ended all signals are referred to the common ground. The dynamic range is

subjected to DC offset and noise through the signal path that can decrease it. In fully

differential, the two differential inputs are 180º out of phase, the difference in voltage

between these two signals is considered. In this way the dynamic range is doubled

with respect to the single ended signal (Figure 15), and a maximum noise rejection is

achieved. Doubling the dynamic range leads to a VLSB doubled, that leads to more

relaxed constraints for the design of the comparator. The differential architecture

allows a good dynamic common mode rejection. Moreover fully differential topology

can reduce the effects of charge injection caused by parasitic capacitances, hence the

precision improves.

Figure 15: Waveforms for single ended signal and fully differential signal

- 14 -


4.3 Digital to Analog Converter DAC Topologies

In charge-redistribution SAR analog to digital converter, a large amount of power is

dissipated in switching the capacitor array. For this reason, several new DAC

topologies have been implemented in order to reduce the switching energy.

Here we compare several single ended topologies in order to choose the best one for

our ADC, then, it will be implemented fully differential.

In order to have an idea and compare the energy dissipation of the different

topologies, the case of Vin=1.2V is taken in account. VDD is set at 1.2V and the unit

capacitance is C0=100fF. The output digital code should be eight bits at logic 1.

4.3.1 Binary Weighted Switched Capacitor Array DAC

Figure 16: Single ended binary weighted switched capacitor array DAC

This DAC [22] (Figure 16) is an array of binary weighted capacitors plus one

additional capacitor of weight corresponding to the last significant bit (LSB), and

switches that connect the capacitor bottom plates to three different voltages: VDD, Vref

and ground. For a n-bit DAC, the value of the capacitors are,

102 , 1,...,i

iC C i−= ⋅ ∈ n (4.1) The conversion is performed in three operation modes. In the first, the “sample

mode”, the top plate is connected to ground and the bottom plates to the input voltage

Vin. In the “hold mode”, the top grounding switch is then opened, and the bottom

plates are connected to ground. Since the charge on the top plate is conserved, its

potential goes to -Vin. The “redistribution mode”, begins testing the value of the most

significant bit (MSB). This is done by raising the bottom plate of the largest capacitor

- 15 -


to the reference voltage Vref. Now, the circuit acts as a voltage divider between two

equal capacitances, so the voltage at the output of the DAC is:

2ref

DAC in

VV V= − + (4.2)

VDAC is then compared with zero, if VDAC<0 it means that Vin>Vref/2 , hence the MSB

is set to 1. Otherwise, if VDAC>0 , Vin<Vref/2 , hence the MSB is set to 0. In this case

the largest capacitor is reconnected to ground. The conversion proceeds in this

manner until all the bits have been determined.

From the energy point of view, we consider:

• The energy to charge Vin on Ctot= 256 ⋅C0. that is

212in tot inE C V= ⋅ ⋅ (4.3)

• The sum of the energy dissipated at each step, for step x:

21( ) ( ) ( ( 1))2ref eq refE x C x V V x= ⋅ ⋅ − − (4.4)

Where

( )

( )

( )( )

old xeq

old x

C x CC

C x C⋅

=+

(4.5)

(4.6) 1

( ) ( ))old x toti x

C C C i=

⎛= − ⎜⎝ ⎠∑ ⎞

⎟

And

1

( )( 1) i x

reftot

C iV x V

C=− = ⋅∑

(4.7)

MATLAB calculations show that the energy consumption for our particular case is

about 31pJ.

- 16 -


4.3.2 Junction-Splitting Capacitor Array

Figure 17: (a) SAR ADC using J_S capacitor array. (b) the ith sub-capacitor section of the J_S

capacitor array The J-S capacitor array [23] (Figure 17) consists of a number of serially connected

sections each of which is composed of splitting capacitor. The desired Vout is created

by appending a sub-capacitor section to the previous capacitor array.

Figure 18: How to make the desired capacitance ratio for the J_S capacitor array

In Figure 18, the denominator and numerator represent Ctot and CH, respectively, can

be seen that Ctot is not constant, it increases during the conversion process. First, the

MSB, b0, is determined by comparing the input voltage with a half reference voltage.

The half reference voltage is achieved by using the two smallest capacitors, one

connected to the ground and the other connected to the reference voltage. Then, the

- 17 -


next voltage to be compared is made by connecting a sub-capacitor section, one at a

time.

The position of all the switches in the J-S capacitor array does not change during the

redistribution mode. Therefore, the required energy is determined by the final state,

which is the fundamental lowest level. This is an advantage with respect to the

conventional capacitor array, which consumes energy in every redistribution step.

Considering the energy dissipation for an output code all at 1, there are two

contributions:

• The energy to charge Vin on Ctot= 256 ⋅C0. that is

212in tot inE C V= ⋅ ⋅ (4.8)

• The energy to charge Vref is the sum of all the energies to charge Vref at each

step. Considering the step x :

21( ) ( ) ( ( 1))2ref eq refE x C x V V x= ⋅ ⋅ − − (4.9)

Where

2( )

2 ( )eqC xC

C x=

⋅ (4.10)

and

1

1

( )( 1)

(1) ( )

i xref

j x

C iV x V

C C

=

=

− = ⋅+

∑

∑ j (4.11)

and C(x) is the weighted capacitor of the stage x.

MATLAB calculations shows that the power dissipation of this DAC is the lowest, in

our particular case around 18pJ.

On the other hand, there are several drawbacks with this topology. The main problem

comes from the fact that floating switches and floating capacitors are needed. These

problems are due to the fact that the floating elements would be easily affected by

crosstalk with the others stages. This crosstalk can determine random levels that can

cause voltage breakdown of the devices, or unwanted closing of the switches. Also

the parasitic capacitance on the top plate and the one on the bottom plate are not

equal.

- 18 -


4.3.3 Energy Efficient Charge-Redistribution DAC

Figure 19: Energy efficient charge redistribution DAC for SAR application

In energy efficient charge redistribution DAC, [24], first, we reset to a state where the

MSB is high and all other bits are low. Next, Vin is sampled onto output VDAC. In a

single-ended ADC, VDAC is compared to Vhalf. The comparator decides if the MSB

should remain high or set low during the remainder of the conversion. Next, MSB-1

is set to high and the procedure is repeated, until N comparisons have been done for

N bits. The difference with respect to the traditional Charge Redistribution DAC is

that the voltage over Ceq is charged from 0 to V in n steps of Vn

.

In this way, the dissipated energy is:

2

21 12 2eq eq

VE n C C Vn n

⎛ ⎞= ⋅ ⋅ ⋅ = ⋅ ⋅⎜ ⎟ ⋅⎝ ⎠ (4.12)

which is n times less than the one of the technique of one-step charge.

In theory, charging with n equidistant voltage steps always decreases the power by a

factor of n. In practice control overhead is added and there is only a net saving for

“small” values of n with “large” values of Ceq. A reasonable number of intermediate

steps to charge are three, while for an 8-bit DAC it is sufficient to use this multiple

steps charge technique for the 3 MSBs, while the supply voltage is used directly for

all other reference voltages, for which the energy dissipated is the typical:

212 eqE C V= ⋅ ⋅ (4.13)

For our example, taking into account also the energy to charge Vin that is the same as

for the previous topologies, an energy consumption of about 25pJ is reached.

- 19 -


The intermediate voltage levels come from big capacitors CBIG1 and CBIG2 and

automatically converge to appropriate values due to repetitive DAC operation. This

implementation is allowed, because the accuracy of the intermediate steps does not

affect the accuracy of the DAC. The energy to charge the first time this big capacitor

and maintain them charged it is not been taken in consideration in our calculation, but

its value is not negligible, due to the big value of these capacitors. So it would

became a value to add to the dissipated energy.

4.3.4 Serial Charge Redistribution D/A Converter

Figure 20: Serial charge-redistribution DAC

In Figure 20 is shown a simplified schematic diagram the serial DAC circuit is shown

[25]. Capacitors Cl and C2 are nominally of equal value. Conversion is performed

serially the most significant bit (MSB) must be determined first. The control logic

then takes a particularly simple form since the DAC input string at any given point in

the conversion is just the previously encoded word taken LSB first.

For example, in order to obtain:

2ref

DAC

VV = (4.14)

As first the capacitor C1 is precharged to the Vref by a momentary closure of S2.

Simultaneously, C2 is discharged to ground through S4. With S2, S3, and S4 open

switch, S1 is then closed momentarily to redistribute the charge. In this way on the

capacitors we obtain the desired VDAC that then will be compared directly with Vin.

Figure 21 shows how this DAC operates.

- 20 -


DAC Input Word D/A

Conversion Number

d1 d2 d3 … dN-1 dN

Comparator Output

No. of Charging

Steps 1 1 -- -- … -- -- aN 2 2 1 aN -- … -- -- aN-1 4 3 1 aN-1 aN … -- -- aN-2 6 … … … … … … … … … N 1 a2 a3 … aN-1 aN 2N

TOTAL.. N(N+1)

Figure 21: Illustration of A/D conversion sequence for Vx/Vref=13/16 The advantage of this topology is that we just need to charge the basic capacitance,

and then, during the redistribution step, no energy is dissipated. However for an N-bit

conversion, charging steps are required. This makes the sampling

frequency really low. In the case of an 8-bit SAR ADC, we would need 72 clock

cycles per each conversion, half for charging and half for the .redistribution.

( 1N N⋅ + )

Every step consume the same amount of energy, so the energy dissipated for one

conversion is

20

1 722 2 refE C V= ⋅ ⋅ ⋅ (4.15)

there are no peaks. The calculated energy for the case that we are taking in

consideration comes out to be 25pJ.

4.3.5 Circuit Choice and Design

For the J-S capacitor array, taking in account advantage and drawbacks, the gain in

energy dissipation is not sufficient to compensate the problems that it can give. Also

the serial charge redistribution DAC is good in terms of energy consumption, but the

number of clock cycles to perform one conversion would deteriorate too much the

sampling rate. The energy efficient charge redistribution has a gain in energy

dissipation, but the two big capacitors would be a problem. Hence, the traditional

binary weighted capacitor array has been chosen.

Figure 22 shows the schematic of the ideal DAC.

- 21 -


Figure 22: DAC Circuit Schematic

- 22 -


The ideal capacitors have then been replaced with symmetric Metal Oxide Metal,

MOM, capacitors, the basic capacitance is chosen to be C0=100fF. MOM capacitors

rely on coupling capacitance between metal fingers running in parallel. We choose a

symmetric architecture, the equivalent circuit is shown in Figure 23.

Figure 23: Equivalent sub-circuit of MOM Capacitor Model

Using a configuration with the same value of parasitic capacitance on the top and the

bottom plate means that the architecture is basically symmetric in terms of the two

ports.

Each analog switch has been implemented connecting an NMOS in parallel with a

PMOS. The NMOS is driven by the signal coming from the logic block, while the

PMOS is driven by the inverted signal. The switch conductivity depends not on the

absolute potential of the control terminals, but on their potential relative to the others.

Whether the n- or the p-channel device carries more signal current depends on the

ratio of input to output voltage. Because the switch has no preferred direction for

current flow, it has no preferred input or output [26].

Figure 24: Switch Circuit Schematic

- 23 -


Figure 25: On-state conductance of MOS switch vs. input signal for a low supply voltage

4.4 Comparator

The comparator is the block that affects the most the total power consumption of the

SAR ADC, it is composed by preamplifiers and latch. Most of the analog power is

consumed by the comparator and it is almost constant with respect the clock

frequency while depends on the value of the supply voltage (as shown in figures 26).

Regarding the digital power and the reference power, both are dynamic. They scale

with the clock frequency and decrease reducing the supply voltage.

Figure 26: Power vs. Frequency [27] (left) and Normalized ADC Energy vs. Supply Voltage [28]

(right).

- 24 -


In our project we use a new topology for the comparator in order to make the velocity

of the comparator independent from the supply voltage with minimum power

consumption (Figure 27, [9]).

Figure 27: STSCL circuit of the comparator, and replica bias circuit

4.4.1 Subthreshold Source-Coupled Logic

Source-Coupled Logic [29] [30] allows reducing the sensitivity of the circuit to the

supply voltage variation. Hence the speed of operation of this logic is independent

from the supply voltage while can be controlled by acting on the tail bias current.

Moreover, using transistors operating in weak inversion, subthreshold regime, the

current density is very low while the ratio between transconductance and bias current,

gm/Id , is maximum. STSCL logic gates can operate biased with a very small tail

current which value can range from 10 pA to 100 nA. It is been shown that in STSCL

circuits the power consumption can be reduced to 1fJ/gate, this makes this approach

very suitable for low voltage-low power applications.

• PMOS Load Devices

When the bias current is reduced to very low values, the load resistance should be

proportionally increased in order to maintain the same voltage swing at the output,

following the relation:.

SW L SSV R I= ⋅ (4.16)

- 25 -


Taking into account that our ISS is in the order of tenth of nA and VSW should range

between 200-500mV, RL needs to be in the order of several MΩ. In order to reach this

value of resistance and control it accurately with ISS, the conventional PMOS

transistors biased in triode region would need a very long channel length. A novel

structure of integrated high value resistors, HVR [31], implements very large value

resistors with PMOS biased in subthreshold regime. The PMOS bulk, that is an

isolated N-well, is connected to its drain. Increasing VSD the threshold voltage is

modified, hence the drain current, ID, increases. By keeping VSD higher than zero and

VSG (source-gate voltage) low, very high value resistors can be obtained maintaining

the device sizes very small.

• Replica Bias

The value of the PMOS load resistor can vary between hundreds of KΩ and 1GΩ,

and it depends on the gate voltage VG of the device. In order to bias the load devices

to have the right resistance and control VSW at the output of the comparator, a replica

bias circuit is used (real schematic in Appendix IV, simplified schematic in Figure

27). The replica bias circuit should be well matched to the SCL gates, conversely, we

would have a variation with respect to the desired operating point that is not

negligible, and the output voltage swing would be different than the desired one. In

terms of accuracy, the amplifier is a critical component; we need it to provide enough

gain with a very low offset.

4.4.2 Design Approach

Here we design the preamplifiers of our comparator; we base our calculation on the

Enz-Krummenacher-Vittoz (EKV) model, which is a continuous model developed for

MOS transistors. Its equations are valid in all regimes of operation, above or below

threshold, as well as in saturation, for this reason, the EKV model is highly suitable

our low-voltage circuit that operates in subthreshold regime [32].

The MOS digital circuits operate in subthreshold regime when the supply voltage is

lower than the threshold voltage Vth of the transistors. The drain current of an NMOS

transistor operating in this regime is given by:

- 26 -


exp 1 expGS th DSDS ss

T T

V V VI InU U

⎡ ⎤⎛ ⎞ ⎛−= ⋅ ⋅ − −

⎞⎢ ⎥⎜ ⎟ ⎜

⎝ ⎠ ⎝⎟⎠⎣ ⎦

(4.17)

where n is the subthreshold slope factor; UT is the thermal voltage; VGS and VDS are

the gate to source and drain to source voltages, respectively. The current Iss is given

by:

22ss ox TWI n C UL

µ= ⋅ ⋅ ⋅ ⋅ ⋅ (4.18)

where µ is the mobility of carriers, Cox is the gate oxide capacitance per unit area and

W/L is the aspect ratio of the transistor. The drain current of a MOS transistor in

subthreshold region shows exponential dependence on VGS and VDS, slope factor and

the operating temperature. IDS=0 when VDS= 0, and reaches its maximum value and

saturates with VDS higher than a few UT .

For the PMOS load devices

0

exp exp 1SD SDSD SD

T T

V VI InU U

⎡ ⎤⎛ ⎞ ⎛ ⎞= ⋅ − ⋅ − −⎢ ⎥⎜ ⎟ ⎜ ⎟

⎝ ⎠ ⎝ ⎠⎣ ⎦ (4.19)

where

0 0 exp SG

SDT

VI In U

⎛ ⎞= ⋅ ⎜ ⋅⎝ ⎠

⎟ (4.20)

The voltage swing at the output is

sw ss LRV I= ⋅ (4.21) and it should be large enough to guarantee to switch completely the current in the

input transistors of the next stage. It means that, being in subthreshold region, we

need

( )4 200 300sw TV n U m≥ ⋅ ⋅ ≈ ÷ V (4.22) The gain of each stage depends on the voltage swing Vsw. In order to calculate the

voltage gain, the transconductance of the input differential pair can be expressed by:

2

12

cosh2

ssm

T in

T

Ign U V

n U

= ⋅⋅ ⋅ ⎛ ⎞∆

⎜ ⎟⋅ ⋅⎝ ⎠

(4.23)

where ∆Vin is the input differential voltage.

It can be shown that there is an upper bound for the differential gain of the circuit for

∆Vin = 0V that can be expressed as

( ),max 1p

vn p

nA

n n=

− (4.24)

- 27 -


4.4.3 Matching Considerations

We implement a fully differential 8-bit SAR ADC in 90nm technology. It has a

differential input voltage range of ± 1.2V and the supply voltage is 1.2V. The

converter requires 9 clock cycles per conversion.

The minimum input voltage difference that has to be discriminated is:

_ _ 2.4 9.3752 256LSB n

input dynamic rangeV m= = V= (4.25)

When a real comparator compares the two signals at its input, the output is not

exactly equal to the difference of the two [33] [34]. This is due to the comparator

offset voltage Vos, which depends on the matching properties of the used technology.

Since Vos is a random variable, it directly influences the differential nonlinearity

(DNL) and the integral nonlinearity (INL). Hence, as first step for the design, we

should derive the offset voltage standard deviation, σos, that guarantees

32LSB

osVσ⋅ ≤ (4.26)

so we need 1.5625os mVσ ≤ .

Taking into account a single preamplifier that is part of the comparator, the offset

voltage has two main contributions: ( )_ , _osV f differential pair PMOS load= .

We know the relation with the threshold voltage difference ∆VT:

Tos T os T

n T

VV U V Vn U∆

≈ ⋅ → ≈ ∆⋅

(4.27)

The mismatch formula for the differential pair is:

( )222 5

TVos

A mV mW L W L

µσ

⋅= ≈

⋅ ⋅ (4.28)

where AVT is a process dependent parameter.

The accuracy of the conversion is proportional to the matching of the transistor. In

order to improve the system accuracy, longer devices are required, but in this way,

the capacitive loading of the circuit nodes increases, hence, more power is required to

reach certain speed performances:

2

m

gs

gSpeedCπ

≈⋅ ⋅

(4.29)

It can be proved that

2 1

Tox V

Speed AccuracyPower C A×

≈⋅

(4.30)

- 28 -


hence we need to size the transistor in order to find the best compromise that allows

to fulfill the constrain on the offset, without decrease the speed below a certain lower

limit.

Several Monte Carlo simulations of the comparator have been performed in

CADENCE. The two contributions to the standard deviation are taken in

consideration separately. We need

( )22 2 2 3_ 1.5625 10os PMOS diff pairσ σ σ −= + ≤ ⋅ (4.31)

First, we fix the size of the PMOS load and the current mirror to big values,

105

Pload

Pload

W umL um

= , 105

Mirr

Mirr

W umL um

= and we sweep the size of the differential pair

maintaining a ratio 1Diff

Diff

WL

= . For every value of the ratio, 50 runs are performed.

For the PMOS load we repeat the same procedure, we sweep the ratio Pload

Pload

WL

and

maintain fix 105

Diff

Diff

W umL um

= and 105

Mirr

Mirr

W umL um

= .

In Figure 28 the results are plotted, using these graph we can determine the maximum

WL for the sizing the transistors.

Differential Pair

0

5

10

15

20

25

30

35

0 10 20 30 40

W*L [um]

Sigm

a O

ffset

[mV]

P Load

02468

101214161820

0 10 20 30 40

W*L [um]

Sigm

a O

ffset

[mV]

Figure 28: Sigma vs. Size for differential pair and PMOS load

tarting from these results, others simulations has been performed to find the best S

compromise between the offset and the rising time of the comparator, that affect the

allowable maximum working frequency. We define that we need to be able to convert

without missing codes at 2KSample/s at least. Taking in account that the internal

working clock is nine times faster than the sampling rate, in order to reach

- 29 -


2KSample/s an internal frequency of 18KHz is needed. This means that the rising

time should be at least less than a quarter of the period.

The mismatch of two closely spaced, identical MOS transistor doesn’t affect just the

comparator offset, but also the current factor difference, oxWCL

β β µ⎛ ⎞∆ =⎜ ⎟⎝ ⎠

The threshold voltage difference and the current factor difference have a low

correlation, so are usually modeled as independent random variables.

Under nominal operation, the output current of the mirror is equal to the input current,

out inI I= , where Iout corresponds to our bias current Ib. In reality, the mismatch

between the transistor of the current mirror cause a little difference, so out inI I I= + ∆ .

Monte Carlo simulations have been performed in the same manner as for the voltage

offset. For a fix bias current, we have swept the size of the transistor of the current

mirror and fixing 105

Pload

Pload

W umL um

= and 105

Diff

Diff

W umL um

= .

The results are shown in figure 29.

N Mirror

02468

1012141618

0 5 10 15 20

W*L [um]

Mirr

ored

Cur

rent

[nA

]

Figure 29: Sigma vs. Size for the current mirror

4.4.4 Circuit implementation

The comparator is implemented with two preamplifier stages, and one latch. The

preamplifiers amplifies the differential signal, than the latch establish full logic levels

and synchronize the decision of the comparator with the other blocks.

- 30 -


Figure 30: Comparator circuit schematic

Each preamplifier consists of an N-mirror, a differential pair and the P-load. The

simplified schematic of a single preamplifier is shown in Figure 31.

Figure 31: Simplified Schematic of the Preamplifier

- 31 -


Figure 32 shows the circuit implementation of the N- mirror, its transistors have been

sized in order to maintain the error on the current due to the transistor mismatch less

than 2%. The high Vth transistors are placed is series in order to create a transistor

with a high length, L. In this way, the preamplifier is less affected by the unwanted

noise on ground.

Figure 32: N-mirror circuit schematic

In the following figures the P-load and the whole preamplifier are shown. As

explained before, the Bulk of the PMOS is connected to the Drain in order to create a

large resistance value.

Figure 33: P-load circuit schematic

- 32 -


The two capacitors of value C1 and C2 are used to model the parasitic capacitance

and their values are calculated as:

( ) (1 2 p p )j perimeterC L W C= ⋅ + × (4.32) and

(2 p p j areaC L W C )= ⋅ × (4.33)

4.5 Level shifter

This block is used in order to be sure that the output of the comparator saturates to

full logic levels for any input values difference. This avoids unwanted problems that

can rise if the logic block is driven by values too different from the logic levels 1.2V

and 0V.

The circuit is shown in Figure 34, the first stage amplifies the difference between the

inputs, than the first inverter produces the output corresponding to the saturated logic

level for inP, and the last inverter the one for inN.

Figure 34: Level Shifter circuit schematic

4.6 Track and Hold

In the typical configuration of the SAR ADC, the Track and Hold is one of the basic

building blocks. In our SAR ADC we choose to use the capacitor array as sampling

capacitor to acquire the analog signal during the sampling phase, that least one clock

- 33 -


period, and avoid this block. The reasons of this choice are several, first of all the

Track & Hold circuit would need a switch and a capacitor, but also a voltage follower

to adapt the impedance. This would add consumption of power that can be avoided.

In order to charge directly on the DAC capacitors, we decide to define our

specification on the sampling frequency in order to have a driving impedance

relatively high. In this way, our A/D converter can be directly driven by an external

compatible impedance source, as shown in Figure 35, without gain error.

Figure 35: External driving circuit for the analog differential input

We define that the driving impedance should be at least 1dR M≈ Ω . The DAC basic

capacitor is , so the total capacitance that can be seen at the input of the

DAC for each input is . We can easily calculate the time

constant to charge the capacitor array as

0 100C ≈ fF

pF0128 12.8totC C= ⋅ =

12.8d totR C sτ µ= ⋅ ≈ (4.34) The maximum error that we can tolerate is half of the LSB, that normalized

correspond to 0.002. Hence we put a constrain on the normalized error that is:

0.002T

e τε−

= ≤ (4.35) It is straightforward that

min1ln 6.21T τ τε

= ⋅ = ⋅ (4.36)

Hence the minimum period is min 80T sµ≈ .

From these calculations we can define a specification on the maximum allowable

sampling rate of

max

min

1 1.49samp

kSamplefT s

= ≈⋅

(4.37)

- 34 -


4.7 Delay Cell

A delayed clock is needed by the logic block. The desired delay is obtained by

cascading a number of inverters. In this way it is possible to obtain the desired signal

that is delayed with respect to the internal clock, maintaining the same period and

duty cycle.

Figure 36: Delay Cell circuit schematic

We need inverter cells with high delay; this can be reached by increasing the length

value L of the MOS transistors due to the relationship:

nPHL

n

LW

τ ∝ (4.38)

pPLH

p

LW

τ ∝ (4.39)

where τPHL and τPLH are the high-to-low and low-to-high propagation delay times of a

CMOS inverter. The drawback of using long channel devices is that the charge

injection increases, so, the output voltage can have spikes above and below the

desired values. These spikes should be maintained small to avoid a degradation of the

chip, so the last two inverters are short channel devices. These two last inverters also

allow a short rise and fall times of the delayed clock signal.

Simulations of the circuit shows that we can obtain a delay of about 3ns between 50%

of the rising edge of the input clock and the 50% of the rising edge of the output

- 35 -


delayed clock. The rising time of the delayed clock calculated between 10% and 90%

of the rising edge is 45ps.

Figure 37: Transient Response of the delay cell

4.8 SAR Logic

The logic control block of the ADC has two important aims. It sets the switches in

function of the current state of the conversion and the output of the comparator;

moreover, it computes and stores the digital converted value to be given as output at

the end of the conversion. The Successive Approximation Register has been

implemented in VHDL. The code is then synthesized, it means compiled and mapped

into the desired technology. As final step, the place & route allows to create the

physical layout for the circuit.

4.8.1 VHDL Code

The SAR logic is implemented as synthesizable VHDL model at the Register

Transfer Level, RTL level. The code can be found in Appendix V.

- 36 -


Figure 38: SAR logic block

The logic block is synchronous with the internal clock, CLK.

CLKD is the delayed clock; The switches in our circuit are not ideal, so, if we need to

close and open at the same time two of them there can be a little moment when both

two conduct. This can cause an unwanted short circuit. CLKD allows to drive the

switches that should be opened before the ones that should be closed.

CLKN is the inverse of the internal clock. The comparator reach full logic levels just

at the falling edge of the clock, hence we need to check the comparator output and

take a decision for the next bit when the clock is low. Our state machine is

synchronized with the rising edge of the clock. It is never good to be sensitive to both

edge of a signal, for this reason the negated clock, CLKN, is used in order to check

the comparison and set the bits of the digital converted value.

RST is the reset signal; it is asynchronous and active low. When the reset is released

and goes high, the rising edge of the clock is waited to enter in Sample mode.

SC is the Start Conversion; it should be set low to start a conversion. If SC goes high,

the current conversion is completed, then the converter remains in Sample mode until

SC back low and a new conversion can start.

IN_POS and IN_NEG are the output of the level shifter that brings the comparator

response.

At the output of the block there are the controlling signals for the switches of the

DAC, plus the converted value. The output digital value is available during the

Sample state, and remains fix until the next conversion is been performed and the

new converted value is ready.

The control signal that drives the switch that connects the dummy capacitor C0 to

ground goes high only during the Sample state. This signal is also given as output of

the chip as BUSY signal. When BUSY is high the conversion is completed and the

output data can be read.

- 37 -


In Figure 39 the simplified behavior of the logic is explained by a state diagram

should be highlighted that the signal V+ and V- are created internally in function of

the comparator outputs and the signal ‘sel’. They are equal to the comparator output if

‘sel’ is high, otherwise are the inverse.

In Figure 40 the simulated waveforms for the conversion of an input at half of the full

scale, are shown, the output digital value is ‘10000000’.

- 38 -


RESET STATEReset all.

Connect all the capacitances to

ground and open all the other switches

If V+<V- then bit5=1

else bit5=0

charge Vref on the next capacitor,

C5, andIf bit5=0 then

connect to gnd C6 capacitor

Bit7=1


else bit0=0

Connect all capacitors to Vin


else bit1=0





else bit2=0





else bit3=0





else bit4=0




STATE 5 STATE 4

STATE 1STATE 8

STATE 2

STATE 3STATE 6

STATE 7

CLK=’1'

CLKN=’1'

CLK=’1'

CLK=’1'

CLK=’1'CLK=’1'

CLK=’1'

CLK=’1'

CLKN=’1'

CLKN=’1'

CLKN=’1'

CLKN=’1'

CLKN=’1'

CLKN=’1'

CLKN=’1'

RST=’1'RST=’0'

RST=’0'

RST=’0'

RST=’0'

RST=’0'

RST=’0'

RST=’0'

RST=’0'

Start new conversion: Vin is charged on the capacitor array

C7,…,C0

Output the old converted digital value, ConvVal. If sel=1 then

ConvVal=bit else ConvVal=not(bit)

SAMPLE MODE

Charge Vref on the MSB capacitors,C7, all other capacitors connected to gnd.

Vdac=-Vin+(Vref/2)




Bit7=1If Vdac+>Vdac-

then sel=1,Vin+(-) compared with

Vref+(-) else sel=0, Vin+(-) compared

with Vref-(+)


else bit6=0

RST=’0'

SC=1

CLK=’1' &

SC=’0'

CLK=’1'

Figure 39: State diagram corresponding to the SAR logic behavior

- 39 -


Figure 40: Simulated logic behavior-Waveforms

- 40 -


4.8.2 Synthesis

The Synthesis infers a gate level realization of the RTL description that meets the

constraints that we specify, in our case power consumption and timing.

After synthesis, reports about the circuit are created: Number of ports: 34 Number of nets: 136 Number of cells: 130 Number of references: 22 Combinational area: 416 µm Noncombinational area: 965 µm Total cell area: 1381 µm

Cell Internal Power = 10.8104 nW (83%) Net Switching Power = 2.1650 nW (17%) --------- Total Dynamic Power = 12.9753 nW (100%) Cell Leakage Power = 2.2340 uW

Figure 41: Synthesized gate level schematic

- 41 -


Comparing the dynamic power and the leakage power it is evident that the main

contribution to the total consumption comes from the leakage. In order to explain it,

we need to consider the different contributions to the power consumption in a circuit,

which can be divided into 3 different components that are:

• Dynamic or switching power consumption. It occurs when signals change

their logic state, this cause charging and discharging of internal parasitic

capacitances.

• Short circuit power consumption. It occurs during switching of both NMOS

and PMOS transistors in the circuit; due to the simultaneous conduction there is a

direct conducting path from the power supply to the ground for a short amount of

time period.

• Static or Leakage power consumption. Leakage is the power consumed due

to flow of current from the power rails in the absence of any switching activity. There

are two primary sources of leakage in MOS transistors. First one is the sub-threshold

leakage, which is leakage from drain to source (or power to ground). It is based on the

fact that no transistor is a perfect switch. The other main component is gate-oxide

leakage.

As MOS transistors are reduced to deep submicron sizes, undesirable consequences

regarding power consumption arise. Decreasing the dimensions of the transistor

requires a reduction in the supply voltage to keep the dynamic power consumption

reasonable. This demands a reduction of the threshold voltage to maintain

performance, which causes an exponential increase in the sub-threshold leakage

current. Also thinner gate oxides have led to an increase in gate leakage current due to

electron tunneling through the gate oxide.

With every shrinking dimension, the leakage current will become even greater than

the dynamic current in the overall power dissipation. Working in 90nm technology

we are affected by this unwanted effect, that is evident comparing the total dynamic

power and the cell leakage power consumption reported after synthesis.

A good solution to decrease the leakage power is to use STSCL logic gates instead of

standard 90nm CMOS logic gates. In Table 2 we compare the reports on the area and

power after the synthesis.

- 42 -


Table 2: 90nm vs. STSCL after synthesis

90 nm CMOS STSCL

Number of ports 34 35

Number of nets 136 313

Number of cells 130 270

Number of references 22 31

Combinational area 416 um 9215 um

Non-combinational area 965 um 2410 um

Total cell area 1381 um 11625 um

Cell Internal Power 10.8104 nW 2.5520 fW

Net Switching Power 2.1650 nW 1.0073 nW

Total Dynamic Power 12.9753 nW 1.0073 nW

Cell Leakage Power 2.2340 uW 593.0607 nW

We can notice that with STSCL logic, the number of cells increases, hence the area, is

more than doubled. On the other hand, the power consumption decreases

significantly. The leakage power is almost a quarter of the leakage in 90nm.

- 43 -


4.8.3 Place & Route

Figure 42: SAR logic after Place & Route

The placement and routing of the synthesized gate-level netlist infers a geometric

realization of the gate level netlist, the layout. The MOS transistors that are used are

in 90nm technology, the standard performance ones, N_12_SP and P_12_SP.

As shown in Figure 43, a power ring is placed all around the block and each cell

inside it has a power rail at its top and a ground rail at its bottom.

- 44 -

Design of a Very Low Power SAR ADC Experimental Results

5 Experimental Results

As first step, the ADC circuit has been implemented in CADENCE with ideal

components, and then one kind of component has been substituted with the real one at

each time in order to simulate its effect on the linearity. For some problems related to

CADENCE, the components from the library UMC90 cannot be simulated with a

digital block written in VHDL or Verilog. For this reason we have implemented a

digital block in Verilog-A language that has the same behavior as the one

implemented in VHDL, the only difference is that the Verilog-A code takes eight

clock cycles to complete a conversion instead of nine, this is because the VHDL has

been modified during the last simulations on the whole real circuit.

The Verilog-A code can be found in Appendix VI.

As last step, the whole circuit made up of real analog components in 90nm

technology and the LVS_extracted of the layout of the digital block has been

simulated. From these simulations, the input and output of the converter have been

analyzed to extract the non-linearity parameters. Moreover, we checked the current

flowing through the circuit to have a rough estimation of the power consumption.

5.1 Comparator

The comparator has two preamplifier stages and one latch. Some AC simulations of

the single preamplifier have been performed. In Figure 44 the gain and phase versus

frequency are plotted. The gain of a single preamplifier stage is A0=11.34dB. The

frequency at -3dB is f-3dB=46.8 kHz, this is a value sufficiently large considering our

working frequency. The phase margin is PM=74 and the gain-bandwidth product is

fGBW=167 kHz.

- 45 -


Figure 43: Gain and Phase of the preamplifier

Figure 45 shows the simulated response of the comparator for a differential input

square wave. We can see that also for an input difference of 4mV, that corresponds to

half of the LSB, the comparator discriminates which input is the higher one. The full

logic levels are reached when the inverse clock, CLKN is high.

Figure 44: Comparator Transient Response for a differential input of 400mV and 4mV

- 46 -


5.2 Mismatch effects on ADC parameters

• MOM Capacitors and Real Switches

The first component to be substituted has been the capacitors of the DAC, then, we

perform some Monte Carlo simulations. We have performed 100 runs; each run, the

tool inserted a mismatch between the capacitors, where C0=100fF. The maximum

mismatch inserted by CADENCE is σos,cap=0.454fF. The extracted non linearity

parameters show that this mismatch doesn’t affect too much the non linearity, in

Figure 46 are shown the two parameters plotted for one of the runs. The worst

integral non linearity comes out to be INL=0.2342LSB.

Figure 45: DNL and INL - real capacitors

The same kind of simulation has been performed with the ideal capacitors, but

replacing the switches with the real ones. The extracted INL and DNL are shown in

Figure 47.

- 47 -


Figure 46: DNL and INL - real switches

5.3 Signal to Noise Ratio

Simulating the circuit for a sinusoidal input, the results can be imported in MATLAB

in order to extract the SNR and SFDR, using the Fast Fourier Transform (FFT). The

power spectrum is plotted in the Nyquist bandwidth fs/2. We define a sampling clock

fs=1.024kHz, than we simulate for a number of fft points Nfft=256. The frequency of

the input sinusoidal signal is fin=255Hz.

For the ideal circuit we extract an SNR=48.7dB, slightly lower than the ideal one, that

is 49.9dB. The SFDR is 57.7 and the effective number of bits is ENOB=7.8.

The power spectrum in Figure 48 is plotted for the simulation of the ADC with real

components.

Figure 47: Power spectrum for the real circuit.

- 48 -


5.4 DAC

In Figure 48 is shown the output of the DAC for the conversion of the analog inputs

Vin=1.2 and Vin=-1.2, the maximum and minimum allowable input for the converter.

The output of the DAC is the input of the comparator. Whatever is the number to

convert, the common mode of the comparator differential input is always 0.6V, half

of the full scale. This avoids problems due to the input range of the comparator.

Figure 48: Transient response of the output of the DAC

- 49 -


5.5 Input/Output Characteristic

At the input of the converter, we gave a ramp with a very low slope, in order to

ideally have 10 samples per each digital value. From the results of this simulation, we

have been able to extract in MATLAB the integral and differential non-linearity.

Figure 49: DNL working with 50nA of bias current at a frequency of 8kHz

To better understand this behaviour, the analog input versus the digital output is

plotted in Figure 51. The peak in the middle of the DNL corresponds to the passage

of the analog input through zero; it means that the differential signals IN+ and IN- are

both at 0.6V and their difference correspond to 0V. We can see that for the 2 digital

levels around 0, instead of staying 1LSB on one level and 1LSB on the other, the

characteristic stays ¾ of 2LSB on the first level, and ¼ of 2LSB on the other one.

Also changing the operating frequency, this behavior doesn’t change; it means that it

is a problem due to the logic of the conversion that has to be fixed. However, it

remains a local problem; it doesn’t affect the linearity of the next conversions.

- 50 -


Figure 50: Input-Output Characteristic

It can be seen immediately that almost all the steps are equally spaced in both x and y

directions. This led to a DNL that is for most of the time equal to zero. This would

seem strange considering that the circuit is composed by real components, but we

didn’t inject any mismatch between the components, moreover the simulations have

been performed for 10 samples per each digital step. Focusing on the initial part of

the ramp and simulating in order to have 100 points per step, we can see that actually,

there is a variation in the DNL.

Figure 51:INL for 100 points per LSB

Then we try to find, ideally, which is the upper limit until which we can increase the

frequency of operation, and the bottom limit for the bias current. Working at 20 kHz

with a bias current of 10nA, the differential non linearity of the circuit starts

exceeding 1LSB.

- 51 -


Figure 52: INL/DNL working with 10nA of bias current at a frequency of 20kHz

5.6 Current and power considerations

We perform several simulations in order to check the current flowing through the

whole circuit and how it is divided between the different blocks. The current is

directly proportional to the power consumption, so we can estimate it.

Some parameters have been changed between different simulations, in this way we

can check the effect of each parameter on the power consumption of the converter

and of each of his building blocks.

It is important to underline the fact that these simulations were carried on with bias

current that are also different from the nominal one, and for frequencies that

sometimes exceeds their maximum value. This is done because the goal of these

simulations is to show how the current changes in the circuit due to a change of these

parameters.

The parameters on which we play are three, the value of the basic capacitor, the

internal frequency of operation and the bias current. Each time we fix one or two

parameters and we compare how the current in the circuit change due to the change of

the others.

- 52 -


We consider the rms(root mean square) value of the currents flowing through:

• The comparator (the two preamplifier, latch, replica bias blocks): Icomparator;

• The digital logic block: ISARlogic;

• The Digital to Analog converter: IDAC;

• The others analog blocks, level shifter and delay cells: Ianalog;

• The whole ADC circuit: ITOT=rms(Icomparator+ISARlogic+Ianalog+IDAC).

First we fix the basic capacitor value and the bias current to see the effect of a change

in the working frequency.

C0 97.4783 fF Ibias 50 nA

Table 3: Current versus a change in frequency

fint

[Hz]

Icomparator

[A]

ISARlogic

[A]

Ianalog

[A]

IDAC

[A]

ITOT

[A]

P=VDDITOT

[W]

8 k 495n 8.28u 2.66u 5.04u 10.74u 12.9u

12.5 k 496n 9.21u 2.39u 4.04u 11.15u 13.4u

20 k 505n 12.56u 2.39u 4.25u 14.18u 17.0u

It is evident the increase in the value of the current flowing in the digital block due to

the increase in frequency.

In the next Table we can see for different frequencies, how the current change if we

change the bias current.

C0 97.4783 fF

Table 4: Current versus a change in bias current for different frequencies

Ibias

[A]

fint

[Hz]

Icomparator

[A]

ISARlogic

[A]

Ianalog

[A]

IDAC

[A]

ITOT

[A]

P=VDDITOT

[W]

10n 8 k 120n 8.25u 2.48u 3.18u 9.77u 11.7u

50n 8 k 495n 8.28u 2.66u 5.04u 10.74u 12.9u

10n 12.5 k 121n 9.24u 2.86u 3.90u 11.27u 13.5u

50n 12.5 k 496n 9.21u 2.39u 4.04u 11.15u 13.4u

10n 20 k 143n 12.52u 3.11u 4.31u 14.41u 17.3u

50n 20 k 505n 12.56u 2.39u 4.25u 14.18u 17.0u

- 53 -


As predicted by theory, the comparator consumes less if the bias current decreases,

however this can be a benefit just in case of low frequencies. When the frequencies

are higher, the decrease in consumption due to the comparator became negligible

compared to the increase of current requested by the level shifter and the delay cells,

that contain inverters.

In Table 4 we see the effect of changing the size of the basic capacitor for different

frequencies and a fixed bias current.

Ibias 50nA

Table 5: Current versus a change in bias current for different frequencies

C0

[F]

fint

[Hz]

Icomparator

[A]

ISARlogic

[A]

Ianalog

[A]

IDAC

[A]

ITOT

[A]

P=VDDITOT

[W]

97.4783 f 8 k 495n 8.28u 2.66u 5.04u 10.74u 12.9u

7.71472f 8 k 495n 8.24u 2.71u 4.09u 10.17u 12.2u

97.4783 f 20 k 505n 12.56u 2.39u 4.25u 14.18u 17.0u

7.71472f 20 k 504n 12.51u 2.36u 3.80u 13.99u 16.8u

The DAC consumes less if the capacitance decrease, this is evident considering that

the energy is proportional to the capacitance: 212in tot inE C V= ⋅ ⋅

- 54 -

Design of a Very Low Power SAR ADC Conclusions

6 Conclusions

This project has been started with an extensive research in order to study and analyze

the state of the arts of the ultra low power ADCs. Based on this study the SAR

architecture has been chosen as the one that allows targeting few micro-Watts of

power consumption. Then, a behavioral model in Matlab has been implemented to

study the working principle and the effects of non-idealities on the converter

performances. A deep research on the available literature has been carried out to

define the topologies of the various building blocks of the ADC core. The ADC core

is composed by comparator, DAC, SAR control logic and delay elements; these

components have been designed targeting to fulfill several constraints on

requirements such as the offsets due to mismatch.

From the results presented in the previous chapter it can be deduced that the

performance of the ADC less than ideal. Actually it consumes a low amount of

power, few tens of micro-Watts, but the price to pay is in the speed of the conversion

that decreases to few kSample/s. However the conversion is performed without

missing codes.

Power supply 1.2 V

Process Technology 90 nm

Input dynamic range ±1.2V (differential)

Resolution 8 bits

Internal frequency fint 12.6 kHz

Sampling Rate 1.4 kSample/s

Basic capacitor C0 97.4783 fF

Bias current Ibias 50 nA

Power 13.4 µW

- 55 -

Design of a Very Low Power SAR ADC Conclusions

6.1 Future work

In the limited time available for this project we couldn’t perform some important

analysis, such as noise analysis. As future work, several improvements can be

brought to the circuit in order to increase the performances.

First a study of the most suitable design for Track and Hold circuit to be inserted in

the circuit can be performed; adding this block the sampling rate can be increased.

Also, the analog components, such as the level shifter, can be redesigned to decrease

the amount of current that they require.

But the most important element that we should care about is the logic block.

Currently it is built by components from the standard 90nm CMOS technology;

targeting a lower consumption of power the digital part can be implemented with

STSCL gates, this would help a lot to decrease the current flowing through it.

The last important part that we still have to work on, is the layout of the whole circuit

and the post layout simulations in order to see the real behavior and performances of

the ADC.

- 56 -


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[17] M. van Elzakker, E. van Tuijl, P. Geraeds, D. Schinkel, E. Klumperink, B. Nauta “A 1.9uW 4.4fJ/Conversion-step 10b 1MS/s Charge Redistribution ADC”, Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), 3-7 Feb. 2008. [18] B.P. Ginsburg, A.P. Chandrakasan, “12.2 Highly Interleaved 5b 250MS/s ADC with Redundant Channels in 65nm CMOS”, Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International, 3-7 Feb. 2008. [19] http://www.maxim-ic.com/appnotes.cfm/an_pk/1080/, 21 juin 2009. [20] M. D. Scott, K. S. J. Pister, and B. E. Boser, “An ultra-low-energy ADC for smart-dust,” IEEE Journal of Solid-State Circuits, vol. 38, no. 7, pp. 1123–1129, 2003. [21] B. Pangrle, S. Kapoor, “Leakage Power at 90nm and below” EE Times Asia, june 2005. [22] R. E. Suàrez, P. R. Gray, D. A. Hodges “All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques—Part I”, IEEE J. Solid-State Circuits, vol. 10, no. 6, December 1975. [23] J. Lee, I. Park “Capacitor Array Structure and Switch Control for Energy-Efficient SAR Analog-to-Digital Converters”, Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on, pages 236-239 , 18-21 May 2008. [24] M. van Elzakker, E. van Tuijl, P. Geraeds, D. Schinkel, E. Klumperink, B. Nauta “A 1.9uW 4.4fJ/Conversion-step 10b 1MS/s Charge Redistribution ADC”, Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), 3-7 Feb. 2008. [25] R. E. Suàrez, P. R. Gray, D. A. Hodges “All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques—Part II”, IEEE J. Solid-State Circuits, vol. 10, no. 6, December 1975. [26] C.J.B. Fayomi, M.Sawan, G.W. Roberts, “Low-Voltage Analog Switch in Deep Submicron CMOS: Design Technique and Experimental Measurements”, IEICE Trans. Fundamentals, Vol.E89–A, No.4, April 2006. [27] Hao-Chiao Hong, Guo-Ming Lee “A 65-fJ/Conversion-Step 0.9-V 200-kS/s Rail-to-Rail 8-bit Successive Approximation ADC” , IEEE J. Solid-State Circuits, vol. 42, no. 10, October 2007 [28] N. Verma, A. P. Chandrakasan, “An Ultra Low Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes”, IEEE J. Solid-State Circuits IEEE, vol. 42, no. 6, june 2007 [29] A. Tajalli, E. J. Brauer, Y.Leblebici “Ultra-low power 32-bit pipelined adder using subthreshold source-coupled logic with 5 fJ/stage PDP” Microelectronics Journal 40 (2009) 973-978. [30] A. Tajalli, Elizabeth J. Brauer et al., “Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications”, IEEE J. Solid-State Circuits, vol. 43, no.7, pp. 1699-1710, July 2008. [31] A. Tajalli, Y. Leblebici, Elizabeth J. Brauer, “Implementing ultra-high-value floating tunable CMOS resistors”, IEE Electron. Lett. 44(5)(2008) 349-350.

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Appendix I Matlab code for INL and DNL calculation: clc clear all % Basic Ut = 0.026; Vsw = 10*Ut; nn = 1.3; ISS = 1e-9; % tail bias % ADC NF = 8; % num. bit N = 2^NF; % fft points FS = 1; % full scale dV = FS/2^NF; LSB = FS/N; Vr = 1; fs = 2^13; % sampling freq. tck = 1/fs; % sampling period fsh = fs/9; % sampling freq. tsh = 1/fsh; % sampling period % Input signal Vin = 0.7; Vref = FS; Vss = 0; Ain = 0.5; % sin wave amplitude fin = fs/2^12; % sin wave freq start_ramp=0; offset_sin=0.5; Vcin1 = 1; % =1->ramp ; =0->sin (if Vcin2=0) Vcsah = 0; % Vcsah = 0 : SAH is employed g_comp = 10000; % gain of comparator preamplifier noise = 0; % white noise at comparator input off_comp = 0; % offset of comparator comp_val = 0.5; % limit of comparison % Simulation M = 2^12; % sample points ts = 0.001*tck; % sim. time for unit delay %tf = (6 + M)/(fs*2); % sim. final time slope=(1/N)/(4*LSB); stop_sim=1; % DAC capacitances and voltages--mismatched index=1; tr=100; var_cap=0; vfin=0.01; step=vfin/5; while var_cap<=vfin for turns=1:tr Cdac = 0; c0 = 24e-15; for i=1:8 cap_id(i) = c0 * 2^(i-1); cap(i) = c0*2^(i-1) + var_cap*cap_id(i)*randn(1); end Cdac = sum(cap)+c0;

- 60 -

Cdac_id= sum(cap_id)+c0; for j=1:8 Vdac(j)=cap(j)/Cdac; Vdac_id(j)=cap_id(j)/Cdac_id; end % run simulation tout = sim('SAR_ADC_inldnl'); load('o_adc_di.mat'); out_adc_a=o_adc(2,:)'; x_adc=o_adc(1,:)'; load('o_sah_di.mat'); out_sah=o_sah(2,:)'; load('in_sh_di.mat'); in_shape=in_sh(2,:)'; load('o_adc_dig.mat'); y_adc_d=o_adc_dig'; fin=max(size(y_adc_d)); out_adc=zeros(fin,1); for ii=1:fin for jj=1:8 out_adc(ii) = out_adc(ii)+y_adc_d(ii,jj+1)*Vdac_id(jj); end end i=1; while x_adc(i)<(tsh) i=i+1; end l=max(size(out_adc)); out_adc=out_adc(i:l); l1=l-i+1; x_adc=x_adc(1:l1); out_sah=out_sah(1:l1); in_shape=in_shape(1:l1); y=out_adc; x=in_shape; out_ch=[x y]; % dnl and inl ADC output % input y contains the ADC output vs time min_v=min(y); max_v=max(y); x1=min_v:LSB:max_v; l=numel(x1); % histogram h = hist(y,x1); n_elem =histc(y,x1); % cumulative histogram ch = cumsum(h); dnl=0; v_real=zeros(l-1,1);

- 61 -

n=0; n_old=0; x1=x1(1:l-1); for i=1:l-1 if i==1 n=ch(i); n_old=1; v_real(i)=out_ch(n,1); else n_old=n; n=ch(i); v_real(i)=out_ch(n,1)-out_ch(n_old,1); end dnl(i) = (v_real(i)-LSB)/LSB; end misscodes = length(find(dnl<-0.9)); % % calculate inl inl=zeros(size(dnl)); for j=1:size(inl') inl(j)=sum(dnl(1:j)); %INL,j=DNL,0+DNL,1+...+DNL,j % INL=inl(j); end inl_turn(turns)=max(abs(inl)); dnl_turn(turns)=max(abs(dnl)); end INL(index)=mean(inl_turn); DNL(index)=mean(dnl_turn); xax(index)=var_cap; index=index+1; var_cap = var_cap + step; end figure(1) clf subplot(211) plot([1:2^NF],DNL,'--rs','MarkerEdgeColor','k','MarkerFaceColor','g','MarkerSize',10); grid on; title('MAX DIFFERENTIAL NONLINEARITY vs. VARIANCE_ERROR_CAP'); xlabel('VARIANCE_ERROR_CAP'); ylabel('DNL (LSB)'); hold on subplot(212) plot([1:2^NF],INL); grid on; title('MAX INTEGRAL NONLINEARITY vs. VARIANCE_ERROR_CAP'); xlabel('VARIANCE_ERROR_CAP'); ylabel('INL(LSB)'); hold on

- 62 -

Appendix II Matlab code for SNR calculation: clc clear all % Basic Ut = 0.026; Vsw = 10*Ut; nn = 1.3; ISS = 1e-9; % tail bias % ADC NF = 8; % num. bit N = 2^NF; % fft points Nfft = 2^8; FS = 1; % full scale dV = FS/2^NF; LSB = FS/N; Vr = 1; % fs = fsh*9 % clk freq. % tck = 1/fs; % clk period fsh = 2^10; % sampling freq. tsh = 1/fsh; % sampling period fs = fsh*9; % clk freq. tck = 1/fs; % clk period bw=fsh/2; % Input signal Vin = 0.7; Vref = FS; Vss = 0; Ain = 0.5; % sin wave amplitude M =63; % prime number fin = M*fsh/Nfft; % sin wave freq start_ramp=0; offset_sin=0.5; Vcin1 = 0; % =1->ramp ; =0->sin (if Vcin2=0) Vcsah = 0; % Vcsah = 0 : SAH is employed g_comp = 100; % gain of comparator preamplifier noise = 0; % white noise at comparator input off_comp = 0; % offset of comparator comp_val = 0.5; % limit of comparison % Simulation ts = 0.01*tck; % sim. time for unit delay tf = (Nfft+10)*tsh; % sim. final time slope=(1/N)/(3*LSB); stop_sim=0.1; % DAC capacitances and voltages--mismatched index=1; tr=50; var_cap=0; vfin=0.01; step=vfin/5; while var_cap<=vfin var_cap

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for turns=1:tr turns Cdac = 0; c0 = 24e-15; for i=1:8 cap_id(i) = c0 * 2^(i-1); cap(i) = c0 * 2^(i-1)+ var_cap*cap_id(i)*randn(1) ; end Cdac = sum(cap)+c0; Cdac_id= sum(cap_id)+c0; for j=1:8 Vdac(j)=cap(j)/Cdac; Vdac_id(j)=cap_id(j)/Cdac_id; end % run simulation tout = sim('SAR_ADC_SNR',tf); load('o_adc.mat'); y_adc_a=o_adc(2,:)'; x_adc=o_adc(1,:)'; load('o_sah.mat'); y_sah=o_sah(2,:)'; load('in_sh.mat'); y_in_sh=in_sh(2,:)'; load('o_adc_dig.mat'); y_adc_d=o_adc_dig'; fin=max(size(y_adc_d)); y_adc=zeros(fin,1); for ii=1:fin for jj=1:8 y_adc(ii) = y_adc(ii)+y_adc_d(ii,jj+1)*Vdac_id(jj); end end prova=[y_adc_a y_adc]; i=1; while x_adc(i)<(tsh) i=i+1; end l=max(size(y_adc)); y_adc=y_adc(i:l); l1=l-i+1; x_adc=x_adc(1:l1); y_sah=y_sah(1:l1); y_in_sh=y_in_sh(1:l1); new_yad=zeros(1,(Nfft+9)); j=1; k=1; val=y_adc(1); while k <= (Nfft+9)

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val=y_adc(j); new_yad(k)=val; while (y_adc(j)==val && j<max(size(y_adc)) ) j=j+1; end k=k+1; end new_y=zeros(1,(Nfft+9)); j=1; k=1; val=y_sah(1); while k <= (Nfft+9) val=y_sah(j); new_y(k)=val; while (y_sah(j)==val && j<max(size(y_sah)) ) j=j+1; end k=k+1; end diff=zeros(Nfft+9,1); error=0; for j=1:Nfft+9 diff(j)=abs(new_y(j)-new_yad(j)); if diff(j)>LSB error=1; end end y=new_yad; n=2^floor(log2(length(y))); ywin=hann(n).*y(1:n); p=(abs(fft(ywin(1:n),n)))'; k1=3; offset=4; [v h]=max(p(offset:n/2)); v; h=h+offset; p_sq=p.^2; Spow=sum(p_sq(h-1:h+1)); Npow1=sum(p_sq(4:h-k1)); Npow2=sum(p_sq(h+k1:n/2)); Npow=Npow1+Npow2; Npow_db=10*log10(Npow); SNR_turn(turns)=10*(log10(Spow)-log10(Npow)); f=fsh*(1:n)/n; %ENOB = (SNR_turn(turns) - 1.76) / 6.02; %ideal_SNR=6.02*NF+1.76; p_db=log10(p_sq); [v1 h1]=max(p_db(offset:h-k1));

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[v2 h2]=max(p_db(h+k1:n/2)); Hpow=0; if v1>v2 Hpow=v1; else Hpow=v2; end SFDR_turn(turns)=10*(log10(Spow)-Hpow); end SNR(index)=mean(SNR_turn); SFDR(index)=mean(SFDR_turn); xax(index)=var_cap; index=index+1; var_cap = var_cap + step; end figure(1) clf subplot(211) plot(xax,SNR); grid on; title('SNR vs. VARIANCE_ERROR_CAP'); xlabel('VARIANCE_ERROR_CAP'); ylabel('SNR'); hold on subplot(212) plot(xax,SFDR); grid on; title('SFDR vs. VARIANCE_ERROR_CAP'); xlabel('VARIANCE_ERROR_CAP'); ylabel('SFDR'); hold on

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Appendix III Here we can find the simulated trends of INL, DNL, SNR and SFDR when the error standard deviation, due to the non idealities of the circuit, increases.

• Capacitor mismatch:

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• Comparator offset:

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• Non-ideal reference voltage:

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Appendix IV

• Replica bias that creates the gate voltage for the PMOS load and acts as controlling circuit

to mantain the desired voltage swing at the output of the SCL gates.

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Appendix V VHDL code of the logic block: -- ADVance MS model for SAR_real SARVHDL adms_vhdl -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity logicSAR5 is port(clk,clkd,clkn :in std_logic; rst,sc :in std_logic; --reset and start of conversion in_pos, in_neg :in std_logic; sw_pp, sw_pn :out std_logic; sw_sample :out std_logic; sw_ref :out std_logic; sw_gnd :out std_logic_vector (7 downto 0); -- connect single stages to gnd sw_v :out std_logic_vector (7 downto 0); -- connect single stages to Vref conv_value :out std_logic_vector (7 downto 0) ); -- end entity; architecture behav of logicSAR5 is type state_type is (ch_V_1,comp0,comp1,comp2,comp3,comp4,comp5,comp6,comp7,rst_state); signal N_S,C_S_D,C_S : state_type; signal bits : std_logic_vector (7 downto 0); signal in_reg_pos : std_logic; signal in_reg_neg : std_logic; signal sel : std_logic; signal tmp : std_logic; begin ------------------------------------------------------------------------- outc: process(tmp,rst) constant zero : std_logic_vector (8 downto 0) := (others => '0'); begin if (rst='0') then sw_sample <= '0'; sw_ref <= '0'; elsif (tmp='1') then if (C_S=comp1 or C_S=comp0) then sw_sample <= '0'; sw_ref <= '0'; else sw_sample <= '0'; sw_ref <= '1'; end if; elsif (tmp='0') then if (C_S=comp0) then sw_sample <= '1';

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sw_ref <= '0'; else sw_sample <= '0'; sw_ref <= '1'; end if; end if; end process outc; ------------------------------------------------------------------------- tmp <= clk and (not clkd); in_reg_pos <= ( (in_pos and sel) or ( in_neg and (not(sel)) ) ); in_reg_neg <= ( (in_neg and sel) or ( in_pos and (not(sel)) ) ); ------------------------------------------------------------------------- comp: process( rst,clk ) constant zero : std_logic_vector (7 downto 0) := (others => '0'); constant uno : std_logic_vector (7 downto 0) := (others => '1'); constant undef : std_logic_vector (7 downto 0) := (others => 'U'); begin if (rst='0') then -- reset all, discharge all capacitors sw_v <= zero; sw_gnd <= uno; conv_value <= zero; C_S <= rst_state; elsif ( clk'event and clk='1' ) then case C_S is -- sample mode when ch_V_1 => sw_gnd <= zero; -- disconnect V sw_v <= uno; if (sel = '1') then conv_value <= bits; else conv_value <= not(bits); end if; if (sc='0') then --active low C_S <= comp0; -- conversion start just when the start conversion is low,or it --remains in sample state else C_S <= ch_V_1; end if; -- test MSB: Vout=-Vin+Vref/2 when comp0 => sw_v <= zero; sw_gnd <= uno; sw_gnd(7)<= '0'; sw_v(7) <= '1'; --charge Vref on 64C C_S <= comp1; when comp1 => if (bits(6)='0') then sw_gnd(7) <= '1'; sw_v(7) <= '0'; else sw_gnd(7) <= '0'; sw_v(7) <= '1'; end if; sw_v(6) <= '1'; --charge Vref on 32C sw_gnd(6) <= '0'; C_S <= comp2; when comp2 => if (bits(5)='0') then sw_gnd(6) <= '1'; sw_v(6) <= '0'; else sw_gnd(6) <= '0'; sw_v(6) <= '1'; end if; sw_v(5) <= '1'; --charge Vref on 16C sw_gnd(5) <= '0'; C_S <= comp3; when comp3 => if (bits(4)='0') then

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sw_gnd(5) <= '1'; sw_v(5) <= '0'; else sw_gnd(5) <= '0'; sw_v(5) <= '1'; end if; sw_v(4) <= '1'; --charge Vref on 8C sw_gnd(4) <= '0'; C_S <= comp4; when comp4 => if (bits(3)='0') then sw_gnd(4) <= '1'; sw_v(4) <= '0'; else sw_gnd(4) <= '0'; sw_v(4) <= '1'; end if; sw_v(3) <= '1'; --charge Vref on 4C sw_gnd(3) <= '0'; C_S <= comp5; when comp5 => if (bits(2)='0') then sw_gnd(3) <= '1'; sw_v(3) <= '0'; else sw_gnd(3) <= '0'; sw_v(3) <= '1'; end if; sw_v(2) <= '1'; --charge Vref on 2C sw_gnd(2) <= '0'; C_S <= comp6; when comp6 => if (bits(1)='0') then sw_gnd(2) <= '1'; sw_v(2) <= '0'; else sw_gnd(2) <= '0'; sw_v(2) <= '1'; end if; sw_v(1) <= '1'; --charge Vref on C sw_gnd(1) <= '0'; C_S <= comp7; when comp7 => sw_gnd <= zero; -- disconnect V sw_v <= uno; C_S <= ch_V_1; when rst_state => C_S <= ch_V_1; end case; end if; end process comp; -------------------------------------------------------------------- comp_d: process(rst,clkn,clk) constant zero : std_logic_vector (7 downto 0) := (others => '0'); constant uno : std_logic_vector (7 downto 0) := (others => '1'); begin if (rst='0') then sw_pp <= '0'; sw_pn <= '0'; sel <= '1'; bits <= zero; elsif (clkn'event and clkn='1') then -- check the results of the comparisons and -- set the value of the bits of the digital output case C_S is when rst_state => sw_pp <= '0'; sw_pn <= '0'; sel <= '1'; bits <= zero;

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when ch_V_1 => bits <= bits; when comp0 => bits <= zero; bits(7) <= '1'; if (in_pos > in_neg) then sw_pp <= '1'; sw_pn <= '0'; sel <= '1'; else sw_pn <= '1'; sw_pp <= '0'; sel <= '0'; end if; when comp1 => if (in_reg_pos < in_reg_neg) then bits(6) <= '1'; else bits(6) <= '0'; end if; when comp2 => if (in_reg_pos < in_reg_neg) then bits(5) <= '1'; else bits(5) <= '0'; end if; when comp3 => if (in_reg_pos < in_reg_neg) then bits(4) <= '1'; else bits(4) <= '0'; end if; when comp4 => if (in_reg_pos < in_reg_neg) then bits(3) <= '1'; else bits(3) <= '0'; end if; when comp5 => if (in_reg_pos < in_reg_neg) then bits(2) <= '1'; else bits(2) <= '0'; end if; when comp6 => if (in_reg_pos < in_reg_neg) then bits(1) <= '1'; else bits(1) <= '0'; end if; when comp7 =>if (in_reg_pos < in_reg_neg) then bits(0) <= '1'; else bits(0) <= '0'; end if; end case; end if; end process comp_d; end architecture;

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Appendix VI

Verilog-A code of the logic block: // VerilogA for SAR_real, logicBlock, veriloga `include "constants.vams" `include "disciplines.vams" module logicBlock(clk,clkd,rst,in_pos, in_neg,sw_pp, sw_pn, sw_sample,sw_ref, sw_gnd,sw_v,conv_value, N_SO, C_SO, selO,CKO,CKdO ,CKsahO ,regINpO,regINnO ); input clk,clkd,rst; electrical clk,clkd,rst; input in_pos, in_neg; electrical in_pos, in_neg; output sw_pp, sw_pn; electrical sw_pp, sw_pn; output sw_sample; electrical sw_sample; output sw_ref; electrical sw_ref; output [0:7] sw_gnd, sw_v; electrical [0:7] sw_gnd, sw_v; output [0:7] conv_value; electrical [0:7] conv_value; output N_SO; electrical N_SO; output C_SO; electrical C_SO; output selO; electrical selO; output CKO; electrical CKO; output CKdO; electrical CKdO; output CKsahO; electrical CKsahO; output regINpO; electrical regINpO; output regINnO; electrical regINnO ; real in_reg_pos; real in_reg_neg; real reg_sw_vdac; real reg_sw_vin; real reg_sw_sample; real reg_sw_in; real reg_sw_ref; real tmp; real sampOut; real sampData [0:7]; integer swpp, swpn;

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integer swsample; integer swref; integer swgnd [0:7]; integer swv [0:7]; integer convvalue [0:7]; integer fileDesc; integer N_S; integer C_S; integer bits [0:7]; integer sel; integer CK; integer CKd; integer RES; integer regINp; integer regINn; parameter real vth = 0.6; parameter real vthCOMP = 1.1; parameter integer ch_V_1 = 1; parameter integer comp0 = 2; parameter integer comp1 = 3; parameter integer comp2 = 4; parameter integer comp3 = 5; parameter integer comp4 = 6; parameter integer comp5 = 7; parameter integer comp6 = 8; parameter integer rst_state = 9; analog begin /*--------------------------------------------------------------*/ V(sw_pp) <+ swpp; V(sw_pn) <+ swpn; V(sw_sample) <+ swsample; V(sw_ref) <+ swref; V(sw_gnd[0]) <+ swgnd[0]; V(sw_gnd[1]) <+ swgnd[1]; V(sw_gnd[2]) <+ swgnd[2]; V(sw_gnd[3]) <+ swgnd[3]; V(sw_gnd[4]) <+ swgnd[4]; V(sw_gnd[5]) <+ swgnd[5]; V(sw_gnd[6]) <+ swgnd[6]; V(sw_gnd[7]) <+ swgnd[7]; V(sw_v[0]) <+ swv[0]; V(sw_v[1]) <+ swv[1]; V(sw_v[2]) <+ swv[2]; V(sw_v[3]) <+ swv[3]; V(sw_v[4]) <+ swv[4]; V(sw_v[5]) <+ swv[5]; V(sw_v[6]) <+ swv[6]; V(sw_v[7]) <+ swv[7]; V(conv_value[0]) <+ convvalue[0]; V(conv_value[1]) <+ convvalue[1]; V(conv_value[2]) <+ convvalue[2]; V(conv_value[3]) <+ convvalue[3]; V(conv_value[4]) <+ convvalue[4]; V(conv_value[5]) <+ convvalue[5]; V(conv_value[6]) <+ convvalue[6];

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V(conv_value[7]) <+ convvalue[7]; /*-------------------------------------- V(conv_value[0]) <+ bits[0]; V(conv_value[1]) <+ bits[1]; V(conv_value[2]) <+ bits[2]; V(conv_value[3]) <+ bits[3]; V(conv_value[4]) <+ bits[4]; V(conv_value[5]) <+ bits[5]; V(conv_value[6]) <+ bits[6]; V(conv_value[7]) <+ bits[7]; --------------------------------------*/ //tmp output for debug V(N_SO) <+ N_S; V(C_SO) <+ C_S; V(selO) <+ sel; V(CKO) <+ CK; V(CKdO) <+ CKd; V(regINpO) <+ regINp; V(regINnO) <+ regINn; /*--------------------------------------------------------------*/ CK = (V(clk) > vth) ? 1:0; CKd = (V(clkd) > vth) ? 1:0; RES = (V(rst) > vth) ? 1:0; regINp = (V(in_pos) > vthCOMP) ? 1:0; regINn = (V(in_neg) > vthCOMP) ? 1:0; /*--------------------------------------------------------------*/ @(cross(CK-0.5, +1) or cross(RES-0.5, -1)) begin if (RES == 0) C_S = rst_state; else if (CK == 1) C_S = N_S; end /*--------------------------------------------------------------*/ tmp = CK && (!CKd); in_reg_pos = ( (regINp && sel) || ( regINn && (!sel) ) ); in_reg_neg = ( (regINn && sel) || ( regINp && (!sel) ) ); /*--------------------------------------------------------------*/ @(cross(RES-0.5, -1) or cross(CK-0.5, +1) or cross(tmp-0.5, 0)) begin if (RES==0) begin swsample = 0; swref = 0; end else if (C_S==ch_V_1 && tmp==1) begin swsample = 0; swref = 0; end else if (C_S==comp0 && tmp==1) begin swsample = 0; swref = 0; end else begin swsample = reg_sw_sample; swref = reg_sw_ref; end

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end /*--------------------------------------------------------------*/ @(cross(CK-0.5, +1) or cross(RES-0.5, -1)) begin if (RES==0) begin swgnd[0] = 1; swgnd[1] = 1; swgnd[2] = 1; swgnd[3] = 1; swgnd[4] = 1; swgnd[5] = 1; swgnd[6] = 1; swgnd[7] = 1; swv[0] = 0; swv[1] = 0; swv[2] = 0; swv[3] = 0; swv[4] = 0; swv[5] = 0; swv[6] = 0; swv[7] = 0; convvalue[0] = 0; convvalue[1] = 0; convvalue[2] = 0; convvalue[3] = 0; convvalue[4] = 0; convvalue[5] = 0; convvalue[6] = 0; convvalue[7] = 0; N_S = rst_state; end else if (CK==1) begin case (C_S) ch_V_1 : begin reg_sw_sample = 1; reg_sw_vdac = 0; reg_sw_vin = 1; reg_sw_in = 1; reg_sw_ref = 0; swgnd[0] = 0; swgnd[1] = 0; swgnd[2] = 0; swgnd[3] = 0; swgnd[4] = 0; swgnd[5] = 0; swgnd[6] = 0; swgnd[7] = 0; swv[0] = 1; swv[1] = 1; swv[2] = 1; swv[3] = 1; swv[4] = 1; swv[5] = 1; swv[6] = 1; swv[7] = 1; N_S = comp0; if (sel == 1) begin convvalue[0] = bits[0];

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convvalue[1] = bits[1]; convvalue[2] = bits[2]; convvalue[3] = bits[3]; convvalue[4] = bits[4]; convvalue[5] = bits[5]; convvalue[6] = bits[6]; convvalue[7] = bits[7]; end else begin convvalue[0] = !bits[0]; convvalue[1] = !bits[1]; convvalue[2] = !bits[2]; convvalue[3] = !bits[3]; convvalue[4] = !bits[4]; convvalue[5] = !bits[5]; convvalue[6] = !bits[6]; convvalue[7] = !bits[7]; end end comp0 : begin reg_sw_sample= 0; reg_sw_in = 0; reg_sw_ref = 1; swv[0] = 0; swv[1] = 0; swv[2] = 0; swv[3] = 0; swv[4] = 0; swv[5] = 0; swv[6] = 0; swv[7] = 1; //charge Vref-Vcm on 64C swgnd[0] = 1; swgnd[1] = 1; swgnd[2] = 1; swgnd[3] = 1; swgnd[4] = 1; swgnd[5] = 1; swgnd[6] = 1; swgnd[7] = 0; N_S = comp1; end comp1 : begin if (bits[6]==0) begin swgnd[7] = 1; swv[7] = 0; end swv[6] = 1; //charge Vref-Vcm on 32C swgnd[6] = 0; N_S = comp2; end comp2 : begin if (bits[5]==0) begin swgnd[6] = 1; swv[6] = 0; end swv[5] = 1; //charge Vref on 16C swgnd[5] = 0; N_S = comp3; end

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comp3 : begin if (bits[4]==0) begin swgnd[5] = 1; swv[5] = 0; end swv[4] = 1; //charge Vref on 8C swgnd[4] = 0; N_S = comp4; end comp4 : begin if (bits[3]==0) begin swgnd[4] = 1; swv[4] = 0; end swv[3] = 1; //charge Vref on 4C swgnd[3] = 0; N_S = comp5; end comp5 : begin if (bits[2]==0) begin swgnd[3] = 1; swv[3] = 0; end swv[2] = 1; //charge Vref on 2C swgnd[2] = 0; N_S = comp6; end comp6 : begin if (bits[1]==0) begin swgnd[2] = 1; swv[2] = 0; end swv[1] = 1; //charge Vref on C swgnd[1] = 0; N_S = ch_V_1; end rst_state : begin N_S = ch_V_1; end endcase end end /*--------------------------------------------------------------*/ @(cross(RES-0.5, -1) or cross(CK-0.5, -1)) begin if (RES==0) begin swpp = 0; swpn = 0; sel = 1; bits[0] = 0; bits[1] = 0; bits[2] = 0; bits[3] = 0; bits[4] = 0;

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bits[5] = 0; bits[6] = 0; bits[7] = 0; end else if (CK==0) begin case (C_S) ch_V_1 : begin if (V(in_pos) > V(in_neg)) begin swpp = 1; swpn = 0; sel = 1; end else begin swpn = 1; swpp = 0; sel = 0; end bits[0] = 0; bits[1] = 0; bits[2] = 0; bits[3] = 0; bits[4] = 0; bits[5] = 0; bits[6] = 0; bits[7] = 1; end comp0 : begin if (in_reg_pos < in_reg_neg) bits[6] = 1; else begin bits[6] = 0; end end comp1 : begin if (in_reg_pos < in_reg_neg) bits[5] = 1; else begin bits[5] = 0; end end comp2 : begin if (in_reg_pos < in_reg_neg) bits[4] = 1; else begin bits[4] = 0; end end comp3 : begin if (in_reg_pos < in_reg_neg) bits[3] = 1; else begin bits[3] = 0; end end comp4 : begin if (in_reg_pos < in_reg_neg) bits[2] = 1; else begin

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bits[2] = 0; end end comp5 : begin if (in_reg_pos < in_reg_neg) bits[1] = 1; else begin bits[1] = 0; end end comp6 : begin if (in_reg_pos < in_reg_neg) bits[0] = 1; else bits[0] = 0; end endcase end end end endmodule

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