achieve a module product with optimized performance through
TRANSCRIPT
Achieve a Module Product with Optimized Performance through SHF Full Channel DesignSungyao Kao / Section Manager / SE-PCB SI PI, SMART Modular Technologies
Agenda
• Company Profile• Objective• Case Outline• Simulation Topology and Conditions• Key Points of SHF channel design in this case• Geometry Trace Routing Effect to High Speed Channels• Summary
Agenda
• Company Profile• Objective• Case Outline• Simulation Topology and Conditions• Key Points of SHF channel design in this case• Geometry Trace Routing Effect to High Speed Channels• Summary
Founded
Entered BrazilianMemory Market
Taken PrivateBy Silverlake
Listed as a Public Company
AcquiredPenguin ComputingNASDAQ(SGH)
Acquired Artesyn & Inforce Computing
Acquired Cree Led
We are a global leader providing specialty memory solutions to OEM’s focused in vertical markets including:
• Networking
• Telecom
• Aerospace
• Defense/Military
• Server/Storage
• Industrial
• Medical
• Mobile
1988 2011 2018 2021
2002 2017 2019
SGH Key Milestones
SGH Revenue Mix
Brazil (High Volume)
Specialty Compute & Storage Specialty Memory (High Mix)
42%
34%
24%
Doesn’t include Cree LED revenue
SGH Revenue
SGH Global Footprint
SGH’s Diverse Business Units
Founded 1988 June 2018 July 2019 March 2021July 2019
Highly Durable & Reliable DRAM/Flash
Solutions for Industrial Application
Open-Based Solutions for Enterprise, Cloud,Data Centers and HPC
Blade and Systemfor Edge Computing
SBC/SOM Wireless Solutions
for IoT/AIoT
Established global leader in the LED
lighting market with the industry’s
strongest LED brand
Intelligent Platform SolutionsGroup
LED SolutionsGroup
Memory SolutionsGroup
Enabling high performance computing through design,
development, and advanced packaging of leading edge to
legacy memory solutions
Memory Solutions Group
Memory/Storage Product Evolution
SDRAM-PC133 | CPD | DDR1| DDR2 | DISPLAY | FBDIMM | STACKING | DDR3-1337Mhz | DDR3-2133Mhz | DDR4 | DDR5
Memory Product Line
EPD | TSBU | Liner SRAM | CF & PC Card | USB | eUSB | Mini IDE | SCDD | mPCIe | SSD | SATA | eMMC | uSD | M.2 SATA | EDSFF
Flash Product Line
Agenda
• Company Profile• Objective• Case Outline• Simulation Topology and Conditions• Key Points of SHF channel design in this case• Geometry Trace Routing Effect to High Speed Channels• Summary
Objective
• Explore the two factors that have the most significant impact on the SHF Gen-Z Ethernet SI of this case, Via stub and trace angle.
• This report will be explored from the two aspects of the time domain and frequency domain.
• Explanation of Terms
SHF : Super High Frequency (3GHz~30GHz), wave length:10cm~1cm
Ethernet speed: 25Gbps has entered SHF range
BP : Backplane PCB
Agenda
• Company Profile• Objective• Case Outline• Simulation Topology and Conditions• Key Points of SHF channel design in this case• Geometry Trace Routing Effect to High Speed Channels• Summary
Case Outline
• The entire SHF channel is composed of GEN-Z board and Backplane board.
• We have done GEN-Z board routing with B/B via, so there is no issue with via stub.
• Since customer’s backplane PCB does not use B/B via but uses PTH is affected by the stub in the initial stage of simulation, after dig out the issue caused by via stub, we have support to built back-drill model to match real PCB structure and solve this issue, so we will discuss this part in particular.
A high-speed processor
expansion bus standard,
offering low latency, high
speed, direct memory access
connectivity between devices
of different instruction set
architectures
Agenda
• Company Profile• Objective• Case Outline• Simulation Topology and Conditions• Key Points of SHF channel design in this case• Geometry Trace Routing Effect to High Speed Channels• Summary
Design Software Used
• Simulation (Ansys)1. Ansys HFSS 2021/R12. Ansys Siwave 2021/R13. Ansys Electronics Desktop 2021/R1
• Simulation (3rd-party)- Synopsis Hspice
• Layout (3rd - party)- Cadence Allegro
Always Perform System-Level Simulation Completely
Power Integrity - IR-Drop
- Z-parameter analysis - Decoupling capacitor
optimization …
Signal Integrity - Impedance analysis- Waveform analysis
-S-parameter analysis- Cross-talk analysis
...
Highly Durable & Reliable DRAM/Flash
Solutions for Industrial Application
Interactionbetween increased signals
Interaction betweenincreased system hardware
components
The Impact of the Discontinuity of the Module on System
~43 ohm
~17 ohm
~11.5 ohm
Simulation Topology and Conditions
IC TX Driver model
TX die model TX Substrate Package model
Gen-Z PCB trace model
Ethernet signals on SMART PCB(please see page7 for details)
RX die model
IC RX Receiver model
Controller models
Gen-Z connector model
Backplane connector model
Backplane PCB trace model
RX Substrate Package model
Customer’s Backplane PCB(please see page7 for details)
Controller models
• Data rate: 25Gb/s• Data pattern: PRBS31• Data stream Qty: over 1,000,000 bits• All information of IC, substrate and PCB material are included.
Two PCB Database
• 16-layers/85Ohm±10%/1.579 mm• Ek=3.5 , Ef=0.011 , high Tg• Used B/B via routing to eliminate stub
effect in high speed.
• 10-layers/85Ohm±10%/2.647 mm• Ek=3.4~3.5 , Ef=0.011 , high TgUsed back-drill to eliminate stub effect,
via routing is through-hole, therefore, SI modeling to back-drill is necessary.
Gen-Z BP
Agenda
• Company Profile• Objective• Case Outline• Simulation Topology and Conditions• Key Points of SHF channel design in this case• Geometry Trace Routing Effect to High Speed Channels• Summary
Via Stub – Stub Resonance
• A dangling Via stub acts as an open stub resonator, similar to a series LC resonator, at a quarter wavelength, the impedance turns into a short impedance; therefore, the insertion loss at that frequency becomes the maximum.
• Depending on the Q value, the loss at other frequencies can be significant as shown in the dB(S21) plot.
Via Stub and Back-Drilling on BP
VIA stub
Backdrill
Stackup
- The via stub resonance can be removed or pushed up to a higher frequency by back-drilling the via.
- Signal trace is routed on L8_HS and Bottom- VIA stub is from Top to L7_GND
Via Stub Effect to SHF Gen-Z High Speed Channels - Time
Just Channel @ 25Gb/s
Via inserted between @ 25Gb/s
Via Stub Removed @ 25Gb/s
Use a Backdrill to remove Via stub
Only consider with SI on channel w/o any via
Maintain a structure that originally contained Via + Via stub (failed)
Via Stub Effect to SHF Gen-Z High Speed Channels – S21
Just Channel @ 25Gb/s
Via inserted between @ 25Gb/s
Via Stub Removed @ 25Gb/s
Only consider with SI on channel w/o any via
Maintain a structure that originally contained Via + Via stub (failed)
Use a Backdrill to remove Via stub
How to build via back-drill in layout for simulation model?
• Step 1: Define B/B via• Step 2: Add new via definitions (e.g. TEST)
• Step 3: Select the via that you would like to modify• Step 4: Replace old via with new via step1
step2
step3step4Siwave 3rd-party
Insertion loss caused by BP’s VIA stub
VIA Stub Resonance causes eye-diagram be shrank (page 16)
No bad S21 so eye-diagram is ok (page 16)
Electrical Radiation in Via stub and Backdrill
Electric Field @17.6 GHzin Stub location
Signals are on internal Layer 8
Via stub Back-drill
No radiation
Improvement to Eye size of channel
No Backdrill
With Backdrill
Agenda
• Company Profile• Objective• Case Outline• Simulation Topology and Conditions• Key Points of SHF channel design in this case• Geometry Trace Routing Effect to High Speed Channels• Summary
SHF Routing by ARC
Original 45 degree routing Change to Arc routing
Eye Contour Improvement
Agenda
• Company Profile• Objective• Case Outline• Simulation Topology and Conditions• Key Points of SHF channel design in this case• Geometry Trace Routing Effect to High Speed Channels• Summary
Summary
• The implementation of modular design must consider the complete channel characteristic.
• Considering the behavior of high-speed channels, via stub and trace routing are very important to SI result.
• Via stubs act as a series LC resonator, adding significant loss to the channels, that can be minimized by back-drill the via stubs.
• ARC routing is not a panacea and must be used carefully according to the case.
Reference
• Designed Solutions Driven by Innovation, SGH Marketing, 2021• UltraScale Architecture GTY Transceivers IBIS-AMI Signal Integrity User Guide, March
25, 2016• PCB Via to Trace Return Loss Optimization for >25Gbps Serial Links, Ji Zhang, Jane
Lim, Wei Yao, Kelvin Qiu, Rick Brooks, Cisco System Inc, 2014 IEEE.• High Frequency Measurements and Noise in Electronic Circuits, Seminar by Douglas
C. Smith, http://www.dsmith.org.