acer flamingo l1: l2: (y) mobile cpu pcb p/n: revision · place near each pin no stuff: caps are...
TRANSCRIPT
http://mycomp.su/x/
Acer Flamingo
CLK GEN.ICS
Almador-MGMCH
PCI BUS
Project code:PCB P/N:
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PAGE:03
L8:
L3:
L7:
L2:
L6:
L5:
L1:
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L4:
LPC BUS
SERIAL FINGERPRINTER
PAGE:27PAGE:28
PRINTERPAGE:28
ICH3-M
PAGE:15~17
LAN82562EM
PAGE:20
Card
INT.SPKR
LINE OUT
!"#$%" Daughter
PAGE:25
MODEM
PAGE:19
VR
MIC
ALC200
LINE IN
AC'97 CODEC
PAGE:23
AC-Link
HDDPAGE:18
CDROMPAGE:18
SECONDARY EIDE
PAGE:19
USB 1.0X2
CARDBUSSLOT A,B
PAGE:22PAGE:21
OZ6933TCARDBUS
POWER SWMIC2564A
version:PAGE:11~12
MEM BUS
PAGE:7~9
PAGE:10
SO-DIMM*2
HOST BUS
Mobile CPUTualatinverson :
PAGE:4~5
CMOSBAT
PAGE:28
TOUCH PAD
REVISION:
Version : A4
Version :
PRIMARY EIDE
PAGE:22
SIOSMsC
LPC47N267PAGE:27
PS/2 CONNPAGE:26
INT. KBPAGE:26
L9:
L10:
HUB I/F
KBC
PAGE:26
M38859FWH
PAGE:29
82802ABCONN.
LPCDEBUG
PAGE:29
PAGE:13CRT
LCDPAGE:13
AGP 4XVGA
ATI MobilityM6S
Signal 1(X)
GND
Signal 2 (Y)
Signal 3 (X/Y)
GND
POWER
Signal 4(weak)
Signal 5 (X)
GND
Signal 6 (Y)
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INPUTS
DCBATOUT
+5VSB
OUTPUTS
DC/DC&CHARGER
MAX1632/MAX1772Switching Power
+3VSB
+1.8VSB
+3.3V
+5V
+3.3V
+12V
CD+5V
AD+
PAGE:32
INPUTS
+VCC_CORE
CPU DC/DC
OUTPUTS
Switching Power
+VCCT
DCBATOUT
PAGE:30/31
MAX1718/MAX1714
+1.8V
PAGE:31/32
+5V
+3.3V
OTHER DC/DC
INPUTS OUTPUTS
+1.5V
MAX1644/MAX1792
LAN_+3.3V
+5VSB
MAX8863
DOCK V QSW
DOCK V TV OUT
RAM BUFFER(2*32bit)*2
+6V
ATA100
HOT PLUG
FLOPPYPAGE:18PAGE:27
FIR
(133M)
(133M)
(66M)
(66M)
(33M)
(33M)
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http://mycomp.su/x/
Acer Flmanigo History
Rev. 0.1 : Jun. /1 / 2001 for PCB team placement
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http://mycomp.su/x/
PLACE NEAR EACH PIN
No stuff:caps are internalto CK-TITAN.
CPU & MEMORY Freq. Selection
Filtering CKT for48MHz power plane
PIN 2 WITH 10K
SC10P
SC10P2MR3
1/2
CLOSE TO CLK GEN
CGANGE TOICS 950806AF
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http://mycomp.su/x/
2/4
CPU
Place near CPU
CPU1/4
Layout note:Place CPU_RST# Resistor < 0.1" from CPU
10pF
GHI#:internal pullup to VCCT
FOR NOISEREDUCTION
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http://mycomp.su/x/
CPU4/4
CPU3/4
Decouping Recommendation
0.47uF * 24
10uF / 6.3V * 10
VCCT
1uF * 10
VCC_CORE
Underneath ballson solder side
On the peripheralnear balls
Place close toprocessor forall
Use 2-3 vias per pad for reducedinductance during layout
Placement should be nearprocessor for all
Use 2 vias per pad for reducedinductance during layout
Almador-M Checklist Ver. 0.5 8/28
Freeza
0.1uF * 24
10uF / 10V * 10
1uF * 10
Kodiak Ver. 0.5
10uF / 6.3V * 12
1uF * 10 + 2 * NS
10uF / 6.3V * 10 + 6 * NS
Bulk Caps
Bulk Caps
220uF / 2.5V * 8
220uF / 2.5V * 2
150uF / 4V * 12 + 2 * NS
150uF / 4V * 5 + 1 * NS
Place resistorsbetween GMCHand CPU
GTLREF( 2/3 +VCCT)
Place caps near CPU
CMOSREF
Place caps near CPU
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Place near GMCH
SM_RCOMP = 1/2 PCB impedance
DVO_RCOMP = PCB impedanceHUB_RCOMP = PCB impedanceAGP_RCOMP = PCB impedance
Almador checklist
AGP_REF used asDVO_REF for DVO device
SCD1U10V2MX
10R3 10R3
SC10P SC10P
Have some pin difference between A2 and A3 stepping
SM_OCLK = 0.15INCH
GTL_RCOMP =80 ohm impedance
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Pull-up requiredfor ext. AGP GFXand int. DVO GFX
Connect pin AE20, G24(VSSA_DPLL[0,1]) tothe respective decoupling caps of pinAC20, F25(VCCA_DPLL[0,1])
Pull-up 10K to +5VRUN
Pull-up 100K to 1.5VRUN
DDC2DAT
DVO_INTR#
Pull-up 10K to +3VRUN
DDC2CLK
DDC1CLKDDC1DAT
Pull-up 2.2K to +5VRUN
Pull-up/down requiredif DVOA notimplemented.
Non-5V tolerant,Q-Switch required for5V support
Pull-down 100K to GND
I2CDATA
Pull-up 100K to 1.5VRUN
I2CCLK
DVO_CLKIN
DVO_FIELD
Pull-down 2.2K to GND
DVOA_D0 0 = 200MHz
Pull-up 2.2K to V1.5S
Int. P/U
Int. P/D
Int. P/D
Pull-down 2.2K to GND1 = 133MHz
Int. P/U
Pull-up 2.2K to V1.5S
1 = Single ended term.
1 : IOQD = 8
0 = Dual ended term.DVOA_D6
1 = MOBILE
0 = DESKTOPDVOA_D5
0 : IOQD = 1DVOA_D1
AGP device attached
Strapping Option for SW detection of AGP or DVO device
DVO device attached
AGP_PARPull-up 8.2K to 1.5VRUN
Pull-down 2.2K to GND
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http://mycomp.su/x/
Decouping Recommendation
0.1uF * 20
68uF / 10V * 5
1uF * 40
V1.2S_GMCH
Distribute as close as possibleto GMCH-M processor Quadrant
Almador-M Checklist Ver. 0.5 8/28
Freeza
22uF / 20V * 1
1uF * 20
Kodiak Ver. 0.5
Bulk Caps
150uF / 4V * 10 + 1 * NS
150uF / 4V * 5 + 1 * NS
DecouplingCaps
V1.2S_GMCHCOREDecouplingCaps 0.1uF * 40
68pF * 1Close to VDD_LM, near pins AE15and AE16 on Almador
Bulk Caps
68pF * 1 68pF * 1
V1.5S_GMCH
Bulk Caps
Bulk Caps
Bulk Caps
V1.8S_GMCH
V3_GMCH
DecouplingCaps
DecouplingCaps
DecouplingCaps
0.1uF * 9
82pF * 4
0.1uF * 4 + 4
82pF * 2
82pF * 4
0.1uF * 12 + 2
Distribute as close as possibleto GMCH-M AGP/DVO Quadrant
Distribute as close as possibleto GMCH-M Local Memory Quadrant
Additional 4* 0.1uF shall be distributedas close as possible to VCCPCMOS_LM
Additional 4* 0.1uF shall be distributedas close as possible to IO Quadrant
Distribute as close as possible toGMCH-M System Memory Quadrant
0.1uF * 9
82pF * 4
82pF * 20.1uF * 4 + 2
22uF / 20V * 2
0.1uF * 12 + 282pF * 422uF / 20V * 2
0.1uF * 20
100uF / 10V * 1
0.1uF * 20
100uF / 10V * 2
0.1uF * 80.01uF * 3
100uF / 10V * 1
10uF / 10V * 1
0.1uF * 2
CHECK
SYSTEM MEMORYREF 0.55V
HUB INTERFACE REF1/2*1.8V
Layout Note:Place divider pair in middle of bus.Place capacitors near GMCH.
Place capacitor near GMCH.
Place C near AE16 and AE15 on GMCH
SC470P50V3JN
56D2R3F
(1.8A) (800mA)
(1A)
(500mA)
(250mA)
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http://mycomp.su/x/
NOTE: NETWORK RESISTOR NEAR GMCH < 1.5 inch.
(Reverse Type)(Normal Type)
MOLEX 54534-144H=5.2mm
MOLEX 54432-144H=4.0mm
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36
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TGT;''
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TGT;43
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TGT;2
TGT;24
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http://mycomp.su/x/
DDC_ID2???----GPIO???
0
1
1.25
1.0
0
test1
0.5
1
SLE1SLE0
0
Spread %
1
0For AGP Timing Tunning
P_IRQA#AD16AGP_REQ#AGP_GNT#
Dummy
SPECTRUM NO SPECTRUM
SSIN
SSOUT
MK1705
R163
BCY1
SS_SEL0
SS_SEL1
FLOATING
FLOATING
20KR2_GND
20KR2_GND
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
MOUNT
33R3
SC1000P50V
TABLE
TABLE
1:1KR20:0R2
33R3
PULL UP 10KR2
PCI/AGP
AGP 2X
AGP 4X
DAC2
SSC
CLK
DAC1
TMDS
LVDS
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PCI BUS
CLK termination close to ICH
CPU Interface
HUB Interface
INTERRUPT Interface
EEPROMI/F
LAN I/F
RCOMP should be 2/3board impedance
SC-3062
PLACE RCOMP resistor within 0.5"of ICH pad using a thick trace
HUB INTERFACE LAYOUTRoute signals with 5/20 trace/space routing. Signals must match +/- 0.1" of HUB_STB/STB#signals.
(for use if CPU unableto support DPSLP#)
HUB I/F VSWING VOLTAGE
LAYOUT NOTE:Place divider pairin middle of bus.
SystemManagementI/F
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PCI I/F Pullups Interrupt I/F Pullups
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ICH3 Integrated Pull-up and Pull-down Resistors
FM-1882 P4-1,2
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AC97 AC terminations
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AC_SDOUT
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If this signal is sampled low (default due toweak int. pull-down), the termination schemewill be set to source. If this signal issampled high (via an ext. pull-up to Vcc1_8),the termination scheme will be set toparallel.
NO REBOOT
DPRSLPVR
POWER
FM-1882ICH3 H/W Pin Straps
Kodiak Ver. 0.7b
SAFE MODE
RSM
PWR
HUB
PWR
PCI PWR
ICH3-M
From Kris 8/10
System designers should include a placeholderfor a pull-down resistor on EE_DOUT but donot populate the resistor.
This signal has a weak int. pull-down. Ifthe signal is sampled high, the ICH3 willset the CPU speed strap pins for safemode.
IDE
PWR
VSS
Rising Edgeof PWROK
EE_DOUT Reserved
*Within a given well, 5VREF needs to beup before the corresponding 3.3V rail
CORE PWR
This signal has a weak int. pull-up. If thesignal is sampled low, this indicates thatthe system is strapped to the "TOP-SWAP"mode(ICH3 will invert A16 for all cyclestargeting FWH BIOS spacing). Note that SWwill not be able to clear the Top-Swap bituntil the system is rebooted w/o GNT[A]#being pulled down.
SPKR Rising Edgeof PWROK
GNT[A]#
This signal has a weak int. pull-down. If thesignal is sampled high, this indicates thatthe system is strapped to the " No Reboot "mode (ICH3 will disable the TXO Timer systemreboot feature).
USB
PWR
Rising Edgeof PWROK
FPET7 Elec. P3-62
HUB INTERFACETERMINATIONSCHEME(PARALLEL vs.SOURCE)
ICH3-M
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Decouping Recommendation
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VCC_IO_CPU
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