acer aspire 5235 5535 5735 - wistron cathedral peak ii

5

4

3

2

1

Cathedral Peak II Block DiagramD

Project code: 91.4K801.001 PCB P/N : 48.4K801.0SC REVISION : 08219-SCSYSTEM DC/DCTPS5112535D

CLK GEN.ICS 9LPRS365BKLFT (71.09365.A03) RTM 875N-606-LFT (71.00875.C03) 3

Mobile CPUPenryn 4794, 5

THERMAL EMC210221TOP VCC

PCB STACKUP

INPUTS

OUTPUTS5V_S5

DCBATOUT 3D3V_S5

DDR2 DIMM1667/800 MHz12

HOST BUS 667/800MHz

667/800/[email protected]

CRT LCD

S S

15

CantigaAGTL+ CPU I/F DDR Memory I/F INTEGRATED GRAHPICS LVDS, CRT I/F

SYSTEM DC/DCTPS51124INPUTSDCBATOUT 1D8V_S3 1D05V_S0

GND BOTTOM

14

37

OUTPUTS

DDR2 DIMM2667/800 MHz13C

667/800MHz

6,7,8,9,10,11

RT90261D8V_S3

36DDR_VREF_S0C

INT.MIC16

X4 DMI 400MHz

C-Link0

DDR_VREF_S3

CodecALC26828

ICH9MAZALIA6 PCIe ports PCI/PCI BRIDGE ACPI 2.0 4 SATA 12 USB 2.0/1.1 ports ETHERNET (10/100/1000MbE) High Definition Audio LPC I/F

RT9018A

361D5V_S0

PCIex1

LAN Giga LAN88E8071 25

1D8V_S3

TXFM26

RJ4526

CFXCORE DC/DCISL6263 38 OUTPUTS VGFXCORE0.7~1.25V

MIC In29

PCIex1 PCIex1

New card27

PWR SW TPS2231

INPUTS 27DCBATOUT

Mini CardKedron a/b/g/n

29B

OP AMPAPA2057 29

27

Serial Peripheral I/F Matrix Storage Technology(DO) Active Managemnet Technology(DO)

CPU DC/DCISL6266A 34B

LPC BUS BIOSWinbond W25X16 16M Bits

INT.SPKR29

INPUTS

OUTPUTS VCC_CORE_S00.35~1.5V

KBCENE3310

LPC31

DCBATOUT

Line Out (NO SPDIF)

RJ11

MODEM MDC Card23

17,18,19,20

30

DEBUG 31 CONN.

USBBlue Tooth 23 (USB) Camera (USB) 14

Launch Buttom 16

CHARGERBQ24745 INPUTS 39 OUTPUTS BT+DCBATOUT

Touch Pad 30

INT. KB 30 MS/MS Pro/xD /MMC/SD5 in 1

SATAHDD SATA 22A

23

24

omDate: Wednesday, July 16, 2008

USB 3 Port

USB

ODD SATA

he

165 4 3 2

Size A3

Document Number

xa in

Launch Board LED Board

BLOCK DIAGRAM

f@

Title

ho

SATA

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

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22

Wistron Corporation

Cathedral Peak IISheet1

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CardReader Realtek RTS5158E 24

DCBATOUT

A

Rev

SC

ASignal HDA_SDOUT Usage/When Sampled Comment

Bpage 92

ICH9M Functional Strap Definitions ICH9 EDS 642879 Rev.1.5

ICH9M Integrated Pull-up and Pull-down ResistorsICH9 EDS 642879

C

E CantigaDchipset and ICH9M I/O controller Hub strapping configurationRev.1.5Pin Name CFG[2:0]

Montevina Platform Design guide 22339page 218 Strap Description FSB Frequency Select Configuration 000 = FSB1067 011 = FSB667 010 = FSB800 others = Reserved

0.5

XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 PCIE Port Config1 bit1, pulled low.When TP3 not pulled low at rising edge Rising Edge of PWROK of PWROK,sets bit1 of RPC.PC(Config Registers: offset 224h). This signal has weak internal pull-down PCIE config1 bit0, Rising Edge of PWROK. PCIE config2 bit2, Rising Edge of PWROK. Reserved This signal has a weak internal pull-down. Sets bit0 of RPC.PC(Config Registers:Offset 224h) This signal has a weak internal pull-up. Sets bit2 of RPC.PC2(Config Registers:Offset 0224h) This signal should not be pulled high.

SIGNALCL_CLK[1:0] CL_DATA[1:0] CL_RST0# DPRSLPVR/GPIO16 ENERGY_DETECT HDA_BIT_CLK HDA_DOCK_EN#/GPIO33 HDA_RST# HDA_SDIN[3:0] HDA_SDOUT HDA_SYNC GLAN_DOCK# GPIO[20] GPIO[49] LDA[3:0]#/FHW[3:0]# LAN_RXD[2:0] LDRQ[0] LDRQ[1]/GPIO23 PME# PWRBTN# SATALED#SPI_CS1#/GPIO58/CLGPIO6 GNT[3:0]#/GPIO[55,53,51]

Resistor Type/ValuePULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-DOWN 20K PULL-DOWN 20K PULL-DOWN 20K PULL-DOWN 20K

4

HDA_SYNC GNT2#/ GPIO53 GPIO20 GNT1#/ GPIO51

CFG[4:3] CFG8 CFG[15:14] CFG[18:17] CFG5 CFG6

Reserved

40 = DMI x2 1 = DMI x4 (Default) 0= The iTPM Host Interface is enabled(Note2) 1=The iTPM Host Interface is disalbed(default) 0 = Transport Layer Security (TLS) cipher suite with no confidentiality 1 = TLS cipher suite with confidentiality (default) 0 = Reverse Lanes,15->0,14->1 ect.. 1= Normal operation(Default):Lane Numbered in order 0 = Enable (Note 3) 1= Disabled (default) 00 = Reserve 10 = XOR mode Enabled 01 = ALLZ mode Enabled (Note 3) 11 = Disabled (default) 0 = Dynamic ODT Disabled 1 = Dynamic ODT Enabled (Default) 0 = Normal operation(Default): Lane Numbered in Order

DMI x2 Select iTPM Host Interface Intel Management engine Crypto strap

ESI Strap (Server Only) ESI compatible mode is for server platforms only. Rising Edge of PWROK This signal should not be pulled low for desttop and mobile. Top-Block Swap Override. Rising Edge of PWROK. Sampled low:Top-Block Swap mode(inverts A16 for all cycles targeting FWH BIOS space). Note: Software will not be able to clear the Top-Swap bit until the system is rebooted without GNT3# being pulled down. Controllable via Boot BIOS Destination bit (Config Registers:Offset 3410h:bit 11:10). GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC. Sample low: the Integrated TPM will be disabled. Sample high: the MCH TPM enable strap is sampled low and the TPM Disable bit is clear, the Integrated TPM will be enable.

CFG7

GNT3#/ GPIO55

The pull-up or pull-down active when configured for native CFG9 GLAN_DOCK# functionality and determined by LAN controller

PCIE Graphics Lane

GNT0#: SPI_CS1#/ GPIO58

Boot BIOS Destination Selection 0:1. Rising Edge of PWROK. Integrated TPM Enable, Rising Edge of CLPWROK

PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 15K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-UP 20K PULL-DOWN 15KL_DDC_DATA Local Flat Panel (LFP) Present SDVO_CTRLDATA SDVO Present CFG20 CFG19 DMI Lane Reversal CFG16 FSB Dynamic ODT CFG10 CFG[13:12] PCIE Loopback enable XOR/ALL

SPI_MOSI

3GPIO49 SATALED# SPKR

DMI Termination Voltage, The signal is required to be low for desktop Rising Edge of PWROK. applications and required to be high for mobile applications.

3

PCI Express Lane Reversal. Rising Edge of PWROK. No Reboot. Rising Edge of PWROK.

Signal has weak internal pull-up. Sets bit 27 of MPC.LR(Device 28:Function 0:Offset D8) If sampled high, the system is strapped to the "No Reboot" mode(ICH9 will disable the TCO Timer system reboot feature). The status is readable via the NO REBOOT bit. This signal should not be pull low unless using XOR Chain testing.

1 = Reverse Lanes DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3) DMI x2 mode[MCH -> ICH]:(3->0,2->1) Digital Display Port 0 = Only Digital Display Port (SDVO/DP/iHDMI) or PCIE is operational (Default) Concurrent with PCIe 1 =Digital display Port and PCIe are operting simulataneously via the PEG port 0 =No SDVO Card Present (Default) 1 = SDVO Card Present 0 = LFP Disabled (Default) 1= LFP Card Present; PCIE disabled

SPI_MOSI SPI_MISO SPKR TACH_[3:0] TP[3] USB[11:0][P,N]

TP3

XOR Chain Entrance. Rising Edge of PWROK.

GPIO33/ HDA_DOCK _EN#

Flash Descriptor Sampled low:the Flash Descriptor Security will be Security Override Strap overridden. If high,the security measures will be Rising Edge of PWROK in effect.This should only be enabled in manufacturing environments using an external pull-up resister.

2SMBusEMC2102

NOTE: 1. All strap signals are sampled with respect to the leading edge of the (G)MCH Power OK (PWROK) signal. 2. iTPM can be disabled by a 'Soft-Strap' option in the Flash-decriptor section of the Firmware. This 'Soft-Strap' is activated only after enabling iTPM via CFG6. Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time.

2

Thermal

USB TableUSB

KBCBAT_SCL

PCIE RoutingLANE1 LANE2 LANE3 LANE4 LANE5 LANE6 LAN MARVELL 88E8071 MiniCard WLAN NC NC NewCard NC

Pair 0 1 2 3 4 5 6 7 8 9 10 11

Device USB1 NC USB2 NC USB3 Bluetooth NC MINIC1 WEBCAM NEW1 Card Reader NCSMBC_ICH

BATTERY

1

ICH9M

1Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title

9LPRS365BKLFT DDRSize A3 Date:

ReferenceDocument Number Rev

Cathedral Peak IIWednesday, July 16, 2008 Sheet 2 of 43

SC

A

B

C

D

E

A

B

C

D

E

3D3V_S0 3D3V_S0

3D3V_S0

-13D3V_48MPWR_S0 3D3V_CLKPLL_S0 C190 SC4D7U6D3V3KX-GP C183 SC1U16V3ZY-GP EC58 SCD1U16V2ZY-2GP C463 SCD1U16V2ZY-2GP C235 SC4D7U10V5ZY-3GP C459 SCD1U16V2ZY-2GP C465 SCD1U16V2ZY-2GP C231 SCD1U16V2ZY-2GP

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

C246 SCD1U16V2ZY-2GP

C195 SC4D7U10V5ZY-3GP




1

1 R146 2 0R0603-PAD

1 R197 2 0R0603-PAD C462SCD1U16V2ZY-2GP

3D3V_CLKGEN_S0

1 R157 2 0R0603-PAD C234SCD1U16V2ZY-2GP


DY2

DY2

DY

DY2

DY2

DY2

DY

DY2

2

2

2

2

2

2

2

2

2

4

2

4

3D3V_CLKGEN_S0

PCLK_ICH

CLK_ICH14

1

2

DY

2 4 16 9 46 62 23 VDD96_IO VDDPLL3_IO VDDSRC_IO VDDSRC_IO VDDSRC_IO VDDCPU_IO VDDREF VDD48 VDDPCI VDDSRC VDDCPU VDDPLL3 19 27 43 52 33 56CLK_CPU_BCLK_1 CLK_CPU_BCLK_1# CLK_MCH_BCLK_1 CLK_MCH_BCLK_1# CLK_PCIE_LAN_R CLK_PCIE_LAN#_R CLK_PCIE_NEW_R CLK_PCIE_NEW#_R CLK_PCIE_ICH_1 CLK_PCIE_ICH_1# R160 1 R166 1 R167 1 R169 1 R173 1 R176 1 R182 1 R181 1 R195 1 R194 1

EC57 SC5P50V2CN-2GP

1

1EC55 SC5P50V2CN-2GP

CLK48_ICH EC137 SC5P50V2CN-2GP 3D3V_48MPWR_S0

3D3V_CLKPLL_S0

DYU19

DY

SB

CL=20pF0.2pFC177 SC33P50V2JN-3GP GEN_XTAL_IN 1 2 R154 2

2

DY

1 10MR2J-L-GP 1 0R0402-PADGEN_XTAL_OUT RN51

CPUT0 CPUC0 CPUT1_F CPUC1_F CPUT2_ITP/SRCT8 CPUC2_ITP/SRCC8

61 60 58 57 54 53 51 50 48 47 41 42 40 39 37 38 34 35 31 32 28 29 24 25 20 21

2 0R0402-PAD 2 0R0402-PAD 2 0R0402-PAD 2 0R0402-PAD 2 0R0402-PAD 2 0R0402-PAD 2 0R0402-PAD 2 0R0402-PAD 2 0R0402-PAD 2 0R0402-PAD

CLK_CPU_BCLK 4 CLK_CPU_BCLK# 4 CLK_MCH_BCLK 6 CLK_MCH_BCLK# 6 CLK_PCIE_LAN 25 CLK_PCIE_LAN# 25 CLK_PCIE_NEW 27 CLK_PCIE_NEW# 27 CLK_PCIE_ICH 18 CLK_PCIE_ICH# 18

CPU NB LAN New Card SB DMI3

X3 X-14D31818M-44GP

2 R15324 18 4,7

3 2 4 SRN33J-5-GP-U 3

X1 X2

1

82.30005.9512 1 2GEN_XTAL_OUT_R

CLK48_5158E CLK48_ICH CPU_SEL0

1 2 2 R156 1

CLK48 17

USB_48MHZ/FSLA SRCT7/CR#_F SRCC7/CR#_E PCI_STOP# CPU_STOP# SRCT6 SRCC6 SRCT10 SRCC10 SRCT11/CR#_H SRCC11/CR#_G SRCT9 SRCC9 PCI0/CR#_A PCI1/CR#_B PCI2/TME PCI3 PCI4/27_SELECT PCI_F5/ITP_EN SRCT4 SRCC4 SRCT3/CR#_C SRCC3/CR#_D SRCT2/SATAT SRCC2/SATAC FSLB/TEST_MODE REF0/FSLC/TEST_SEL NC#55 GND GNDSRC GNDSRC GNDSRC GNDCPU GND GND48 GNDPCI GNDREF 27MHZ_NONSS/SRCT1/SE1 27MHZ_SS/SRCC1/SE2 SRCT0/DOTT_96 SRCC0/DOTC_96

C176 SC33P50V2JN-3GP3

2K2R2J-2-GP

18 PM_STPPCI# 18 PM_STPCPU# 3D3V_S0 4,7 CPU_SEL2 3D3V_S0 12,13,20 SMBC_ICH 12,13,20 SMBD_ICH

45 44

7 6 63

SCLK SDATA CK_PWRGD/PD#

RN59 SRN10KJ-6-GP TPAD30 TP158 7

2 R155

DY

1 10KR2J-3-GP

18 CLK_PWRGD

8 7 6 5

CLK_MCH_OE#

R150 1 DY 2 475R2F-L1-GP

PCLKCLK2 CPU_SEL2_R PCLKCLK4 PCLKCLK5 30 18 PCLK_KBC PCLK_ICH RN17 1 2

PCLKCLK0 PCLKCLK1 PCLKCLK2 PCLKCLK3 PCLKCLK4 PCLKCLK5

4 3

8 10 11 12 13 14

1 2 3 4

CLK_PCIE_MINI_1 CLK_PCIE_MINI_1# CLK_MCH_3GPLL_1 CLK_MCH_3GPLL_1# CLK_PCIE_SATA_1 CLK_PCIE_SATA_1# DREFSSCLK_1 DREFSSCLK#_1 DREFCLK_1 DREFCLK#_1

R192 1 R193 1 R180 1 R184 1 R174 1 R177 1 R168 1 R171 1 R158 1 R161 1

2 0R0402-PAD 2 0R0402-PAD 2 0R0402-PAD 2 0R0402-PAD 2 0R0402-PAD 2 0R0402-PAD 2 0R0402-PAD 2 0R0402-PAD 2 0R0402-PAD 2 0R0402-PAD

CLK_PCIE_MINI1 27 CLK_PCIE_MINI1# 27 CLK_MCH_3GPLL 7 CLK_MCH_3GPLL# 7 CLK_PCIE_SATA 17 CLK_PCIE_SATA# 17 DREFSSCLK 7 DREFSSCLK# 7 DREFCLK 7 DREFCLK# 7

MINI1 NB CLK SB SATA NB CLK NB CLK (96 MHz)

SB,-1PCLK_KBC PCLK_FWH 4,7 CPU_SEL1 CLK_ICH14 PCLK_FWH

SRN33J-5-GP-U CPU_SEL2_R

64 5 55

1

1

2

2

EC56 SC5P50V2CN-2GP

EC59 SC22P50V2JN-4GP

18 31

1 2

4 3

PCLKCLK3

ICS9LPRS365BKLFT setting table PIN NAME DESCRIPTION PCI0/CR#_AByte 5, bit 7 0 = PCI0 enabled (default) 1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair Byte 5, bit 6 0 = CR#_A controls SRC0 pair (default), 1= CR#_A controls SRC2 pair Byte 5, bit 5 0 = PCI1 enabled (default) 1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair Byte 5, bit 4 0 = CR#_B controls SRC1 pair (default) 1= CR#_B controls SRC4 pair 0 = Overclocking of CPU and SRC Allowed 1 = Overclocking of CPU and SRC NOT allowed 3.3V PCI clock output

18 15 1

22 30 36 49 59 26

71.09365.A03

65

ICS9LPRS365BKLFT-GP-U

GND

2

DY

RN70 SRN33J-5-GP-U

2

2nd: 71.00875.C03 RTM875N-606-LFT QFN 64P

SEL2 SEL1 SEL0 FSC FSB FSA PIN NAME SRCC3/CR#_D SRCC7/CR#_E DESCRIPTIONByte 5, bit 1 0 = SRC3 enabled (default) 1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair Byte 5, bit 0 0 = CR#_D controls SRC1 pair (default) 1= CR#_D controls SRC4 pair Byte 6, bit 7 0 = SRC7# enabled (default) 1= CR#_F controls SRC6 Byte 6, bit 6 0 = SRC7 enabled (default) 1= CR#_F controls SRC8 Byte 6, bit 5 0 = SRC11# enabled (default) 1= CR#_G controls SRC9 Title Byte 6, bit 4 0 = SRC11 enabled (default) 1= CR#_H controls SRC10

CPU100M 133M 166M 200M 266M

FSBX 533M 667M 800M 1066M

PCI1/CR#_B PCI2/TME PCI31

1 0 0 0 0

0 0 1 1 0

1 1 1 0 0

SRCT11/CR#_H

Size

Document Number

xa in

SRCT3/CR#_C

Byte 5, bit 3 0 = SRC3 enabled (default) 1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair Byte 5, bit 2 0 = CR#_C controls SRC0 pair (default), 1= CR#_C controls SRC2 pair

Clock GeneratorRev

Date: Wednesday, July 16, 2008A B C D

he

Cathedral Peak IISheetE

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SRCC11/CR#_G

ho


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PCI_F5/ITP_EN

0 =SRC8/SRC8# 1 = ITP/ITP#

SRCT7/CR#_F

Wistron Corporation

3

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PCI4/27M_SEL

0 = Pin24 as SRC-1, Pin25 as SRC-1#, Pin20 as DOT96, Pin21 as DOT96# 1 = Pin24 as 27MHz, Pin25 as 27MHz_SS, Pin20 as SRC-0, Pin21 as SRC-0#

omSC

1

A

B

C

D

E

6

H_A#[35..3]

H_A#[35..3] H_DINV#[3..0] U33A 1 OF 4 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 TP57 TPAD30 H_DSTBN#[3..0] 6 6 6 1D05V_S0 H_DSTBP#[3..0] H_D#[63..0] H_DINV#[3..0] H_DSTBN#[3..0] H_DSTBP#[3..0] H_D#[63..0] 6 6 6 64

4

6 6

H_ADSTB#0 H_REQ#[4..0]

J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 K3 H2 K2 J3 L1 Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 A6 A5 C4 D5 C6 B4 A3

A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# ADSTB0# REQ0# REQ1# REQ2# REQ3# REQ4# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A32# A33# A34# A35# ADSTB1# A20M# FERR# IGNNE# STPCLK# LINT0 LINT1 SMI# RSVD#M4 RSVD#N5 RSVD#T2 RSVD#V3 RSVD#B2 RSVD#C3 RSVD#D2 RSVD#D22 RSVD#D3 RSVD#F6 KEY_NC

ADS# BNR# BPRI#

H1 E2 G5 H5 F21 E1 F1 D20 B3 H4 C1 F3 F4 G3 G2 G6 E4 AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET# H_RS#0 H_RS#1 H_RS#2

H_ADS# H_BNR# H_BPRI#

ADDR GROUP 0

CONTROL

DEFER# DRDY# DBSY# BR0# IERR# INIT# LOCK# RESET# RS0# RS1# RS2# TRDY# HIT# HITM#

H_DEFER# 6 H_DRDY# 6 H_DBSY# 6 H_BREQ#0 6 H_IERR# H_INIT# 17

1

R125 56R2J-4-GP

Place testpoint on H_IERR# with a GND 0.1" away

2

TP95

TPAD30

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_LOCK# 6 H_CPURST# 6,41 H_RS#[2..0]

U33B 2 OF 4 6 H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0

H_TRDY# 6 H_HIT# H_HITM# TP27 TP25 TP28 TP41 TP30 TP37 TP29 TP39 TP40 TP44 TP34 TP91 6 6 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 H_THERMDA

XDP/ITP SIGNALS

3

Side Band Non GTL6 17 17 17 17 17 17 17 H_ADSTB#1 H_A20M# H_FERR# H_IGNNE# H_STPCLK# H_INTR H_NMI H_SMI# TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TP52 TP49 TP48 TP47 TP89 TP92 TP87 TP90 TP88 TP72 TP93

BPM0# BPM1# BPM2# BPM3# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#

DYH_THERMDC

1D05V_S0 6 6 6

2

C136 SC2200P50V2KX-2GP

E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25

R123 68R2-GP

D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# DSTBN0# DSTBP0# DINV0# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# DSTBN1# DSTBP1# DINV1# GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 BSEL0 BSEL1 BSEL2

D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# DSTBN2# DSTBP2# DINV2# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DSTBN3# DSTBP3# DINV3# COMP0 COMP1 COMP2 COMP3 DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI#

Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 R26 U26 AA1 Y1 E5 B5 D24 D6 D7 AE6

H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 6 H_DSTBP#2 6 H_DINV#2 6 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 6 H_DSTBP#3 6 H_DINV#3 6 COMP0 COMP1 COMP2 COMP3 R105 R104 R98 R99

DATA GRP2

DATA GRP0

1

2

THERMTRIP#

C7

PM_THRMTRIP-A# 7,17,32

HCLK

BCLK0 BCLK1

A22 A21

CLK_CPU_BCLK 3 CLK_CPU_BCLK# 3 PM_THRMTRIP# should connect to ICH9 and MCH without T-ing ( No stub) Layout Note: "CPU_GTLREF0" 0.5" max length.

1D05V_S0

2

RSVD_CPU_1 RSVD_CPU_2 RSVD_CPU_3 RSVD_CPU_4 RSVD_CPU_5 RSVD_CPU_6 RSVD_CPU_7 RSVD_CPU_8 RSVD_CPU_9 RSVD_CPU_10 RSVD_CPU_11

M4 N5 T2 V3 B2 C3 D2 D22 D3 F6 B1

2

RESERVED

R263 1KR2F-3-GP

6 6 6

H_DSTBN#1 H_DSTBP#1 H_DINV#1

1

CPU_GTLREF0

DATA GRP3

1

1

BGA479-SKT6-GPU7

2

2

ADDR GROUP 1

3

1

THERMALPROCHOT# THRMDA THRMDC D21 A24 B25CPU_PROCHOT# H_THERMDA 21 H_THERMDC 21

1 R124

DY

2

CPU_PROCHOT#_R

34

0R2J-2-GP

H_D#16 N22 H_D#17 K25 H_D#18 P26 H_D#19 R23 H_D#20 L23 H_D#21 M24 H_D#22 L22 H_D#23 M23 H_D#24 P25 H_D#25 P23 H_D#26 P22 H_D#27 T24 H_D#28 R24 H_D#29 L25 H_D#30 T25 H_D#31 N25 L26 M26 N24

DATA GRP1

ICH1D05V_S0

R266 2KR2F-3-GP

DY C352SC1KP50V2KX-1GP

TPAD30 TP86 TPAD30 TPAD30 TP21 TP150

AD26 TEST1 C23 TEST2 D25 RSVD_CPU_12 C24 TEST4 AF26 RSVD_CPU_13 AF1 RSVD_CPU_14 A26 B22 B23 C21

MISC

1 1 1 1

2 2 2 2

27D4R2F-L1-GP 54D9R2F-L1-GP 27D4R2F-L1-GP 54D9R2F-L1-GP

2

62.10079.001

2nd: 62.10053.401

3,7 3,7 3,7

CPU_SEL0 CPU_SEL1 CPU_SEL2

H_DPRSTP# 7,17,34 H_DPSLP# 17 H_DPWR# 6 H_PWRGD 17,32,41 H_CPUSLP# 6 PSI# 34

BGA479-SKT6-GPU7

62.10079.001

Follow Demo CircuitXDP_TMS XDP_TDI XDP_BPM#5 R102 1 R101 1 R97

2 54D9R2F-L1-GP 2 54D9R2F-L1-GP 2 54D9R2F-L1-GP 1 R118 1 R295 2 C351

1

DY DY

2 2

TEST1 1KR2J-1-GP TEST2 1KR2J-1-GP

Net "TEST4" as short as possible, make sure "TEST4" routing is reference to GND and away other noisy signals

Layout Note: Comp0, 2 connect with Zo=27.4 ohm, make trace length shorter than 0.5" . Comp1, 3 connect with Zo=55 ohm, make trace length shorter than 0.5" .

H_CPURST# XDP_TCK1

R116 1 R94 R96

DY

2 51R2F-2-GP 2 54D9R2F-L1-GP 2 54D9R2F-L1-GP

1 1

TEST4 1 SCD1U10V2KX-4GP

XDP_TRST#

DY3D3V_S01

All place within 2" to CPUXDP_DBRESET# R121 1

DY

2 1KR2J-1-GP1D05V_S0 Title

Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

XDP_TDO

R100 1

DY

2 54D9R2F-L1-GPSize Date: Document Number

CPU (1 of 2)Rev

Cathedral Peak IIWednesday, July 16, 2008 SheetE

SCof 43

4

A

B

C

D

A

B

C

D

E

VCC_CORE VCC_CORE4

VCC_CORE

VCC_CORE

U33D

4 OF 4

VCC_CORE

1

1

1

1

1

1

1

1

C86 SCD1U10V2KX-4GP

C120 SCD1U10V2KX-4GP


C88 SCD1U10V2KX-4GP

C90 SCD1U10V2KX-4GP



C89 SCD1U10V2KX-4GP

1 4

U33C 3 OF 4

3

2

A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCA VCCA VID0 VID1 VID2 VID3 VID4 VID5 VID6 VCCSENSE VSSSENSE

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20G5

TC9 ST900U2D5VM-1-GP TP22 TPAD30

DY

DY2

DY2

DY2

DY

DY

DY

DY

NEC77.E9071.011

VCC_CORE

C123 SC10U6D3V5MX-3GP














DY2

DY2

DY2

DY2

DY2

DY2

DY2

DY2

CAP

CAP

CAP

CAP

CAP

CAP

1D05V_S0 VCCP_1D05

G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 B26 C26 AD6 AF5 AE5 AF4 AE3 AF3 AE2 AF7 AE7

1

2GAP-CLOSE-PWR-2U 1D05V_S0



DY

2

2






C95 SCD1U10V2KX-4GP

C98 SCD1U10V2KX-4GP

C99 SC4D7U6D3V3KX-GP


layout note: "1D5V_VCCA_S0" as short as possible1D5V_S0 1D5V_VCCA_S0 L11

DY

DY

1 1 1H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6 H_VID[6..0] VCC_CORE 34 C421 SCD01U16V2KX-3GP C427 SC10U6D3V5MX-3GP

2

PBY160808T-121Y-GP

DY

68.00206.021

R77 100R2F-L1-GP-U

VCC_SENSE 34 VSS_SENSE 34

Layout Note: R88 100R2F-L1-GP-U VCCSENSE and VSSSENSE lines should be of equal length.

BGA479-SKT6-GPU7

62.10079.0012

Title

Size Date:A B C D

Document Number Wednesday, July 16, 2008

xa in

CPU (2 of 2)

f@

ho


tm

Wistron Corporation

ai l.c43

1

omRev

Layout Note: Provide a test point (with no stub) to connect a differential probe between VCCSENSE and VSSSENSE at the location where the two 54.9ohm resistors terminate the 55 ohm transmission line.

A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

4

2

2

2

2

2

1

1

1

1

1

1

1

1

1

1

1

1

1

2 3

2

2

2

2

2

2

1

3

1

1

1

1

1

1

1

1

1

1

2

2

2

2

2

2

2

2

2

1

2

2

1

2

TPAD30 TP24

2

1

TPAD30 TP26 TP94 TPAD30

TP151 TPAD30 TP23 TPAD30

BGA479-SKT6-GPU7

62.10079.001

1

he


SCof

5

5

4

3

2

1

U35A 4 H_D#[63..0] H_D#[63..0] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

1 OF 10 H_A#[35..3]

D

H_SWING routing Trace width and Spacing use 10 / 20 mil H_SWING Resistors and Capacitors close MCH 500 mil ( MAX )C450 SCD1U10V2KX-4GP

1D05V_S0

R317 221R2F-2-GP

H_SWING

R316 100R2F-L1-GP-U

C

H_RCOMP routing Trace width and Spacing use 10 / 20 mil1 R312 2 24D9R2F-L-GPH_RCOMP

Place them near to the chip ( < 0.5")

B

F2 G8 F8 E6 G2 H6 H2 F6 D4 H3 M9 M11 J1 J2 N12 J6 P2 L2 R2 N9 L6 M5 J3 N2 R1 N5 N6 P13 N8 L7 N10 M3 Y3 AD14 Y6 Y10 Y12 Y14 Y7 W2 AA8 Y9 AA13 AA9 AA11 AD11 AD10 AD13 AE12 AE9 AA2 AD8 AA3 AD3 AD7 AE14 AF3 AC1 AE3 AC3 AE11 AE8 AG2 AD6

H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35 H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#

A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20 H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADS# 4 H_ADSTB#0 4 H_ADSTB#1 4 H_BNR# 4 H_BPRI# 4 H_BREQ#0 4 H_DEFER# 4 H_DBSY# 4 CLK_MCH_BCLK 3 CLK_MCH_BCLK# 3 H_DPWR# 4 H_DRDY# 4 H_HIT# 4 H_HITM# 4 H_LOCK# 4 H_TRDY# 4

H_A#[35..3]

4

D

2

1

2

1

2

1

C

HOST

H_DINV#[3..0]

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 H_RS#_0 H_RS#_1 H_RS#_2

J8 L3 Y13 Y1 L10 M7 AA5 AE6 L9 M8 AA6 AE5 B15 K13 F13 B13 B14 B6 F12 C8

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#[3..0] H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#[3..0] H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#0 H_RS#1 H_RS#2

H_DINV#[3..0]

4

H_DSTBN#[3..0]

4

H_DSTBP#[3..0]

4

B

1D05V_S0

H_REQ#[4..0]

4

2

H_SWING H_RCOMP R322 1KR2F-3-GP 4,41 H_CPURST# 4 H_CPUSLP# H_AVREF

C5 E3 C12 E11 A11 B11

H_SWING H_RCOMP H_CPURST# H_CPUSLP# H_AVREF H_DVREF

H_RS#[2..0]

4

1

1

1R318 2KR2F-3-GP


CANTIGA-GM-GP-U-NF

2

71.CNTIG.00U2A

A

Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Date:5 4 3 2

Document Number

Cantiga (1 of 6)Cathedral Peak IISheet1

Rev

SCof 43

Wednesday, July 16, 2008

6

5

4

3

2

1

U35B

2 OF 10 U35C 3 OF 10 R214 1D05V_S0

1D8V_S3

R339 1KR2F-3-GP

SM_RCOMP_VOH

D

2

2

R338 3K01R2F-3-GP

C477 C475 SCD01U16V2KX-3GP SC2D2U6D3V3MX-1-GP SM_RCOMP_VOL

RESERVED#M36 RESERVED#N36 RESERVED#R33 RESERVED#T33 RESERVED#AH9 RESERVED#AH10 RESERVED#AH12 RESERVED#AH13 RESERVED#K12 RESERVED#AL34 RESERVED#AK34 RESERVED#AN35 RESERVED#AM35 RESERVED#T24

DDR CLK/ CONTROL/COMPENSATION

1

1

1

M36 N36 R33 T33 AH9 AH10 AH12 AH13 K12 AL34 AK34 AN35 AM35 T24 B31 B2 M1 AY21

SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1 SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1 SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1 SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1 SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1 SM_RCOMP SM_RCOMP# SM_RCOMP_VOH SM_RCOMP_VOL SM_VREF SM_PWROK SM_REXT SM_DRAMRST#

AP24 AT21 AV24 AU20 AR24 AR21 AU24 AV20 BC28 AY28 AY36 BB36 BA17 AY16 AV16 AR13 BD17 AY17 BF15 AY13 BG22 BH21 BF28 BH28 AV42 AR36 BF17 BC36

M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3 M_CKE0 M_CKE1 M_CKE2 M_CKE3 M_CS0# M_CS1# M_CS2# M_CS3# M_ODT0 M_ODT1 M_ODT2 M_ODT3 M_RCOMPP M_RCOMPN SM_RCOMP_VOH SM_RCOMP_VOL 13 13 12 12 13 13 12 12 13 13 12 12

13 13 12 12 13 13 12 12

14 L_BKLTCTL 30 GMCH_BL_ON TPAD30 TP119 TPAD30 TP118 14 CLK_DDC_EDID 14 DAT_DDC_EDID 14 GMCH_LCDVDD_ON

L_BKLTCTL GMCH_BL_ON LCTLA_CLK LCTLB_DATA CLK_DDC_EDID DAT_DDC_EDID

L32 G32 M32 M33 K33 J33 M29 C44 B43 E37 E38 C41 C40 B37 A37 H47 E46 G40 A40 H48 D45 F40 B40 A41 H38 G37 J37 B42 G38 F37 K37

L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3 LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3 LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3 LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3

PEG_COMPI PEG_COMPO PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15 PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15 PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15

T37 T36 H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39 H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40 J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 AA40 AD43 AC46 J42 L46 M48 M39 M43 R47 N37 T39 U36 U39 Y39 Y46 AA36 AA39 AD42 AD46

PEG_CMP 2

1 49D9R2F-GP

Close to GMCH as 500 mils.

1

GMCH_LCDVDD_ON LIBG TPAD30 TP121 L_LVBG

2

D

RSVD

RESERVED#B31 RESERVED#B2 RESERVED#M1 RESERVED#AY21

14 GMCH_TXACLK14 GMCH_TXACLK+ 14 GMCH_TXBCLK14 GMCH_TXBCLK+ 14 GMCH_TXAOUT014 GMCH_TXAOUT114 GMCH_TXAOUT214 GMCH_TXAOUT0+ 14 GMCH_TXAOUT1+ 14 GMCH_TXAOUT2+ DDR_VREF_S3 14 GMCH_TXBOUT014 GMCH_TXBOUT114 GMCH_TXBOUT214 GMCH_TXBOUT0+ 14 GMCH_TXBOUT1+ 14 GMCH_TXBOUT2+

2

LVDS

1

1

2

2

BG23 BF23 BH18 BF18

RESERVED#BG23 RESERVED#BF23 RESERVED#BH18 RESERVED#BF18

layout take note

SM_REXT R328 1 TP_SM_DRAMRST#

2 2499R2F-2-GP TP120 TPAD30


1D8V_S3

CLK

R331 80D6R2F-L-GP

PEG_CLK PEG_CLK#

F43 E43

CLK_MCH_3GPLL CLK_MCH_3GPLL#

3 3

TVA_DAC TVB_DAC TVC_DAC

F25 H25 K25 H24

TVA_DAC TVB_DAC TVC_DAC TV_RTN

M_RCOMPP M_RCOMPN

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_33,4 3,4 3,4 CPU_SEL0 CPU_SEL1 CPU_SEL2 CFG5 CFG6 CFG7

1

AE41 AE37 AE47 AH39 AE40 AE38 AE48 AH40 AE35 AE43 AE46 AH42 AD35 AE44 AF46 AH43

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

DMI_TXN0 18 DMI_TXN1 18 DMI_TXN2 18 DMI_TXN3 18 DMI_TXP0 18 DMI_TXP1 18 DMI_TXP2 18 DMI_TXP3 18 DMI_RXN0 18 DMI_RXN1 18 DMI_RXN2 18 DMI_RXN3 18 DMI_RXP0 18 DMI_RXP1 18 DMI_RXP2 18 DMI_RXP3 18 15 GMCH_BLUE GMCH_BLUE GMCH_GREEN GMCH_RED

C31 E32

R330 80D6R2F-L-GP

TV_DCONSEL_0 TV_DCONSEL_1

2

C

3D3V_S0

CFG9 CFG10 CFG12 CFG13

R207 1 R208 1

DY DY

2 4K02R2F-GP 2 4K02R2F-GP

CFG19 CFG20 CFG16 CFG19 CFG20

GRAPHICS VID

T25 R25 P25 P20 P24 C25 N24 M24 E21 C23 C24 N21 P21 T21 R20 M20 L21 H21 P29 R28 T28

CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

PCI-EXPRESS

DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK#

2

1

B38 DREFCLK A38 DREFCLK# E41 DREFSSCLK F41 DREFSSCLK#

DREFCLK 3 DREFCLK# 3 DREFSSCLK 3 DREFSSCLK# 3

GRAPHICS

R334 1KR2F-3-GP

C470 C472 SCD01U16V2KX-3GP SC2D2U6D3V3MX-1-GP

2

1

1

TV

C

DMI

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

E28 G28 J28 G29

CRT_BLUE CRT_GREEN CRT_RED

15 GMCH_GREEN 15 GMCH_RED

CFG

VGA

CRT_IRTN CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC

15 GMCH_DDCCLK 15 GMCH_DDCDATA 15 GMCH_HSYNC 15 GMCH_VSYNC GFX_VID[4..0] 38

2 1

GMCH_DDCCLK GMCH_DDCDATA GMCH_HS 3 4 GMCH_VS

H32 J32 J29 E29 L29

R345 1 R186 1 R188 1

DY DY DY

2 2K21R2F-GP 2 2K21R2F-GP 2 2K21R2F-GP

CFG5 CFG6 CFG7 18 PM_SYNC# 4,17,34 H_DPRSTP# 18,21,34 VGATE_PWRGD 18,32 PWROK 18,25,27,30,31 PLT_RST1# R354 0R2J-2-GP 1 DY 2 PM_SYNC# H_DPRSTP# PM_EXTTS#0 PM_EXTTS#1 PWROK_GD RSTIN# PM_THRMTRIP-A# PM_DPRSLPVR

R336 1

DY

2 2K21R2F-GP

CFG10

R140

2

R332 1

DY

2 2K21R2F-GP

CFG9

2 R353

1 0R0402-PAD 1 2 300R2F-GP

R29 B7 N33 P32 AT40 AT11 T20 R32

PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4

B33 B32 G33 F33 E33

GFX_VID0 GFX_VID1 GFX_VID2 GFX_VID3 GFX_VID4

RN71 SRN33J-5-GP-U CRT_IREF 1 2 R347 1K02R2F-1-GP

CANTIGA-GM-GP-U-NF

71.CNTIG.00U FOR Cantiga: 1.02k_1% ohm Teenah: 1.3k ohm

PM

GFX_VR_EN

C34

GFXVR_EN

GFXVR_EN 38

1D05V_S0 R355 1KR2F-3-GP

CRT_IREF routing Trace width use 20 mil

ME

1

R185 1

DY

2 2K21R2F-GP

CFG13 4,17,32 PM_THRMTRIP-A# 18,34 PM_DPRSLPVR

2

R190 1

DY

2 2K21R2F-GP

CFG12

2

B

MISC

R189 1

DY

2 2K21R2F-GP

CFG16

3D3V_S0

RN32 PM_EXTTS#0 PM_EXTTS#1

HDA

4 3

1 2SRN10KJ-5-GP

NC#BG48 NC#BF48 NC#BD48 NC#BC48 NC#BH47 NC#BG47 NC#BE47 NC#BH46 NC#BF46 NC#BG45 NC#BH44 NC#BH43 NC#BH6 NC#BH5 NC#BG4 NC#BH3 NC#BF3 NC#BH2 NC#BG2 NC#BE2 NC#BG1 NC#BF1 NC#BD1 NC#BC1 NC#F1 NC#A47

1

C165 SC100P50V2JN-3GP

DY

BG48 BF48 BD48 BC48 BH47 BG47 BE47 BH46 BF46 BG45 BH44 BH43 BH6 BH5 BG4 BH3 BF3 BH2 BG2 BE2 BG1 BF1 BD1 BC1 F1 A47

CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF

AH37 AH36 AN36 CLPWROK_MCH 2 R352 1 0R0402-PAD AJ35 AH34 MCH_CLVREF

CL_CLK0 18 CL_DATA0 18 PWROK 18,32 CL_RST#0 18

1

RN72 GMCH_RED R356 511R2F-2-GP GMCH_BLUE GMCH_GREEN


DDPC_CTRLCLK DDPC_CTRLDATA SDVO_CTRLCLK SDVO_CTRLDATA CLKREQ# ICH_SYNC# TSATN#

N28 M28 G36 E36 K36 H36 B12

2

TP115 TPAD30

1 2 3 4SRN150F-1-GP

8 7 6 5B

CLK_MCH_OE# MCH_ICH_SYNC# MCH_TSATN# TP110 TPAD30

3 18

1

NC

FOR Cantiga:500 ohm Teenah: 392 ohm

RN62

HDA_BCLK HDA_RST# HDA_SDI HDA_SDO HDA_SYNC

B28 B30 B29 C29 A28RN63 GMCH_LCDVDD_ON GMCH_BL_ON GFXVR_EN 1D05V_S0 SRN100KJ-8-GP-U R216 1 2 2K37R2F-GP

TVA_DAC TVB_DAC TVC_DAC

1 2 3 4SRN75J-1-GP

8 7 6 5

1 2 3 4

8 7 6 53D3V_S0 RN33 LCTLB_DATA LCTLA_CLK CLK_MCH_OE#

CANTIGA-GM-GP-U-NF

1R324 56R2J-4-GP

71.CNTIG.00U

LIBG

MCH_TSATN#

5 6 7 8

4 3 2 1SRN10KJ-6-GP

Pin Name

Strap Description

Configuration

2

A

ai l.cWistron CorporationTitle Size Date: Document Number

omA

CFG20

he

Cantiga (2 of 6)Rev


xa in

High = Digital DisplayPort (SDVO/DP/HDMI) and PCIE are operating simultaneously via the PEG port


f@

Digital DisplayPort (SDVO/DP/HDMI) Concurrent with PCIE

ho

Low = Only digital DisplayPort (SDVO/DP/HDMI) or PCIE is operational (default)

tm

SCof 43


7

5

4

3

2

5

4

3

2

1

U35D 13 M_A_DQ[63..0] M_A_DQ[63..0] M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

4 OF 10

U35E

5 OF 10

D

C

AJ38 AJ41 AN38 AM38 AJ36 AJ40 AM44 AM42 AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36 AW36 BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12 BB9 BA9 AU10 AV9 BA11 BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6 AT5 AN10 AM11 AM5 AJ9 AJ8 AN12 AM13 AJ11 AJ12

SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63

SA_BS_0 SA_BS_1 SA_BS_2 SA_RAS# SA_CAS# SA_WE#

BD21 BG18 AT25 BB20 BD20 AY20

12 M_B_DQ[63..0] M_A_BS#0 13 M_A_BS#1 13 M_A_BS#2 13 M_A_RAS# 13 M_A_CAS# 13 M_A_WE# 13

M_A_DM[7..0]

M_A_DQS[7..0] M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14

SYSTEM

DDR

B

DDR

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14

BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25

M_A_A[14..0] 13

SYSTEM

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8

M_A_DQS[7..0]

13

B

SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

A

AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5

M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

M_A_DM[7..0] 13

M_A_DQS#[7..0]

M_A_DQS#[7..0]

13

M_A_A[14..0]

M_B_DQ[63..0] M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

AK47 AH46 AP47 AP46 AJ46 AJ48 AM48 AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44 BG43 BF43 BE45 BC41 BF40 BF41 BG38 BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11 BG8 BH12 BF11 BF8 BG7 BC5 BC6 AY3 AY1 BF6 BF5 BA1 BD3 AV2 AU3 AR3 AN2 AY2 AV1 AP3 AR1 AL1 AL2 AJ1 AH1 AM2 AM3 AH3 AJ3

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

SB_BS_0 SB_BS_1 SB_BS_2 SB_RAS# SB_CAS# SB_WE#

BC16 BB17 BB33 AU17 BG16 BF14

M_B_BS#0 12 M_B_BS#1 12 M_B_BS#2 12 M_B_RAS# 12 M_B_CAS# 12 M_B_WE# 12D

M_B_DM[7..0]

SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14

AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2 AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5 AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33

M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 M_B_DQS[7..0] M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14

M_B_DM[7..0] 12

M_B_DQS[7..0]

12

MEMORY

MEMORY

M_B_DQS#[7..0]

M_B_DQS#[7..0]

12

M_B_A[14..0]

M_B_A[14..0] 12

C

CANTIGA-GM-GP-U-NF

CANTIGA-GM-GP-U-NF

B

71.CNTIG.00U

71.CNTIG.00U

A

A

Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title

Cantiga (3 of 6)Size Date:5 4 3 2

Document Number

Rev

Cathedral Peak IIWednesday, July 16, 2008 Sheet1

SCof 43

8

5

4

3

2

1

7 OF 10 1D8V_S3 U35G

VCC_GFXCORE

667MTS 2400mA 800MTS 3000mAD

AP33 AN33 BH32 BG32 BF32 BD32 BC32 BB32 BA32 AY32 AW32 AV32 AU32 AT32 AR32 AP32 AN32 BH31 BG31 BF31 BG30 BH29 BG29 BF29 BD29 BC29 BB29 BA29 AY29 AW29 AV29 AU29 AT29 AR29 AP29 BA36 BB24 BD16 BB21 AW16 AW13 AT13

VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC

VCC_GFXCORE

C

VCC SM LF

Y26 AE25 AB25 AA25 AE24 AC24 AA24 Y24 AE23 AC23 AB23 AA23 AJ21 AG21 AE21 AC21 AA21 Y21 AH20 AF20 AE20 AC20 AB20 AA20 T17 T16 AM15 AL15 AE15 AJ15 AH15 AG15 AF15 AB15 AA15 Y15 V15 U15 AN14 AM14 U14 T14

VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG

VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF

W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16

1D05V_S0

U35F

6 OF 10

1

1

1

1

1






VCC_GFXCORE

DY

DY

DY

DY

POWER

AG34 AC34 AB34 AA34 Y34 V34 U34 AM33 AK33 AJ33 AG33 AF33 AE33 AC33 AA33 Y33 W33 V33 U33 AH28 AF28 AC28 AA28 AJ26 AG26 AE26 AC26 AH25 AG25 AF25 AG24 AJ23 AH23 AF23VCC_GMCH_35

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

2

2

2

2

2

D

1

1

1

1

1

1

1

1

TC18

Coupling CAP 370 mils from the Edge

2

2

2

2

2

2

2

2

VCC SM

2

SE220U2D5VDM-3GP

DY

DY

DY

1


1


Place on the Edge

Coupling CAP DY2

DY

2

VCC CORE






C233 SC1U10V3ZY-6GP


1


POWER

VCC GFX NCTF

1D05V_S0

Coupling CAPG11

1

2

T32

GAP-CLOSE-PWR

Place CAP where LVDS and DDR2 taps

FOR VCC SM1D8V_S3





TC19




DY

DY

DY2

DY

VCC GFX

Place on the Edge

VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF

AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23

C

2

2

2

2

2

2

VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF

AV44 SM_LF1_GMCH BA37 SM_LF2_GMCH AM40 SM_LF3_GMCH AV21 SM_LF4_GMCH AY5 SM_LF5_GMCH AM10 SM_LF6_GMCH BB13 SM_LF7_GMCH 1 1 1 1 1 1C464 SCD1U10V2KX-4GP C164 SCD1U10V2KX-4GP C178 C468 SCD22U10V2KX-1GP C488 SCD47U16V3ZY-3GP C491 SC1U10V3KX-3GP

2

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

1

C492 SC1U10V3KX-3GPB

38 VCC_AXG_SENSE 38 VSS_AXG_SENSE

VCC_AXG_SENSE VSS_AXG_SENSECANTIGA-GM-GP-U-NF

SCD22U10V2KX-1GP 2

B

2

2

2

2

2

71.CNTIG.00U

place near Cantiga

2

AJ14 AH14

VCC NCTF

1

1

1

1

1

1

1

1

A

ai l.cWistron CorporationTitle Size Date:5 4 3 2

omA

Document Number

he

Cantiga (4 of 6)Sheet1

xa in


f@

ho

tmRev

SE330U2D5VDM-LGP

Cathedral Peak II9 of 43

SC


5

4

3

2

1

5V_S0

Imax = 300 mAU36

3D3V_S0_DAC

3D3V_S0_DAC

1D05V_S0

1 2 3 1

VIN GND EN/EN#

VOUT NC#4

1

1

1

1

1

1

1


4 2 2EC153 SC1U16V3ZY-GP

RT9198-33PBR-GP EC154 74.09198.G7F SC1U16V3ZY-GP

1

2

C476 SC22U16V0KX-1GP


B27 A26

VCCA_CRT_DAC VCCA_CRT_DAC VCCA_DAC_BG VSSA_DAC_BG

D

3D3V_S0_DAC

CRT

DY

M_VCCA_DAC_BG A25 B25

1

1 2 R342 0R0603-PAD

5mA

M_VCCA_DPLLA C474 SCD1U10V2KX-4GP 1D8V_TXLVDS_S3 M_VCCA_DPLLB M_VCCA_HPLL M_VCCA_MPLL

F47 L48 AD1 AE1 J48

1D05V_S0

VCCA_DPLLB VCCA_HPLL VCCA_MPLL VCCA_LVDS

VTT

VCCA_DPLLA

PLL

1

1

R358 1 2 0R0603-PAD C490 SC10U6D3V5MX-3GP

65mAM_VCCA_DPLLA C486 SCD1U10V2KX-4GP

1

A LVDS

DY1D5V_S0

2

VSSA_LVDS

2



1D05V_S0

A PEG

1

1

R357 1 2 0R0603-PAD

M_VCCA_DPLLB

1

65mADY

2

R351 0R0402-PAD 1

VCCA_PEG_BG C482 SCD1U10V2KX-4GP

AD48

VCCA_PEG_BG

1D05V_S0

1

1

1

1

1D05V_S0

1 2 R191 0R0603-PAD

2

2

720mAC171 SC10U6D3V5MX-3GP C224 SC4D7U6D3V3KX-GP C219

1D05V_RUN_PEGPLL AA48 1D05V_SM C227 SC1U10V3KX-3GP

VCCA_PEG_PLL VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM

322mA1 1C467 SC1U10V3KX-3GP C460 SC10U6D3V5MX-3GP

2

2

2

2

2

R310 0R0603-PAD

L13

24mAM_VCCA_HPLL

1D05V_S0

1

1

1

1

68.00217.161

C443

1

1 2 FCM1608KF-1-GP

26mA1D05V_SM_CK C237 SC10U6D3V5MX-3GP C245 SC2D2U6D3V3MX-1-GP C241 SCD1U10V2KX-4GP

120ohm 100MHz2L12 1 2 FCM1608KF-1-GP


1 2 R203 0R0603-PAD

A SM

1

1D05V_SUS_MCH_PLL2

2

1D8V_SUS_SM_CK

2

C

DY

AR20 AP20 AN20 AR17 AP17 AN17 AT16 AR16 AP16

DY

2

C277 SC1KP50V2KX-1GP

DY

13.2mA J47

2

2

R349 10R2F-L-GP

1

1D8V_TXLVDS_S3

VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT

U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1



C256 SC2D2U6D3V3MX-1-GP


1 2

C187

1 2

5

1 2 R346 0R0603-PAD

73mA

3D3V_CRTDAC_S0

U35H

8 OF 10

-1

852mADYC175 SCD1U10V2KX-4GP SCD47U6D3V2KX-GP

DY

2

2

2

2

2

2

D

2

1D05V_S0

D22

1 2 BAT54-7-F-GP 31D05V_HV_S0 1

3D3V_S0

2

3D3V_HV_S0 R350 2 1 0R0402-PAD C480 SCD1U10V2KX-4GP

SC1U10V3KX-3GP

POWER

C

SC4D7U6D3V3KX-GP

1D8V_S3

DY

DY

AXF

M_VCCA_MPLL

1

139.2mA1C446 SCD1U10V2KX-4GP 3D3V_S0_DAC L14

DY

A CK

120ohm 100MHz

68.00217.161

2

2

DY C442

1

1D05V_S0B


1

1 2 0R0603-PAD

3D3VTVDAC C469 SCD01U16V2KX-3GP

SM CK

79mA

AP28 AN28 AP25 AN25 AN24 AM28 AM26 AM25 AL25 AM24 AL24 AM23 AL23

VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF

VCC_AXF VCC_AXF VCC_AXF

B22 B21 A21

2

2

2

124mAR183 1 C230 SCD1U10V2KX-4GP

R179 1 2 0R0603-PAD

2

1

2

1D8V_SUS_SM_CK_RC

1

2

2

1R2F-GP

VCC_SM_CK VCC_SM_CK VCC_SM_CK VCC_SM_CK

BF21 BH20 BG20 BF20

C222 SC10U6D3V5MX-3GP 1D8V_S3

SC10U6D3V5MX-3GP

1D8V_TXLVDS_S3

119mA1 K47 C35 B35 A35 V48 U48 V47 U47 U46 AH48 AF48 AH47 AG473D3V_HV_S0

2

2

L15

50mA1D05V_RUN_PEGPLL

DY

TV

2

1

68.00217.521

220ohm 100MHz


50mAA32 VCC_HDA

VCC_HV VCC_HV VCC_HV VCC_PEG VCC_PEG VCC_PEG VCC_PEG VCC_PEG VCC_DMI VCC_DMI VCC_DMI VCC_DMI

HV

1D05V_S0

HDA

1782mA1 1 1C447 SC4D7U6D3V3KX-GP C262 SC22U6D3V5MX-2GP C439 SC22U6D3V5MX-2GP

2

PEG

1

2

1

2 FCM1608CF-221T02-GP

B24 A24

VCC_TX_LVDS VCCA_TV_DAC VCCA_TV_DAC

1

R217 1 2 0R0603-PAD C275 SC1U10V3KX-3GPB

106mA

C276 SC1KP50V2KX-1GP

1D5VRUN_TVDAC 1D5V_S0 R196 1 2 0R0603-PAD

M25 L28 AF1

35mA1D5VRUN_TVDAC

VCCD_TVDAC VCCD_QDAC VCCD_HPLL VCCD_PEG_PLL VCCD_LVDS VCCD_LVDS

D TV/CRT


1D05V_SUS_MCH_PLL2

1D5VRUN_QDAC

DY

DY

DY1D05V_S0

2

2

2

DMI

1

157.2mA1 1C186 SCD1U10V2KX-4GP C483 SCD1U10V2KX-4GP

-11C263

2

1


1 2


1D05V_RUN_PEGPLL AA47

456mAVTTLF1 VTTLF2 VTTLF3 C185 1 1 SCD47U6D3V2KX-GP 2

2

VTTLF

LVDS

2

2

L2

1

2 PBY160808T-181Y-GP 1

1D5VRUN_QDAC 1D8V_S3 C239 SCD1U10V2KX-4GP

VTTLF VTTLF VTTLF

180ohm 100MHzA

68.00206.041

CANTIGA-GM-GP-U-NF R212 1 2 0R0603-PAD

C202 1 SCD47U6D3V2KX-GP 2

71.CNTIG.00U1D8V_SUS_DLVDS

2

C445 SCD47U6D3V2KX-GP

2

2

M38 L37

DY

2


SCD1U10V2KX-4GP

A8 L1 AB2

A

1


1

60.3mA



2

2

Cantiga (5 of 6)Size Date: Document Number Rev

Cathedral Peak IIWednesday, July 16, 2008 Sheet1

SCof 43

10

5

4

3

2

5

4

3

2

1

U35J U35I 9 OF 10

10 OF 10

D

C

B

Title CANTIGA-GM-GP-U-NF CANTIGA-GM-GP-U-NF

71.CNTIG.00U

71.CNTIG.00U

Size Date:

Document Number Wednesday, July 16, 2008

xa in

Cantiga (6 of 6)

f@

ho


tm

Wistron Corporation

ai l.c43

A

AU48 AR48 AL48 BB47 AW47 AN47 AJ47 AF47 AD47 AB47 Y47 T47 N47 L47 G47 BD46 BA46 AY46 AV46 AR46 AM46 V46 R46 P46 H46 F46 BF44 AH44 AD44 AA44 Y44 U44 T44 M44 F44 BC43 AV43 AU43 AM43 J43 C43 BG42 AY42 AT42 AN42 AJ42 AE42 N42 L42 BD41 AU41 AM41 AH41 AD41 AA41 Y41 U41 T41 M41 G41 B41 BG40 BB40 AV40 AN40 H40 E40 AT39 AM39 AJ39 AE39 N39 L39 B39 BH38 BC38 BA38 AU38 AH38 AD38 AA38 Y38 U38 T38 J38 F38 C38 BF37 BB37 AW37 AT37 AN37 AJ37 H37 C37 BG36 BD36 AK15 AU36

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23 AJ6

BG21 L12 AW21 AU21 AP21 AN21 AH21 AF21 AB21 R21 M21 J21 G21 BC20 BA20 AW20 AT20 AJ20 AG20 Y20 N20 K20 F20 C20 A20 BG19 A18 BG17 BC17 AW17 AT17 R17 M17 H17 C17 BA16 AU16 AN16 N16 K16 G16 E16 BG15 AC15 W15 A15 BG14 AA14 C14 BG13 BC13 BA13 AN13 AJ13 AE13 N13 L13 G13 E13 BF12 AV12 AT12 AM12 AA12 J12 A12 BD11 BB11 AY11 AN11 AH11 Y11 N11 G11 C11 BG10 AV10 AT10 AJ10 AE10 AA10 M10 BF9 BC9 AN9 AM9 AD9 G9 B9 BH8 BB8 AV8 AT8

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4 BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1 U24 U28 U25 U29 AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17 BH48 BH1 A48 C1 A3 E1 D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48TP163 TP155 TP164 TP156 TP157 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30

D

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF

C

B

NCTF TEST PIN: A3,C1,A48,BH1,BH48

VSS SCB

NCTF_VSS_SCB#BH48 NCTF_VSS_SCB#BH1 NCTF_VSS_SCB#A48 NCTF_VSS_SCB#C1 NCTF_VSS_SCB#A3 NC#E1 NC#D2 NC#C3 NC#B4 NC#A5 NC#A6 NC#A43 NC#A44 NC#B45 NC#C46 NC#D47 NC#B47 NC#A46 NC#F48 NC#E48 NC#C48 NC#B48

NC

VSS NCTF

omRev

A

he


SCof

11

5

4

3

2

A

B

C

D

E

DM1 8 DDR_VREF_S34

M_B_A[14..0]

PARALLEL TERMINATIONRN25

8 7 6 5

1 2 3 4

M_B_A8 M_B_A9 M_B_A5

Put decap near power(0.9V) and pull-up resistor

8 7 6 5

SRN56J-5-GP RN31 1 M_CKE3 2 M_B_A12 3 M_B_BS#2 4 M_CKE2

TPAD30 TP111

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

8 8 8

M_B_BS#2 M_B_BS#0 M_B_BS#1 M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_ODT2 M_ODT3

102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 107 106 5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194 11 29 49 68 129 146 167 186 13 31 51 70 131 148 169 188 114 119 1 2

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2 BA0 BA1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7# DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 OTD0 OTD1 VREF VSS GND MH1DDR2-200P-23-GP-U1

RAS# WE# CAS# CS0# CS1# CKE0 CKE1 CK0 CK0# CK1 CK1# DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 SDA SCL VDDSPD SA0 SA1 NC#50 NC#69 NC#83 NC#120 NC#163/TEST VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS GND MH2

108 109 113 110 115 79 80 30 32 164 166 10 26 52 67 130 147 170 185 195 197 199 198 200 50 69 83 120 163 81 82 87 88 95 96 103 104 111 112 117 118 3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196 201 MH2DDRB_SA0 M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

M_B_RAS# 8 M_B_WE# 8 M_B_CAS# 8 M_CS2# 7 M_CS3# 7 M_CKE2 7 M_CKE3 7 M_CLK_DDR2 7 M_CLK_DDR#2 7 M_CLK_DDR3 7 M_CLK_DDR#3 7 M_B_DM[7..0]4

8

SRN56J-5-GP RN18 8 1 M_B_A3 7 2 M_B_A1 6 3 M_B_A10 5 4 M_B_WE# SRN56J-5-GP RN15 1 M_B_A13 2 M_ODT2 3 M_ODT3 4 M_B_RAS# SRN56J-5-GP RN22 M_B_BS#1 M_B_A2 M_B_A0 M_B_A4

8 M_B_DQ[63..0]

8 7 6 5

SMBD_ICH SMBC_ICH

3,13,20 3,13,20

3D3V_S0

2

2 R114 10KR2J-3-GP

1C117 SCD1U16V2ZY-2GP

1

SRN56J-5-GP RN27 M_B_A14 M_B_A11 M_B_A7 M_B_A6

3

8 7 6 5

1 2 3 4SRN56J-5-GP RN12

REVERSE TYPE

8 7 6 5

1 2 3 4

DY

3

1D8V_S3

8 7 6 5

1 2 3 4SRN56J-5-GP

M_B_BS#0 M_B_CAS# M_CS3# M_CS2#

1D8V_S3

Place these Caps near DM11 1 1 1C449 SC2D2U6D3V3MX-1-GP C451 SC2D2U6D3V3MX-1-GP C174 SC2D2U6D3V3MX-1-GP C199 SC2D2U6D3V3MX-1-GP

Decoupling CapacitorDDR_VREF_S32

1 2


Put decap near power(0.9V) and pull-up resistorC180 SCD1U16V2ZY-2GP C166 SCD1U16V2ZY-2GP C196 SCD1U16V2ZY-2GP C215 SCD1U16V2ZY-2GP C197 SCD1U16V2ZY-2GP C221 SCD1U16V2ZY-2GP C217 SCD1U16V2ZY-2GP C160 SCD1U16V2ZY-2GP C220 SCD1U16V2ZY-2GP C172 SCD1U16V2ZY-2GP 8 M_B_DQS#[7..0]

DY2

DY2

2

2

2

1

1

1

1

1

1

1

1

1

1


DY

DY

DY

DY

2

2

2

2

2

2

2

2

2

2

2

1

1

1

1




1 2


DY

DY

2

2

8 M_B_DQS[7..0]

-1

DDR_VREF_S3_1 7 7

1


1

DY


202 MH1

2

2

62.10017.A71

High 9.2mm2nd: 62.10017.B511 1

2


DDR2 Socket 0 (DM1)Size Date:A B C D

Document Number

Rev

Cathedral Peak IIWednesday, July 16, 2008E

SC

Sheet

12

of

43

A

B

C

D

E

DDR_VREF_S34

PARALLEL TERMINATIONRN29

8

M_A_A[14..0]

DM2 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

8 7 6 5

1 2 3 4SRN56J-5-GP RN16

M_A_A12 M_CKE0 M_A_BS#2 M_A_A8

Put decap near power(0.9V) and pull-up resistor

8 7 6 5

1 2 3 4SRN56J-5-GP RN23

M_A_A13 M_ODT0 M_CS0# M_A_RAS#

TPAD30

TP112 8 8 8 M_A_BS#2 M_A_BS#0 M_A_BS#1

102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 107 106

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2 BA0 BA1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 /DQS0 /DQS1 /DQS2 /DQS3 /DQS4 /DQS5 /DQS6 /DQS7 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 ODT0 ODT1 VREF VSS GND

/RAS /WE /CAS /CS0 /CS1 CKE0 CKE1 CK0 /CK0 CK1 /CK1 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 SDA SCL VDDSPD SA0 SA1 NC#50 NC#69 NC#83 NC#120 NC#163/TEST

108 109 113 110 115 79 80 30 32 164 166 10 26 52 67 130 147 170 185 195 197 199 198 200 50 69 83 120 163 81 82 87 88 95 96 103 104 111 112 117 118 3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196 201M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

M_A_RAS# 8 M_A_WE# 8 M_A_CAS# 8 M_CS0# 7 M_CS1# 7 M_CKE0 7 M_CKE1 7 M_CLK_DDR0 7 M_CLK_DDR#0 7 M_CLK_DDR1 7 M_CLK_DDR#1 7 M_A_DM[7..0]

4

8

8 7 6 5

1 2 3 4SRN56J-5-GP RN13

M_A_BS#1 M_A_A0 M_A_A2 M_A_A4

8 M_A_DQ[63..0]

8 7 6 5

1 2 3 4SRN56J-5-GP RN24

M_A_CAS# M_ODT1 M_CS1#

8 7 6 5

1 2 3 4SRN56J-5-GP

M_A_A9 M_A_A14 M_A_A5 M_A_A3

3

RN28

8 7 6 5

1 2 3 4SRN56J-5-GP RN19

M_A_A6 M_A_A7 M_A_A11 M_CKE1

8 7 6 5

1 2 3 4SRN56J-5-GP

M_A_BS#0 M_A_A1 M_A_A10 M_A_WE#

1

1

1

1

DDR_VREF_S3





1

Decoupling CapacitorPut decap near power(0.9V) and pull-up resistor1 1 1 1 1 1 1 1 1C189 SCD1U16V2ZY-2GP C207 SCD1U16V2ZY-2GP C181 SCD1U16V2ZY-2GP C209 SCD1U16V2ZY-2GP C218 SCD1U16V2ZY-2GP C223 SCD1U16V2ZY-2GP C192 SCD1U16V2ZY-2GP C201 SCD1U16V2ZY-2GP C173 SCD1U16V2ZY-2GP



DY

DY

DY

DY

DY

2

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_ODT0 M_ODT1

5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194 11 29 49 68 129 146 167 186 13 31 51 70 131 148 169 188 114 119 1 2

SMBD_ICH SMBC_ICH

3,12,20 3,12,20

3D3V_S0

1 2C115 SCD1U16V2ZY-2GP

DY

REVERSE TYPE

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS GND

3

1D8V_S3

1D8V_S3

Place these Caps near DM2C169 SC2D2U6D3V3MX-1-GP

DY

DY

2

2

2

2

1

2

2

2

2

2

2

2

2

2

2

2

1

2

2

1

1

1

8 M_A_DQS#[7..0]




1 2


DY

DY

2

2

8 M_A_DQS[7..0]

DDR_VREF_S3_1 7 7

1

1

2

2


DY

C279

202

SKT-SODIMM20022U2GP

62.10017.691

High 5.2mm2nd: 62.10017.911

2

1

ai l.cTitle Size Date:A B C D

om1

Document Number

he

DDR2 Socket 1 (DM2)Rev


xa in

f@


ho

tm

SCD1U16V2ZY-2GP

SCof 43


13

LCD/INVERTER/CCD CONNLCDVDD 18 USBPN8 R6 2 1 0R0402-PAD USBPN8_R 18 USBPP8 R7 2 1 0R0402-PAD USBPP8_R 3D3V_S0

Inverter Pin Pin 11

Symbol Vin Vin Brightness BLON GND GND

1

1

LCD1

41 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42

C4

1 2C5

DY2

7 CLK_DDC_EDID 7 DAT_DDC_EDID

CLK_DDC_EDID DAT_DDC_EDID CCD_PWR

BLON_OUT

R457 1 33R2J-2-GP

BRIGHTNESS_CN 2BLON_OUT_1

DCBATOUT F2

1 1 1

2

PWR_INVERTER

3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

SC10U10V5ZY-1GP GMCH_TXBCLK+ GMCH_TXBCLKGMCH_TXBOUT2+ GMCH_TXBOUT2GMCH_TXBOUT1+ GMCH_TXBOUT1GMCH_TXBOUT0+ GMCH_TXBOUT0GMCH_TXACLK+ GMCH_TXACLKGMCH_TXAOUT2+ GMCH_TXAOUT2GMCH_TXAOUT1+ GMCH_TXAOUT1GMCH_TXAOUT0+ GMCH_TXAOUT0GMCH_TXBCLK+ 7 GMCH_TXBCLK- 7 GMCH_TXBOUT2+ 7 GMCH_TXBOUT2- 7 GMCH_TXBOUT1+ 7 GMCH_TXBOUT1- 7 GMCH_TXBOUT0+ 7 GMCH_TXBOUT0- 7 GMCH_TXACLK+ 7 GMCH_TXACLK- 7 GMCH_TXAOUT2+ 7 GMCH_TXAOUT2- 7 GMCH_TXAOUT1+ 7 GMCH_TXAOUT1- 7 GMCH_TXAOUT0+ 7 GMCH_TXAOUT0- 7

2

C3 DY SCD1U25V3ZY-1GP SCD1U25V3ZY-1GP

2 3 4 5 6

Cover Up Switch3D3V_AUX_S5

CCD Pin Pin 1 2 3 4 5 Symbol CCD_PWR USBUSB+ GND GND3 GND VDD 1U4

1

DYOUT 2 2

R253 10KR2J-3-GP LID_CLOSE# LID_CLOSE# 30

EC93 SCD1U16V2ZY-2GP

2

DY1

POLYSW-1D1A24V-GP EC86 SCD1U50V3ZY-GP

ME268-002-GP

DY

20.F0993.040

EC92 SCD1U16V2ZY-2GP

2

2

2nd: 20.F1048.040 3nd: 20.F1084.040

2

DY

R241 1 0R2J-2-GP

L_BKLTCTL 7

BRIGHTNESS_CN 3D3V_S0 BLON_OUT

R242 1 2 0R0402-PAD

BRIGHTNESS 30 BLON_OUT 16,30

74.00268.A7B 74.00268.C7B

1


1


DYRN1 SRN2K2J-1-GP

DY

2

CLK_DDC_EDID DAT_DDC_EDID 3D3V_S0 LCDVDD U1

4 3

1 2

2

Layout 40 mil7 GMCH_LCDVDD_ON GMCH_LCDVDD_ON

1 2 3 4

IN#1 OUT EN GND

1

C6 SC4D7U6D3V3MX-2GP

DY

C2 SCD1U16V2ZY-2GP

GND IN#8 IN#7 IN#6 IN#5

1

1

9 8 7 6 5C7 SC4D7U6D3V3MX-2GP

2

2

G5281RC1U-GP

74.05281.093

-1F3

1

2FUSE-1D1A6V-8GP

3D3V_S0

69.41101.021F4 CCD_PWR

DY23D3V_S0

1C308 SCD1U16V2ZY-2GP

1

C309 SC4D7U10V5ZY-3GP

1

FUSE-4A32V-6-GP

DY

69.44001.041

2

1

2

C307 SC10U25V6KX-1GP

69.50007.A31

ACES-CONN40A-2GP

74.00268.07B

Consumption stockTitle


2

2

LCD CONNSize Date: Document Number Rev

Cathedral Peak IIWednesday, July 16, 2008 Sheet 14 of 43

SC

A

B

C

D

E

Layout Note: Place these resistors close to the CRT-out connector 7 GMCH_RED

Hsync & Vsync level shiftFerrite bead impedance: 10 ohm@100MHzL7 5V_S0 CRT_R

1 2C314 SCD1U16V2ZY-2GP4

1

2 FCB1608CF-GP

68.00230.0214

L6

14

7 GMCH_GREEN

1

68.00230.021L4 7 GMCH_BLUE

1

2 FCB1608CF-GP

CRT_G

1 1 1 1 8 7 6 5EC109 EC106 EC96 SC3P50V2CN-1-GP SC3P50V2CN-1-GP

1

1

14

RN73 SRN150F-1-GP

2

2

2

2

2

2

4

68.00230.021

7

C336 SC6D8P50V2DN-GP

C326 SC6D8P50V2DN-GP

1

2 FCB1608CF-GP

CRT_B C321 SC6D8P50V2DN-GP

7 GMCH_HSYNC

2

3U32A TSAHCT125PW-GP

CRT_HSYNC1

SC3P50V2CN-1-GP

DY1 2 3 4

DY

DY

7 GMCH_VSYNC

5 1 1

6U32B TSAHCT125PW-GP

CRT_VSYNC1

DYC342 SC18P50V2JN-1-GP

DY7C341 SC18P50V2JN-1-GP

2

5V_S0 D20

2

3

Layout Note: * Must be a ground return path between this ground and the ground on the VGA connector. Pi-filter & 150 Ohm pull-down resistors should be as close as to CRT CONN. RGB will hit 75 Ohm first, pi-filter, then CRT CONN.

CRT_R 3

DY1

BAV99PT-GP-U3

D18 CRT_G 3

2

DY1BAV99PT-GP-U D17 CRT_B 3

2

DY1

BAV99PT-GP-U

CRT I/F & CONNECTOR2

DDC_CLK & DATA level shift 6 1 7 2 8 3 9 4 10 57 GMCH_DDCDATA 3D3V_S0 5V_CRT_S0

2

5V_S0

3D3V_S0

1

2

CRT1

2

16CRT_R CRT_G CRT_B

D2 BAS16PT-GP

1 2 3 4

F1

1 2 3 4 4 5 6 3 2 17 GMCH_DDCCLK 2N7002DW-1-GP

CRT_IN#_R

5 17

7 12 8 13 9 14 10 15

CRT_HSYNC1 CRT_VSYNC1 C315 CLK_DDC1_5 SCD01U16V2KX-3GP

RN41 SRN2K2J-1-GP

FUSE-1D1A6V-4GP-U

8 7 6 5RN2 SRN10KJ-6-GP CRT_IN#_R DAT_DDC1_5 CLK_DDC1_5

DAT_DDC1_5

5V_CRT_S0

3 4

1

2

5V_CRT_DDC

69.50007.691Q15

VIDEO-15-42-GP-U

20.20378.015

CRT_VSYNC1 C316 SC18P50V2JN-1-GP

1

CRT_HSYNC1 CLK_DDC1_5 DAT_DDC1_5 C317 C19 SC100P50V2JN-3GP

2

1

2 1

3

6 11

DY

1

1

470R2J-2-GP C578 SC220P50V2JN-3GP

DY

Size Date:

Document Number

xa in

DY

2

2

SC100P50V2JN-3GP

BAV99PT-GP-U 1

Title

CRT Connector

f@

C313

3

DY

ho

30

CRT_DEC#

2

CRT_IN#_R

D16

2


tm

DY

R254 1

2

5V_S0

Wistron Corporation

ai l.c43

1

1

C323 SC18P50V2JN-1-GP

omRev

1

2

2

1


he

SC100P50V2JN-3GP


SCof

15

A

B

C

D

5

4

3

2

1

Q31 30 FRONT_PWRLED

B

C R1 E R2 PDTC143ZU-GP-U

PWRLED#_DB 3D3V_S5 LED5 R451 1 2 56R2J-4-GP R450 1 2 56R2J-4-GP FRONT_PWRLED#_R 3 STDBY_LED#_R

Power ButtonSW1 R8

84.00143.E1KQ30

1 2 1 3 5KBC_PWRBTN#_1

CD

STDBY_LED#_BD

4LED-GY-14-GP

1

2

KBC_PWRBTN#

30

STDBY_LED

B

R1

KBC_PWRBTN# 30D

E R2 PDTC143ZU-GP-U

1

470R2J-2-GP EC5 SC1KP50V2KX-1GP 3D3V_AUX_S5 RN74

84.00143.E1KQ29

83.00195.I70

2

4 2SW-TACT-122-GP

DY

1 2

4 3

KBC_PWRBTN# BLON_OUT 14,30

C30 DC_BATFULL

DC_BATFULL# 3D3V_AUX_S5 LED6 R449 1 2 56R2J-4-GP R448 1 2 56R2J-4-GP DC_BATFULL#_R CHARGE_LED#_R

62.40009.681

SRN10KJ-5-GP

B

R1

2nd: 62.40009.671E

R2 PDTC143ZU-GP-U

84.00143.E1KQ28

SB3 4LED-GY-14-GP

1 2LED3 PWRLED#_DB STDBY_LED#_BD R458 1 2 56R2J-4-GP R465 1 2 56R2J-4-GP FRONT_PWRLED#_PB STDBY_LED#_PB 3D3V_S5

C30 CHARGE_LED

CHARGE_LED#

B

R1

E R2 PDTC143ZU-GP-U

3 4LED-GY-14-GP

1 2

84.00143.E1K27 WLAN_LED#_MC GND WLAN_LED#_1 R34 IN

83.00195.I70

1 2 33R2J-2-GP D

1

C

Q4 CHDTA143ZUPT-GP

2

WLAN_LED#

83.00195.I70C

R2

84.00143.J11R1

Q5 2N7002-11-GP 30 WLAN_TEST_LED

G S

3OUT Q18 30 BT_LED

B

C R1 E R2 PDTC143ZU-GP-U

BT_LED#

84.00143.E1K

E Power ButtonSW2B

1

3 1 5

R462 E-BUTTON#_CN_1 1

2

E-BUTTON#

E-BUTTON# 30

B

470R2J-2-GP EC13 SC1KP50V2KX-1GP

2

4 2SW-TACT-122-GP

DY

62.40009.681

3D3V_S0 C116 SC1U16V3ZY-GP 1 2

DY

2nd: 62.40009.671 -1LAUNCHCN1

EC22 SCD1U16V2ZY-2GP 1 2

-1

DYEC180 SCD1U16V2ZY-2GP 1 2

16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17MLX-CON15-1-GP

DY

5V_S0

EC181 SCD1U16V2ZY-2GP 1 2

DYWLAN_LED# BT_LED# Volume_Up# BT_BTN# WIRELESS_BTN# Volume_Down# MEDIA_LED# CAP_LED# NUM_LED# INT_MIC

A

Volume_Up# 30 BT_BTN# 30 WIRELESS_BTN# 30 Volume_Down# 30 MEDIA_LED# 17 CAP_LED# 30 NUM_LED# 30 INT_MIC 28

WLAN_LED# EC11 BT_LED# EC182 Volume_Up# EC141 BT_BTN# EC142 WIRELESS_BTN# EC143 Volume_Down# EC144 MEDIA_LED# EC123 CAP_LED# EC122 NUM_LED# EC121 INT_MIC EC149

DY1 2SC220P50V2JN-3GP

DY1 2

DY1 2

SC220P50V2JN-3GP SC220P50V2JN-3GP

DY1 2

DY1 2


DY1 2

3D3V_S0 5V_S0 WLAN_LED# BT_LED# Volume_Up# BT_BTN# WIRELESS_BTN# Volume_Down# MEDIA_LED# CAP_LED# NUM_LED# INT_MIC

1 1 1 1 1 1 1 1 1 1 1 1

AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP

TP58 TP189 TP190 TP191 TP192 TP193 TP194 TP195 TP53 TP54 TP55 TP178

DY1 2


DY1 2

DY1 2


DY1 2

SC220P50V2JN-3GP

A

Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Document Number

EMI

POWER /LAUNCH/LED BOARDCathedral Peak IISheet1

20.K0185.015

Rev

SCof 43

Date: Wednesday, July 16, 20085 4 3 2

16

5

4

3

2

1

C91 1

2

RTC_X1

SC12P50V2JN-3GP

3

D9D

X-32D768KHZ-38GPU RTC_AUX_S5

1R95 10MR2J-L-GP

3D3V_AUX_S5

X2

2RTC_BAT_R

82.30001.6912 1 2

4

D

1

3 1

C74 SC1U16V3ZY-GP C92 1

2

1D05V_S0 U16A 1 OF 6 LPC_LAD[0..3]

-1RTC1 R265 1 2 1KR2J-1-GP

CH715FPT-GP

RN75 SRN20KJ-GP-U

SC12P50V2JN-3GP

RTC_X2 RTC_RST# SRTC_RST# INTRUDER#

C23 C24 A25 F20 C22 B22 A22 E25

RTCX1 RTCX2

PWR GND NP1 NP2

1

RTC_BAT 1 2 NP1 NP2

RTC LPC

1R282

DY C353 SCD1U16V2ZY-2GP2

1

1

2 1MR2J-1-GPC73 SC1U16V3ZY-GP

FWH4/LFRAME# LDRQ0# LDRQ1#/GPIO23 A20GATE A20M#

K3 J3 J1 N7 AJ27 AJ25 AE23 AJ26 AD22 AF25 AE22 AG25 L3 AF23 AF24 AH27 AG26 AG27 AH11 AJ11 AG12 AF12 AH9 AJ9 AE10 AF10 AH18 AJ18 AJ7 AH7SATARBIAS ICH_TP8 H_DPRSTP# H_FERR#_R LDRQ0# 3D3V_LDRQ1_S0

LPC_LFRAME# 30,31 TP146 TPAD30 TP50 TPAD30 KA20GATE 30 H_A20M# 4 H_DPRSTP# 4,7,34 H_DPSLP# 4

H_DPSLP#

C354 SC1U16V3ZY-GP TPAD30 TP143

INTVRMEN LAN100_SLP

INTVRMEN LAN100_SLP GLAN_CLK LAN_RSTSYNC LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2 GLAN_DOCK#/GPIO56 GLAN_COMPI GLAN_COMPO HDA_BIT_CLK HDA_SYNC HDA_RST#

2

62.70001.011

2

BAT-CON2-1-GP-U

LAN_RSTYNC

C13 F14 G13 D14 D13 D12 E13

LAN / GLAN CPU

DPRSTP# DPSLP# FERR# CPUPWRGD IGNNE# INIT# INTR RCIN# NMI SMI# STPCLK# THRMTRIP#

2

2 1

3 4

RTCRST# SRTCRST# INTRUDER#

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

K5 K4 L6 K2

LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3

1

83.R0304.B81

2

LPC_LAD[0..3]

30,31

DY

R297 56R2J-4-GP

1D05V_S0 RN8 H_THERMTRIP_R

C

GLAN_COMP place within 500 mil of ICH9MR453 1 2 R452 RN9

1D5V_S0 18 GLAN_DOCK# GLAN_DOCK#

H_PWRGD 4,32,41 4 H_IGNNE# 4 H_INIT# 4 H_INTR 4 KBRCIN# 30

H_FERR#

1 2 3 4

8 7 6 5SRN56J-5-GP

H_FERR#_RC

B10 B28 B27 AF6 AH4 AE7 AF4 AG4 AH3 AE5

ACZ_SYNC

R284 1

23 ACZ_BTCLK_MDC 28 ACZ_BITCLK EC161 SC10P50V2JN-4GP 23,28 ACZ_SYNC 23,28 ACZ_RST# 23,28 ACZ_SDATAOUT

2 22R2J-2-GP 1 0R0402-PAD 8 7 6 5ACZ_SYNC_R ACZ_RST#_R ACZ_SDATAOUT_R

2 GLAN_COMP 24D9R2F-L-GPACZ_BIT_CLK_R

H_NMI 4 H_SMI# 4 H_STPCLK# 4 H_THERMTRIP_R TP96 TPAD30

H_PWRGD

DY

1 2 3 4

R296 200R2F-L-GP 1 DY 2

2

1

1D05V_S0

1

2

IHDA

SRN33J-7-GP 3D3V_S0

28 ACZ_SDATAIN0 23 ACZ_SDATAIN1

HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 HDA_SDOUT

PECI SATA4RXN SATA4RXP SATA4TXN SATA4TXP SATA5RXN SATA5RXP SATA5TXN SATA5TXP SATA_CLKN SATA_CLKP SATARBIAS# SATARBIAS

DY R30054D9R2F-L1-GP

PM_THRMTRIP-A# 4,7,32 Layout note: R373 needs to placed within 2" of ICH9, R379 must be placed within 2" of R373 w/o stub

ACZ_SDATAOUT_R TPAD30 16 22 22 22 22 22 22 22 22 TP148 MEDIA_LED# SATA_RXN0 SATA_RXP0 SATA_TXN0 SATA_TXP0 SATA_RXN1 SATA_RXP1 SATA_TXN1 SATA_TXP1 C146 C145 C147 C148 C149 C150 C144 C143 HDA_DOCK_RST#

AG5 AG7 AE8 AG8

1 R302

DY

HDA_DOCK_EN# 2 8K2R2J-3-GP

HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO34 SATALED#

HDD3D3V_S0B

SATA

1 1 1 1 1 1 1 1

2 2 2 2

SCD01U50V2KX-1GP SCD01U50V2KX-1GP SCD01U50V2KX-1GP SCD01U50V2KX-1GP

SATA_RXN0_C SATA_RXP0_C SATA_TXN0_C SATA_TXP0_C

AJ16 AH16 AF17 AG17

SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA1RXN SATA1RXP SATA1TXN SATA1TXP

CLK_PCIE_SATA# 3 CLK_PCIE_SATA 3

R299 MEDIA_LED#

1 2 10KR2J-3-GP

ODD

2 SCD01U50V2KX-1GP SATA_RXN1_C AH13 2 SCD01U50V2KX-1GP SATA_RXP1_C AJ13 2 SCD01U50V2KX-1GP SATA_TXN1_C AG14 2 SCD01U50V2KX-1GP SATA_TXP1_C AF14

2 1 R301 24D9R2F-L-GP

B

71.ICH9M.00URN14 SRN10KJ-5-GP

1

1

H_INIT#_G R93 330KR2F-L-GP

R90 330KR2F-L-GP

2

INTVRMEN R91 0R2J-2-GP

2

LAN100_SLP R92 0R2J-2-GP

INTVRMEN LAN100_SLP

High=Enable High=Enable

Low=Disable Low=Disable

1

1

H_INIT#

B

integrated VccSus1_05,VccSus1_5,VccCL1_5E

Q13

3 4

RTC_AUX_S5

RTC_AUX_S5

2 1

ICH9M-GP-NF

Place within 500 mils of ICH9 ball

1D05V_S0

3D3V_S0

CMMBT3904-3-GP

FWH_INIT#

integrated VccLan1_05VccCL1_05

FWH_INIT#

31

DY2

DY2

ACZ_BITCLK

Size

Document Number

xa in

EMI

ICH9-M (1 of 4)Sheet1

f@

1 EC188

2 SC22P50V2JN-4GP

Title

ho

DY


tm

ACZ_BTCLK_MDC 1 EC187

DY2 SC22P50V2JN-4GP

Wistron Corporation

Date: Wednesday, July 16, 20085 4 3 2

he

Cathedral Peak II17

of

ai l.cRev 43

A

omSC

A

5

4

3

2

1

U16C U16B 2 OF 6 PCI_REQ#0 PCI_GNT#0 PCI_REQ#1 PCI_REQ#2 PCI_REQ#3 PCI_GNT#3 TPAD30 TP147 20,27 SMB_CLK 20,27 SMB_DATA 3D3V_S5

3 OF 6

D

TP31

TPAD30

G10 GAP-OPEN

R136 1KR2J-1-GP

MISC GPIO Controller Link

1

INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#

J5 E1 J6 C4

Interrupt I/FPIRQA# PIRQB# PIRQC# PIRQD#ICH9M-GP-NF

PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5

H4 K6 F2 G2

INT_PIRQE# INT_PIRQF# INT_PIRQG# INT_PIRQH#

CL_CLK0 CL_CLK1 CL_DATA0 CL_DATA1 CL_VREF0 CL_VREF1 CL_RST0# CL_RST1# GPIO24/MEM_LED GPIO10/SUS_PWR_ACK GPIO14/AC_PRESENT GPIO9/WOL_EN

F24 B19 F22 C19 C25 A19 F21 D18 A16 C18 C11 C20GPIO24 GPIO10 GPIO14 GPIO9

CL_CLK0 7 CL_DATA0 7 CL_VREF0_ICH CL_VREF1_ICH CL_RST#0 TP32 7 TPAD30 3D3V_S5

R281 3K24R2F-GP

2

2

C

1

71.ICH9M.00URP5 PCI_PERR# INT_PIRQE# PCI_LOCK# INT_PIRQA# 3D3V_S0

1

2

1

ICS

2

1

D11 C8 D9 E12 E9 C9 E10 B7 C7 C5 G11 F8 F11 E7 A3 D2 F10 D5 D10 B3 F7 C3 F3 F4 C1 G7 H7 D1 G5 H6 G1 H3

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31

2 1

3 4

SMB

SATA GPIO

PCI

RI# SUS_STAT#/LPCPD# SYS_RESET# PMSYNC#/GPIO0 SMBALERT#/GPIO11

PM_SUS_STAT# DBRESET#

R4 G19 M6

Clocks

REQ0# GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55 C/BE0# C/BE1# C/BE2# C/BE3# IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# FRAME# PLTRST# PCICLK PME#

F1 G4 B6 A7 F13 F12 E6 F6 D8 B4 D6 A5 D3 E3 R1 C6 E4 C2 J4 A4 F5 D7

RN4

G16 A13 SMB_LINK_ALERT# E17 SMLINK0 C17 SMLINK1 B18PM_RI#

SMBCLK SMBDATA LINKALERT#/GPIO60/CLGPIO4 SMLINK0 SMLINK1

SATA0GP/GPIO21 SATA1GP/GPIO19 SATA4GP/GPIO36 SATA5GP/GPIO37 CLK14 CLK48 SUSCLK SLP_S3# SLP_S4# SLP_S5# S4_STATE#/GPIO26

AH23 AF19 AE21 AD20 H1 AF3 P1 C16 E16 G17 C10 G20 M2 B13 R3 D20 D22 R5 R6

SATA0GP SATA1GP GPIO36 GPIO37 CLK_ICH14 CLK48_ICH 3 3

RN11

5 6 7 8

4 3 2 1

SRN10KJ-5-GP

F19

SRN10KJ-6-GP

PM_SUS_CLK 21 PM_SLP_S3# 27,30,32,36,37,38 PM_SLP_S4# 27,30,36,37 TP144 TPAD30 S4_STATE# TP141 TPAD30 PWROK PM_DPRSLPVR PM_BATLOW#_R PWRBTN#_ICH R289 1 DY 2 100KR2J-1-GP 7,32 PM_DPRSLPVR 7,34D

(GPIO6,GPIO22)PCI_IRDY# PCI_PAR TP142 TPAD30 PCI_DEVSEL# PCI_PERR# PCI_LOCK# PCI_SERR# PCI_STOP# PCI_TRDY# PCI_FRAME# R271

7

PM_SYNC#

SLPS5#

SMB_ALERT# A17

SYS GPIO Power MGT

ICS Realtek Seligo

(0, 1) (1, 1) (1, 0)

3 3

PM_STPPCI# PM_STPCPU# 30 PM_CLKRUN#

A14 E19 L4 E20 M5 AJ23 D21 2ICH_TP7

STP_PCI# STP_CPU# CLKRUN# WAKE# SERIRQ THRM# VRMPWRGD SST TACH1/GPIO1 TACH2/GPIO6 TACH3/GPIO7 GPIO8 LAN_PHY_PWR_CTRL/GPIO12 ENERGY_DETECT/GPIO13 TACH0/GPIO17 GPIO18 GPIO20 SCLOCK/G

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