a2 tbd sap · d2 pf4 c1 pf5 c2 pf6 b1 pf7 b2 pf8 a2 pf9 b3 pf10 a3 pf11 b5 pf12 a5 pf13 b6 pf14 a6...
TRANSCRIPT
06/Jun/12
EW + DP + MMcC
1.1
SDP-H1
ANALOG DEVICES
APPROVED:
ECO NO:
LTR
A
B
C
D
6
5
4
3
2
1
DATE:
D
C
B
A
REVISION RECORD
SCALE:
SHEET: OF
DRAWING NO:
TITLE:
COMPANY:
RELEASED:
DATED:
DATED:
QUALITY CONTROL:
CHECKED:
DATED:
DATED:
DRAWN:
CODE:
SIZE:
REV:
13
1
A2
TBD SAP #
TBD
(BLACKFIN - POWER)
C11
0.1uF
C12
0.1uF
C13
0.1uF
C18
1nF
C19
10nF
C20
0.1uF
C23
0.1uF
C25
0.1uF
C26
0.1uF
C15
0.1uF
C16
0.1uF
C29
10uF
C32
10uF
C22
10nF
C46
0.1uF
C31
0.1uF
C21
1nF
C10
10nF
C14
10nF
C27
10nF
C17
10nF
BF_POWER
GREEN
C24
10nF
G12
VDDINT
G13
VDDINT
G14
VDDINT
H14
VDDINT
J14
VDDINT
K14
VDDINT
L14
VDDINT
M14
VDDINT
N14
VDDINT
P12
VDDINT
P13
VDDINT
P14
VDDINT
A16
VDDRTC
D19
VDDUSB
G20
VDDUSB
R20
VDDOTP
L19
VPPOTP
G7
VDDEXT
G8
VDDEXT
G9
VDDEXT
G10
VDDEXT
G11
VDDEXT
H7
VDDEXT
H8
VDDEXT
J7
VDDEXT
J8
VDDEXT
K7
VDDEXT
K8
VDDEXT
L7
VDDEXT
L8
VDDMEM
M7
VDDMEM
M8
VDDMEM
N7
VDDMEM
N8
VDDMEM
P7
VDDMEM
P8
VDDMEM
P9
VDDMEM
P10
VDDMEM
P11
VDDMEM
F19
VRSEL
U1-C
ADSP-BF522_3_4_5_6_7_208-BGA
A1
GND
A17
GND
A20
GND
B20
GND
H9
GND
H10
GND
H11
GND
H12
GND
H13
GND
J9
GND
J10
GND
J11
GND
J12
GND
J13
GND
K9
GND
K10
GND
K11
GND
K12
GND
K13
GND
L9
GND
L10
GND
L11
GND
L12
GND
L13
GND
M9
GND
M10
GND
M11
GND
M12
GND
M13
GND
N9
GND
N10
GND
N11
GND
N12
GND
N13
GND
Y1
GND
Y20
GND
U1-D
ADSP-BF522_3_4_5_6_7_208-BGA
1
IN
2
GND
3
EN
5
OUT
4
ADJ
U32
ADP123AUJZ
TSOT-5
1
IN
2
GND
3
EN
4
NC
5
OUT
U31
C2
1uF
C78
1uF
C3
1uF
C4
1uF
C1
1uF
C5
1uF
C30
1uF
C28
1uF
C34
1uF
1
2
4
U29
NC7S32
C83
0.1uF
R54
100K
C7
1uF
C6
1uF
R104
10K
R105
7K15
R110
100K
C101
0.1uF
R24
100K
R46
DNP
R58
25.5K
C253
1uF
R141
0R
C254
0.1uF
1
IN
2
GND
3
EN
4
NC
5
OUT
U28
R25
0R
R40
0R
R200
0R
1
OUT
2
OUT
3
OUTSEN
4
GND
5
EN
6
NC
7
IN
8
IN
9
EP
U6
ADP124ARHZ-3.3
1
VOUT
2
VOUT
3
GND
4
SEL1
5
SEL0
6
EN
7
VIN
8
VIN
U9
ADP198ACPZ
R11
680r
+3.3V
+2.5V
+3.3V
1.2V_BFIN
+5V
+3.3V_SWITCHED
+3.3V
+5V
+3.3V
+3.3V
+2.5V
1.2V_BFIN
+3.3V
BOOT_COMPLETE
+2.5V
VIN_SDP_CON
+3.3V
+3.3V
VCC_SWITCHED
BOARD_ON
1.1
EW + DP + MMcC
ANALOG DEVICES
APPROVED:
ECO NO:
LTR
A
B
C
D
6
5
4
3
2
1
DATE:
D
C
B
A
REVISION RECORD
SCALE:
SHEET: OF
DRAWING NO:
TITLE:
COMPANY:
RELEASED:
DATED:
DATED:
QUALITY CONTROL:
CHECKED:
DATED:
DATED:
DRAWN:
CODE:
SIZE:
REV:
13
2
A2
SDP-H1
TBD SAP #
TBD
06/Jun/12
(BLACKFIN - MEMORY)
EN
2
DQ0
4
DQ1
5
DQ2
7
DQ3
8
DQ4
10
DQ5
11
DQ6
13
DQ7
15
DQML
16
WE
17
CAS
18
RAS
19
CS
20
BA0
21
BA1
22
A10
23
A0
24
A1
25
A2
26
A3
53
DQ15
51
DQ14
50
DQ13
48
DQ12
47
DQ11
45
DQ10
44
DQ9
42
DQ8
40
N/C
39
DQMH
38
CLK
37
CKE
36
A12
35
A11
34
A9
33
A8
32
A7
31
A6
30
A5
29
A4
U5-A
MT48LC16M16A2P
49
VD
DQ
43
VD
DQ
9
VD
DQ
3
VD
DQ
27
VD
D
14
VD
D
1
VD
D
52
VSSQ
46
VSSQ
12
VSSQ
6
VSSQ
54
VSS
41
VSS
28
VSS
U5-B
MT48LC16M16A2P
C40
0.1uF
C37
0.1uF
C48
0.1uF
C49
0.1uF
R34-A
33r
R34-B
33r
R34-C
33r
R34-D
33r
R34-E
33r
R34-F
33r
R34-G
33r
R34-H
33r
R35-A
33r
R35-B
33r
R35-C
33r
R35-D
33r
R35-E
33r
R35-F
33r
R35-G
33r
R35-H
33r
R36-H
33r
R36-G
33r
R36-F
33r
R36-E
33r
R36-D
33r
R36-C
33r
R36-B
33r
R36-A
33r
R37-H
33r
R37-G
33r
R37-F
33r
R37-E
33r
R37-D
33r
R37-C
33r
R37-B
33r
R37-A
33r
R38-H
33r
R38-G
33r
R38-F
33r
R38-A
33r
R38-B
33r
R39-A
33r
R39-C
33r
R39-G
33r
R38-C
33r
R39-B
33r
R38-D
33r
R38-E
33r
R39-D
33r
R39-F
33r
R39-H
33r
R41
33R
R42
33R
1
2
4
U20
SN74LVC1G08DCKR
1
IN
2
VDD
3
GND
4
S1
5
D
6
S2
U106
ADG839YKSZ
1
S
2
Q
3
W/VPP
4
VSS
5
D
6
C
7
HOLD
8
VCC
U107
M25P32-MW
R51
100K
R52
100K
V1
DATA15
W1
DATA14
W2
DATA13
Y2
DATA12
W3
DATA11
Y3
DATA10
W4
DATA9
Y4
DATA8
W5
DATA7
Y5
DATA6
W6
DATA5
Y6
DATA4
W7
DATA3
Y7
DATA2
W8
DATA1
Y8
DATA0
V20
ABE1
V19
ABE0
L20
AMS3
M19
AMS2
K19
AMS1
J19
AMS0
P19
ARDY
N20
AOE
M20
ARE
N19
AWE
Y11
ADDR19
W11
ADDR18
Y12
ADDR17
W12
ADDR16
Y13
ADDR15
W13
ADDR14
Y14
ADDR13
W14
ADDR12
Y15
ADDR11
W15
ADDR10
Y16
ADDR9
W16
ADDR8
Y17
ADDR7
W17
ADDR6
Y18
ADDR5
W18
ADDR4
Y19
ADDR3
W19
ADDR2
W20
ADDR1
T19
SRAS
U20
SCAS
T20
SWE
P20
SCKE
K20
CLKOUT
U19
SA10
R19
SMS
U1-A
ADSP-BF522_3_4_5_6_7_208-BGA
R50
100K
R49
100K
R47
100K
1
IN1
2
D1
3
S1
15
D2
5
GND
6
S4
7
D4
8
IN4
9
IN3
10
D3
11
S3
16
IN2
13
VDD
14
S2
U113
ADG712BRUZ
C70
0.1uF
C103
0.1uF
C104
0.1uF
C102
0.1uF
R119
0R
R99
1k
R1
DNP
R22
100K
2
4
1
U2
NC7SV126
C51
0.1uF
R57
33R
R59
DNP
R60
0R
R61
100K
R64
0R
R94
10K
+3.3V
A[1:19]
D[0:15]
ASYNC_AMS2
ASYNC_AMS1
ASYNC_AMS0
D[0:15]
A[1:19]
A18
A19
SA10
SA10
SRAS
SCAS
SWE
SCKE
CLKOUT
ABE1
ABE0
SMS
SWE
SCAS
SRAS
SMS
CLKOUT
SCKE
ABE0
ABE1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A12
A13
ARE
AWE
PAR_RD_WR
+3.3V
PG1/SPISS/SPISEL1
EXP_BOOT
+3.3V
+3.3V
SPI_SEL1/SPI_SS
PG4/MOSI/DT0SECA
PG2/SCK
+3.3V
PG3/MISO/DR0SECA
+3.3V
BOARD_ON
PG2/SCK
SPI_SEL1/SPI_SS
PG4/MOSI/DT0SECA
PG3/MISO/DR0SECA
+3.3V
PG2/SCK_SW
SPI_SEL1/SPI_SS_SW
PG4/MOSI/DT0SECA_SW
PG3/MISO/DR0SECA_SW
+3.3V_SWITCHED
PG10/TMR6/TSCLK0A/TACI6
CLKOUT_BUF
+3.3V
+3.3V
+3.3V_SWITCHED
+3.3V
GND
EW + DP + MMcC
ANALOG DEVICES
APPROVED:
ECO NO:
LTR
A
B
C
D
6
5
4
3
2
1
DATE:
D
C
B
A
REVISION RECORD
SCALE:
SHEET: OF
DRAWING NO:
TITLE:
COMPANY:
RELEASED:
DATED:
DATED:
QUALITY CONTROL:
CHECKED:
DATED:
DATED:
DRAWN:
CODE:
SIZE:
REV:
13
3
A2
SDP-H1
TBD SAP #
1.1
TBD
06/Jun/12
Sets Boot Mode for SPI Flash
(BLACKFIN - CLOCK_USB)
C38
0.1uF
C42
0.1uF
D1
Y1
24.000MHz
R12
330R
C45
8.2pF
C47
8.2pF
D2
1
2
4
U108
SN74LVC1G08DCKR
1
2
RESET
R4
100K
R45
76.8K
R44
200K
W9
BMODE3
Y9
BMODE2
W10
BMODE1
Y10
BMODE0
B18
RESET
B19
NMI
G19
SS/PG
J20
EXT_WAKE1
H20
EXT_WAKE0
U1-K
ADSP-BF522_3_4_5_6_7_208-BGA
C20
USB_ID
H19
USB_VREF
D20
USB_RSET
A19
USB_XTALIN
E19
USB_VBUS
E20
USB_DP
F20
USB_DM
A18
USB_XTALOUT
U1-B
ADSP-BF522_3_4_5_6_7_208-BGA
A14
RTXI
A11
CLKIN
A15
RTX0
C19
CLKBUF
A10
XTAL
U1-I
ADSP-BF522_3_4_5_6_7_208-BGA
R53
100K
R2
100K
R5
100K
R6
100K
R7
100K
R48
100K
L1
600 ohms @ 100MHz
R100
1M
C100
10nF
R55
1
GND
2
RESET
3
MR
4
VCC
U11
ADM6384YKS29D1Z
R111
330R
C106
0.1uF
1
VBUS
2
D-
3
D+
4
IO
5
GND
6
SHLD1
7
SHLD2
J1
USB-MINI-B-UX60SC-MB-5S8
R8
100K
C52
0.1uF
1
GND
2
RESET
3
MR
4
VCC
U3
ADM6384YKS29D1Z
MR
+2.5V
+2.5V
+3.3V
EXT_WAKE0
+3.3V
+3.3V_SWITCHED
RESET
POR
EW + DP + MMcC
ANALOG DEVICES
APPROVED:
ECO NO:
LTR
A
B
C
D
6
5
4
3
2
1
DATE:
D
C
B
A
REVISION RECORD
SCALE:
SHEET: OF
DRAWING NO:
TITLE:
COMPANY:
RELEASED:
DATED:
DATED:
QUALITY CONTROL:
CHECKED:
DATED:
DATED:
DRAWN:
CODE:
SIZE:
REV:
13
4
A2
SDP-H1
TBD SAP #
1.1
TBD
06/Jun/12
JTAG
Remove Pin 3 for keying
UART
(BLACKFIN - I/O)
R9
0R
R10
0R
J3-1
J3-2
J3-3
J3-4
J3-5
J3-6
J3-7
J3-8
J3-9
J3-10
J3-11
J3-12
J3-13
J3-14
R16
2k2
2
4
U21
NC7S04
R17
2k2
J5-1
J5-2
J5-3
J5-4
R18
200K
R23
200K
R26
680r
15
2
R28-B
33r
16
1
R28-A
33r
2
15
R27-B
33r
4
13
R27-D
33r
6
11
R27-F
33r
8
9
R27-H
33r
8
9
R28-H
33r
7
10
R28-G
33r
5
12
R28-E
33r
3
14
R28-C
33r
16
1
R27-A
33r
14
3
R27-C
33r
12
5
R27-E
33r
10
7
R27-G
33r
R29-B
33r
R29-D
33r
R29-F
33r
R29-H
33r
R30-B
33r
R30-D
33r
R30-F
33r
R30-H
33r
R32-G
33r
R32-E
33r
R32-C
33r
R32-B
33r
R31-A
33r
R31-C
33r
R31-E
33r
R31-G
33r
R32-H
33r
R32-F
33r
R32-D
33r
R32-A
33r
R31-B
33r
R31-D
33r
R31-F
33r
R31-H
33r
C56
0.1uF
C57
0.1uF
C58
0.1uF
R43
33R
R33
33R
R30-E
33r
R30-C
33r
R30-A
33r
R29-G
33r
R29-E
33r
R29-C
33r
6
11
R28-F
33r
4
13
R28-D
33r
1
2
4
U14
NC7S32
C39
0.1uF
F1
PF0
E1
PF1
E2
PF2
D1
PF3
D2
PF4
C1
PF5
C2
PF6
B1
PF7
B2
PF8
A2
PF9
B3
PF10
A3
PF11
B5
PF12
A5
PF13
B6
PF14
A6
PF15
U1-E
ADSP-BF522_3_4_5_6_7_208-BGA
R2
PG0
P1
PG1
P2
PG2
N1
PG3
N2
PG4
M1
PG5
M2
PG6
L1
PG7
L2
PG8
K1
PG9
K2
PG10
J1
PG11
J2
PG12
H1
PG13
H2
PG14
G1
PG15
U1-F
ADSP-BF522_3_4_5_6_7_208-BGA
A7
PH0
B7
PH1
A8
PH2
B8
PH3
A9
PH4
B9
PH5
B10
PH6
B11
PH7
A12
PH8
B12
PH9
A13
PH10
B13
PH11
B14
PH12
B15
PH13
B16
PH14
B17
PH15
U1-G
ADSP-BF522_3_4_5_6_7_208-BGA
A4
SCL
B4
SDA
F2
PJ0
G2
PJ1
U1-H
ADSP-BF522_3_4_5_6_7_208-BGA
V2
TCK
R1
TDI
U2
TMS
U1
TRST
T1
TDO
T2
EMU
U1-J
ADSP-BF522_3_4_5_6_7_208-BGA
R20
100K
R21
100K
R3
100K
R102
33R
R103
33R
STATUS
YELLOW
R62
0R
1
CLR
2
Q0
3
D0
4
D1
5
Q1
6
Q2
7
D2
8
D3
9
Q3
19
Q7
11
CLK
12
Q4
13
D4
14
D5
15
Q5
16
Q6
17
D6
18
D7
U19
74AHC273BQ
R210
0R
R214
DNP
R215
10K
R19
33R
R217
200K
19
IN1
1
D1
2
S1
14
S2
15
D2
17
IN2
12
S3
11
D3
9
IN3
4
S4
5
D4
7
IN4
13
VDD
3
GND
21
EP
U13
ADG782BCPZ
PF1/PPI_D1/RFS0
PF3/PPI_D3/DT0PRI
PF5/PPI_D5/TSCLK0/TACLK1
PF7/PPI_D7/DR0SEC/TACI1
PF9/PPI_D9/RSCLK1/SPISEL6
PF11/PPI_D11/TFS1/CZM
PF13/PPI_D13/TSCLK1/SPISEL3/CUD
PF15/PPI_D15/DR1SEC/UART1RX/TACI3
PF0/PPI_D0/DR0PRI
PF2/PPI_D2/RSCLK0
PF4/PPI_D4/TFS0/TACLK0
PF6/PPI_D6/DT0SEC/TACI0
PF8/PPI_D8/DR1PRI
PF10/PPI_D10/RFS1/SPISEL7
PF12/PPI_D12/DT1PRI/SPISEL2/COG
PF14/PPI_D14/DT1SEC/UART1TX
PG1/SPISS/SPISEL1
PG3/MISO/DR0SECA
PG5/TMR1/PPI_FS2
PG7/TMR3/DR0PRIA/UART0TX
PG9/TMR5/RSCLK0A/TACI5
PG11/TMR7
PG13/UART1RXA/TACI2
PG15/TFSDA/MII_PHYINT/RMII_MDINT
PG2/SCK
PG4/MOSI/DT0SECA
PG6/DT0PRIA/TMR2/PPI_FS3
PG8/TMR4/RFS0A/UART0RX/TACI4
PG10/TMR6/TSCLK0A/TACI6
PG12/UART1TXA
PH0/MII_CRS/RMII_CRSDV
PH2/MDIO
PH4/MII_TXCLK/RMII_REFCLK
PH6/ERXDO
PH8/SPISEL4/ERXD1/TACLK2
PH10/ERXD2
PH12/ERXD3
PH14/ERXDV
PH1/ERXER
PH3/ETXEN
PH5/ETXD0
PH7/ETXD1
PH9/SPISEL5/ETXD2/TACLK3
PH11/ETXD3
PH13/ERXCLK
PH15/COL
PJ2/SCL
JTAG_TDO
JTAG_EMU
JTAG_TCK
JTAG_TDI
JTAG_TMS
JTAG_TRST
JTAG_EMU
JTAG_TMS
JTAG_TCK
JTAG_TRST
JTAG_TDI
JTAG_TDO
I2C_SEL_CONN_A
SDA_FMC
SDA_CONN_A
POR
ASYNC_AMS2
D[0:15]
D0
D1
D2
D3
D4
D5
D6
D7
I2C_SEL_CONN_A
CONA_PPI_EN
CONA_PPI_DIR
+3.3V
I2C_SEL_FMC
I2C_SEL_FMC
PG8/TMR4/RFS0A/UART0RX/TACI4
PJ0/PP1_FS1/TMR0
PJ1/PPI_CLK/TMRCLK
AWE
PG7/TMR3/DR0PRIA/UART0TX
+3.3V
+3.3V
+3.3V
BOOT_COMPLETE
SW_GPIO_RESET
+3.3V
I2C_SEL_DAC
I2C_SEL_DAC
SDA_DAC
+3.3V
+3.3V_SWITCHED
EW + DP + MMcC
ANALOG DEVICES
APPROVED:
ECO NO:
LTR
A
B
C
D
6
5
4
3
2
1
DATE:
D
C
B
A
REVISION RECORD
SCALE:
SHEET: OF
DRAWING NO:
TITLE:
COMPANY:
RELEASED:
DATED:
DATED:
QUALITY CONTROL:
CHECKED:
DATED:
DATED:
DRAWN:
CODE:
SIZE:
REV:
13
5
A2
SDP-H1
TBD SAP #
1.1
TBD
06/Jun/12
D[23:16] (Future Use)
PAR_WR
PAR_CS
PAR_INT
PAR_RD
PAR_FS3
PAR_FS2
PAR_FS1
PAR_CLK
PAR_A3
PAR_A2
PAR_A1
PAR_A0
SPORT_RSCLK
SPORT_RFS
SPORT1_D0
SPORT1_D1
SPORT1_TDV
SPORT0_TDV
SPORT_TSCLK
SPORT_TFS
SPORT_DT0
SPORT_DT1
SPORT_INT
SPI0_D2
SPI0_D3
Future Use
Future Use
Future Use
SPI_SEL_A
SPI_SEL_B
SPI_SEL_C
SPI_SEL1/SPI_SS
SPI_CLK
SPI_MISO
SPI_MOSI
SDA_0
SCL_0
SDA_1
SCL_1
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
TMR_A
TMR_B
TMR_C
TMR_D
UART_TX
UART_RX
RESET_IN
BMODE1_A
Future Use
Future Use
Future Use
DIR=1: A->B; DIR=0: B->A
RESET_OUT
SLEEP
WAKE
TWI_A0
(BLACKFIN - CONNECTOR A)
CLOCKOUT
J2-1
J2-2
J2-3
J2-4
J2-5
J2-6
J2-7
J2-8
J2-9
J2-10
J2-11
J2-12
J2-13
J2-14
J2-15
J2-16
J2-17
J2-18
J2-19
J2-20
J2-21
J2-22
J2-23
J2-24
J2-25
J2-26
J2-27
J2-28
J2-29
J2-30
J2-31
J2-32
J2-33
J2-34
J2-35
J2-36
J2-37
J2-38
J2-39
J2-40
J2-41
J2-42
J2-43
J2-44
J2-45
J2-46
J2-47
J2-48
J2-49
J2-50
J2-51
J2-52
J2-53
J2-54
J2-55
J2-56
J2-57
J2-58
J2-59
J2-60
J2-61
J2-62
J2-63
J2-64
J2-65
J2-66
J2-67
J2-68
J2-69
J2-70
J2-71
J2-72
J2-73
J2-74
J2-75
J2-76
J2-77
J2-78
J2-79
J2-80
J2-81
J2-84
J2-83
J2-82
J2-85
J2-86
J2-87
J2-89
J2-88
J2-91
J2-90
J2-92
J2-93
J2-94
J2-95
J2-96
J2-97
J2-99
J2-98
J2-100
J2-101
J2-102
J2-103
J2-104
J2-105
J2-106
J2-107
J2-108
J2-109
J2-110
J2-111
J2-112
J2-113
J2-114
J2-115
J2-116
J2-117
J2-118
R14
0R
A6
1A1
B5
1A2
B6
1A3
C5
1A4
C6
1A5
D5
1A6
D6
1A7
E5
1A8
A1
1B1
B2
1B2
B1
1B3
C2
1B4
C1
1B5
D2
1B6
D1
1B7
E2
1B8
A3
1D
IR
A4
1O
E
U15-A
74LVCH16245AZRDR
E6
2A1
F5
2A2
F6
2A3
G5
2A4
G6
2A5
H5
2A6
H6
2A7
J6
2A8
E1
2B1
F2
2B2
F1
2B3
G2
2B4
G1
2B5
H2
2B6
H1
2B7
J1
2B8
J3
2D
IR
J4
2O
E
U15-B
74LVCH16245AZRDR
A6
1A1
B5
1A2
B6
1A3
C5
1A4
C6
1A5
D5
1A6
D6
1A7
E5
1A8
A1
1B1
B2
1B2
B1
1B3
C2
1B4
C1
1B5
D2
1B6
D1
1B7
E2
1B8
A3
1D
IR
A4
1O
E
U16-A
74LVCH16245AZRDR
E6
2A1
F5
2A2
F6
2A3
G5
2A4
G6
2A5
H5
2A6
H6
2A7
J6
2A8
E1
2B1
F2
2B2
F1
2B3
G2
2B4
G1
2B5
H2
2B6
H1
2B7
J1
2B8
J3
2D
IR
J4
2O
E
U16-B
74LVCH16245AZRDR
C54
0.1uF
C55
0.1uF
C60
0.1uF
C61
0.1uF
C66
10nF
C67
10nF
C72
1uF
C73
1uF
1
2
4
U23
NC7S32
R125
100K
C107
0.1uF
D4
BAT750TA
MR
CONA_PAR_D[0:15]
CONA_PAR_D0
CONA_PAR_D1
CONA_PAR_D2
CONA_PAR_D3
CONA_PAR_D4
CONA_PAR_D5
CONA_PAR_D6
CONA_PAR_D7
CONA_PAR_D8
CONA_PAR_D9
CONA_PAR_D10
CONA_PAR_D11
CONA_PAR_D12
CONA_PAR_D13
CONA_PAR_D14
CONA_PAR_D15
A[1:19]
A1
A2
A3
A4
ARE
AWE
PG6/DT0PRIA/TMR2/PPI_FS3
PG5/TMR1/PPI_FS2
PJ0/PP1_FS1/TMR0
PJ1/PPI_CLK/TMRCLK
PG2/SCK_SW
PG3/MISO/DR0SECA_SW
PG4/MOSI/DT0SECA_SW
PH7/ETXD1
PH6/ERXDO
PJ0/PP1_FS1/TMR0
PG8/TMR4/RFS0A/UART0RX/TACI4
PG7/TMR3/DR0PRIA/UART0TX
PF2/PPI_D2/RSCLK0
PF1/PPI_D1/RFS0
PF7/PPI_D7/DR0SEC/TACI1
PF0/PPI_D0/DR0PRI
PF5/PPI_D5/TSCLK0/TACLK1
PF4/PPI_D4/TFS0/TACLK0
PF6/PPI_D6/DT0SEC/TACI0
PF3/PPI_D3/DT0PRI
PG11/TMR7
PH8/SPISEL4/ERXD1/TACLK2
PF9/PPI_D9/RSCLK1/SPISEL6
PF12/PPI_D12/DT1PRI/SPISEL2/COG
PH0/MII_CRS/RMII_CRSDV
PH1/ERXER
PH2/MDIO
PH3/ETXEN
PH4/MII_TXCLK/RMII_REFCLK
PH5/ETXD0
PG7/TMR3/DR0PRIA/UART0TX
PG5/TMR1/PPI_FS2
PG9/TMR5/RSCLK0A/TACI5
EXP_BOOT
SDA_CONN_A
PJ2/SCL
ASYNC_AMS0
CONA_PAR_D[0:15]
D[0:15]
PF0/PPI_D0/DR0PRI
PF1/PPI_D1/RFS0
PF2/PPI_D2/RSCLK0
PF3/PPI_D3/DT0PRI
PF4/PPI_D4/TFS0/TACLK0
PF5/PPI_D5/TSCLK0/TACLK1
PF6/PPI_D6/DT0SEC/TACI0
PF7/PPI_D7/DR0SEC/TACI1
PF8/PPI_D8/DR1PRI
PF9/PPI_D9/RSCLK1/SPISEL6
PF10/PPI_D10/RFS1/SPISEL7
PF11/PPI_D11/TFS1/CZM
PF12/PPI_D12/DT1PRI/SPISEL2/COG
PF13/PPI_D13/TSCLK1/SPISEL3/CUD
PF14/PPI_D14/DT1SEC/UART1TX
PF15/PPI_D15/DR1SEC/UART1RX/TACI3
CONA_PAR_D0
CONA_PAR_D1
CONA_PAR_D2
CONA_PAR_D3
CONA_PAR_D4
CONA_PAR_D5
CONA_PAR_D6
CONA_PAR_D7
CONA_PAR_D8
CONA_PAR_D9
CONA_PAR_D10
CONA_PAR_D11
CONA_PAR_D12
CONA_PAR_D13
CONA_PAR_D14
CONA_PAR_D15
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
ARE
CONA_PPI_EN
CONA_PPI_DIR
CONA_PAR_D0
CONA_PAR_D1
CONA_PAR_D2
CONA_PAR_D3
CONA_PAR_D4
CONA_PAR_D5
CONA_PAR_D6
CONA_PAR_D7
CONA_PAR_D8
CONA_PAR_D9
CONA_PAR_D10
CONA_PAR_D11
CONA_PAR_D12
CONA_PAR_D13
CONA_PAR_D14
CONA_PAR_D15
PG12/UART1TXA
PG15/TFSDA/MII_PHYINT/RMII_MDINT
VCC_SWITCHED
VIN_SDP_CON
ASYNC_AMS0
PAR_RD_WR
SPI_SEL1/SPI_SS_SW
+3.3V_SWITCHED
+3.3V_SWITCHED
+3.3V_SWITCHED
+3.3V_SWITCHED
+3.3V_SWITCHED
+3.3V_SWITCHED
+3.3V_SWITCHED
+3.3V_SWITCHED
+3.3V_SWITCHED
+3.3V_SWITCHED
RESET
EXT_WAKE0
PG15/TFSDA/MII_PHYINT/RMII_MDINT
+3.3V_SWITCHED
CLKOUT_BUF
1.1
EW + DP + MMcC
SDP-H1
TBD
<QC By>
<Released By>
06/Jun/12
<Checked Date>
<QC Date>
<Release Date>
ANALOG DEVICES
<Code>
A2
TBD SAP #
<Scale>
6
13
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
A
B
C
D
DATE:
1
2
3
4
5
6
D
C
B
A
LTR
ECO NO:
APPROVED:
(FPGA BANK 0 - BLACKFIN)
A3
IO_L1P_HSWAPEN_0
A4
IO_L1N_VREF_0
C5
IO_L2P_0
A5
IO_L2N_0
D6
IO_L3P_0
C6
IO_L3N_0
B6
IO_L4P_0
A6
IO_L4N_0
C7
IO_L5P_0
A7
IO_L5N_0
B8
IO_L6P_0
A8
IO_L6N_0
D9
IO_L7P_0
C8
IO_L7N_0
C9
IO_L8P_0
A9
IO_L8N_VREF_0
D7
IO_L32P_0
D8
IO_L32N_0
D10
IO_L33P_0
C10
IO_L33N_0
B10
IO_L34P_GCLK19_0
A10
IO_L34N_GCLK18_0
C11
IO_L35P_GCLK17_0
A11
IO_L35N_GCLK16_0
D11
IO_L36P_GCLK15_0
C12
IO_L36N_GCLK14_0
B12
IO_L37P_GCLK13_0
A12
IO_L37N_GCLK12_0
C13
IO_L38P_0
A13
IO_L38N_VREF_0
E12
IO_L43P_0
D12
IO_L43N_0
H12
IO_L44P_0
F12
IO_L44N_0
F13
IO_L45P_0
D13
IO_L45N_0
H13
IO_L46P_0
G13
IO_L46N_0
E14
IO_L47P_0
F15
IO_L47N_0
F14
IO_L48P_0
H14
IO_L48N_0
D14
IO_L49P_0
C14
IO_L49N_0
B14
IO_L50P_0
A14
IO_L50N_0
C15
IO_L51P_0
A15
IO_L51N_0
D15
IO_L62P_0
C16
IO_L62N_VREF_0
B16
IO_L63P_SCP7_0
A16
IO_L63N_SCP6_0
C17
IO_L64P_SCP5_0
A17
IO_L64N_SCP4_0
B18
IO_L65P_SCP3_0
A18
IO_L65N_SCP2_0
E16
IO_L66P_SCP1_0
D17
IO_L66N_SCP0_0
B11
VCCO
_0
B15
VCCO
_0
B19
VCCO
_0
B4
VCCO
_0
B7
VCCO
_0
E13
VCCO
_0
E17
VCCO
_0
E9
VCCO
_0
G10
VCCO
_0
G14
VCCO
_0
U4-A
XC6SLX25FGG484
LED
0
RED
C62
0.1uF
C153
10uF
C166
0.1uF
C167
0.1uF
C168
0.1uF
C169
0.1uF
C170
0.1uF
C176
10nF
C177
10nF
C178
10nF
C179
10nF
R88
680r
C118
10nF
R63
33R
R134
DNP
1
E/D
2
GND
3
OUT
4
VDD
Y2
FXO-HC735-100
R98
DNP
LED
2
GREEN
LED
1
YELLO
W
R15
2k2
R107
2k2
ARE
PG2/SCK_SW
ASYNC_AMS1
SYSTEM_CLK
3V3_FPGA_VCC0
3V3_FPGA_VCC0
A[1:19]
A10
A16
A18
A17
A15
A14
A12
A13
A11
A9
A8
A7
A6
A3
A5
A19
A4
A2
A1
D[0:15]
D12
D13
D9
D10
D8
D11
D5
D6
D7
D14
D3
D4
D0
D1
D2
D15
AWE
PH13/ERXCLK
PG13/UART1RXA/TACI2
PG4/MOSI/DT0SECA_SW
PG3/MISO/DR0SECA_SW
PF10/PPI_D10/RFS1/SPISEL7
PH9/SPISEL5/ETXD2/TACLK3
GND
GND
GND
FPGA_LED0
FPGA_LED1
FPGA_LED2
FPGA_LED2
FPGA_LED1
FPGA_LED0
CLKOUT_BUF
3V3_FPGA_VCC0
GND
GND
SYSTEM_CLK
FMC_POWER_EN
PS_1050KHZ_SYNC_CLK
PS_350KHZ_SYNC_CLK
FMC_PG_C2M
FMC_PRSNT_M2C_L
3V3_FPGA_VCC0
SW_GPIO_RESET
EW + DP + MMcC
SDP-H1
TBD
<QC By>
<Released By>
06/Jun/12
<Checked Date>
<QC Date>
<Release Date>
ANALOG DEVICES
<Code>
A2
TBD SAP #
1.1
<Scale>
7
13
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
A
B
C
D
DATE:
1
2
3
4
5
6
D
C
B
A
LTR
ECO NO:
APPROVED:
USER SMA (DNP)
Route these lines as differential pairs
FPGA decoupling
SRAM decoupling
These nets will be 2.5V I/O
(FPGA BANK 1 - SRAM)
C19
IO_L1P_A25_1
B20
IO_L1N_A24_VREF_1
B21
IO_L19P_1
B22
IO_L19N_1
A20
IO_L20P_1
A21
IO_L20N_1
D19
IO_L29P_A23_M1A13_1
D20
IO_L29N_A22_M1A14_1
F18
IO_L30P_A21_M1RESET_1
F19
IO_L30N_A20_M1A11_1
D21
IO_L31P_A19_M1CKE_1
D22
IO_L31N_A18_M1A12_1
C20
IO_L32P_A17_M1A8_1
C22
IO_L32N_A16_M1A9_1
G19
IO_L33P_A15_M1A10_1
F20
IO_L33N_A14_M1A4_1
H19
IO_L34P_A13_M1WE_1
H18
IO_L34N_A12_M1BA2_1
E20
IO_L35P_A11_M1A7_1
E22
IO_L35N_A10_M1A2_1
J17
IO_L36P_A9_M1BA0_1
K17
IO_L36N_A8_M1BA1_1
F21
IO_L37P_A7_M1A0_1
F22
IO_L37N_A6_M1A1_1
H20
IO_L38P_A5_M1CLK_1
J19
IO_L38N_A4_M1CLKN_1
G20
IO_L39P_M1A3_1
G22
IO_L39N_M1ODT_1
K20
IO_L40P_GCLK11_M1A5_1
K19
IO_L40N_GCLK10_M1A6_1
H21
IO_L41P_GCLK9_IRDY1_M1RASN_1
H22
IO_L41N_GCLK8_M1CASN_1
M20
IO_L42P_GCLK7_M1UDM_1
L19
IO_L42N_GCLK6_TRDY1_M1LDM_1
J20
IO_L43P_GCLK5_M1DQ4_1
J22
IO_L43N_GCLK4_M1DQ5_1
K21
IO_L44P_A3_M1DQ6_1
K22
IO_L44N_A2_M1DQ7_1
L20
IO_L45P_A1_M1LDQS_1
L22
IO_L45N_A0_M1LDQSN_1
M21
IO_L46P_FCS_B_M1DQ2_1
M22
IO_L46N_FOE_B_M1DQ3_1
N20
IO_L47P_FWE_B_M1DQ0_1
N22
IO_L47N_LDC_M1DQ1_1
P21
IO_L48P_HDC_M1DQ8_1
P22
IO_L48N_M1DQ9_1
R20
IO_L49P_M1DQ10_1
R22
IO_L49N_M1DQ11_1
T21
IO_L50P_M1UDQS_1
T22
IO_L50N_M1UDQSN_1
U20
IO_L51P_M1DQ12_1
U22
IO_L51N_M1DQ13_1
V21
IO_L52P_M1DQ14_1
V22
IO_L52N_M1DQ15_1
M19
IO_L53P_1
N19
IO_L53N_VREF_1
P19
IO_L59P_1
P20
IO_L59N_1
W20
IO_L60P_1
W22
IO_L60N_1
L17
IO_L61P_1
K18
IO_L61N_1
T19
IO_L74P_AWAKE_1
T20
IO_L74N_DOUT_BUSY_1
C21
VCCO
_1
E19
VCCO
_1
G21
VCCO
_1
J18
VCCO
_1
L16
VCCO
_1
L21
VCCO
_1
N18
VCCO
_1
R21
VCCO
_1
U18
VCCO
_1
W21
VCCO
_1
U4-B
XC6SLX25FGG484
A3
A0
A4
A1
A5
A2
B3
A3
B4
A4
C3
A5
C4
A6
D4
A7
H2
A8
H3
A9
H4
A10
H5
A11
G3
A12
G4
A13
F3
A14
F4
A15
E4
A16
D3
A17
B5
CE
A2
OE
G5
WE
A1
LB
B2
UB
B6
IO0
C5
IO1
C6
IO2
D5
IO3
E5
IO4
F5
IO5
F6
IO6
G6
IO7
B1
IO8
C1
IO9
C2
IO10
D2
IO11
E2
IO12
F2
IO13
F1
IO14
G1
IO15
E1
VD
D
D6
VD
D
E6
GN
D
D1
GN
D
H1
A18
G2
A19
U701
IS61WV102416
C143
0.1uF
C144
10uF
C145
0.1uF
C146
0.1uF
C147
0.1uF
C148
0.1uF
C149
0.1uF
C154
0.1uF
C155
0.1uF
C156
1nF
C157
1nF
C158
10uF
C113
10nF
C127
10nF
C128
10nF
C129
10nF
1
2
3
4
5
J701
SMA_BOARD_EDGE_.187
1
2
3
4
5
J702
SMA_BOARD_EDGE_.187
1
2
3
4
5
J703
SMA_BOARD_EDGE_.187
1
2
3
4
5
J704
SMA_BOARD_EDGE_.187
R136
20K
R137
20K
SRAM_D[0:15]
SRAM_D0
SRAM_D1
SRAM_D2
SRAM_D3
SRAM_D4
SRAM_D5
SRAM_D6
SRAM_D7
SRAM_D8
SRAM_D9
SRAM_D10
SRAM_D11
SRAM_D12
SRAM_D13
SRAM_D14
SRAM_D15
SRAM_A[0:19]
SRAM_A0
SRAM_A1
SRAM_A2
SRAM_A3
SRAM_A4
SRAM_A5
SRAM_A6
SRAM_A7
SRAM_A8
SRAM_A9
SRAM_A10
SRAM_A11
SRAM_A12
SRAM_A13
SRAM_A14
SRAM_A15
SRAM_A16
SRAM_A17
SRAM_CS
SRAM_OE
SRAM_WE
2V5_FPGA
SRAM_A[0:19]
SRAM_A13
SRAM_A11
SRAM_A10
SRAM_A2
SRAM_A0
SRAM_A1
SRAM_A12
SRAM_D[0:15]
SRAM_D1
SRAM_D0
SRAM_D3
SRAM_D2
SRAM_D7
SRAM_D6
SRAM_D5
SRAM_D4
SRAM_D8
SRAM_D10
SRAM_D9
SRAM_D11
SRAM_D12
SRAM_D13
SRAM_D14
SRAM_D15
SRAM_WE
SRAM_OE
SRAM_CS
2V5_FPGA
2V5_FPGA
GND
GND
2V5_FPGA
2V5_FPGA
GND
GND
GND
EXT_USR_CLK_P
EXT_USR_CLK_N
EXT_USR_GPIO_1
EXT_USR_GPIO_2
GND
GND
GND
GND
EXT_USR_CLK_P
EXT_USR_CLK_N
EXT_USR_GPIO_1
EXT_USR_GPIO_2
VADJ_EN
SRAM_A18
SRAM_A19
SRAM_A5
SRAM_A4
SRAM_A7
SRAM_A6
SRAM_A3
SRAM_A15
SRAM_A8
SRAM_A14
SRAM_A9
SRAM_A19
SRAM_A17
SRAM_A18
SRAM_A16
2V5_FPGA
GND
PJ2/SCL
SDA_FMC
SDA_DAC
06/Jun/12
SDP-H1
EW + DP + MMcC
TBD
<QC By>
<Released By>
<Checked Date>
<QC Date>
<Release Date>
ANALOG DEVICES
<Code>
A2
TBD SAP #
1.1
<Scale>
8
13
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
A
B
C
D
DATE:
1
2
3
4
5
6
D
C
B
A
LTR
ECO NO:
APPROVED:
BF-FPGA Configuration Interface
FPGA decoupling
FMC_TRST_L
(FPGA BANK 2 - FMC)
3P3VAUX
Y20
CMPCS_B_2
Y22
DONE_2
Y21
IO_L1P_CCLK_2
AA22
IO_L1N_M0_CMPMISO_2
AA21
IO_L2P_CMPCLK_2
AB21
IO_L2N_CMPMOSI_2
AA20
IO_L3P_D0_DIN_MISO_MISO1_2
AB20
IO_L3N_MOSI_CSI_B_MISO0_2
Y19
IO_L5P_2
AB19
IO_L5N_2
W18
IO_L6P_2
Y18
IO_L6N_2
U14
IO_L12P_D1_MISO2_2
U13
IO_L12N_D2_MISO3_2
U15
IO_L13P_M1_2
V15
IO_L13N_D10_2
AA18
IO_L14P_D11_2
AB18
IO_L14N_D12_2
Y17
IO_L15P_2
AB17
IO_L15N_2
AA14
IO_L16P_2
AB14
IO_L16N_VREF_2
Y16
IO_L17P_2
W15
IO_L17N_2
V13
IO_L18P_2
W13
IO_L18N_2
AA16
IO_L19P_2
AB16
IO_L19N_2
W14
IO_L20P_2
Y14
IO_L20N_2
Y15
IO_L21P_2
AB15
IO_L21N_2
W12
IO_L29P_GCLK3_2
Y12
IO_L29N_GCLK2_2
Y13
IO_L30P_GCLK1_D13_2
AB13
IO_L30N_GCLK0_USERCCLK_2
AA12
IO_L31P_GCLK31_D14_2
AB12
IO_L31N_GCLK30_D15_2
Y11
IO_L32P_GCLK29_2
AB11
IO_L32N_GCLK28_2
R11
IO_L40P_2
T11
IO_L40N_2
AA10
IO_L41P_2
AB10
IO_L41N_VREF_2
V11
IO_L42P_2
W11
IO_L42N_2
Y9
IO_L43P_2
AB9
IO_L43N_2
W10
IO_L44P_2
Y10
IO_L44N_2
AA8
IO_L45P_2
AB8
IO_L45N_2
W8
IO_L46P_2
V7
IO_L46N_2
W9
IO_L47P_2
Y8
IO_L47N_2
Y7
IO_L48P_D7_2
AB7
IO_L48N_RDWR_B_VREF_2
AA6
IO_L49P_D3_2
AB6
IO_L49N_D4_2
U9
IO_L50P_2
V9
IO_L50N_2
W6
IO_L53P_2
Y6
IO_L53N_2
Y5
IO_L54P_2
AB5
IO_L54N_2
AA4
IO_L57P_2
AB4
IO_L57N_2
Y3
IO_L58P_2
AB3
IO_L58N_2
R9
IO_L59P_2
R8
IO_L59N_2
T7
IO_L60P_2
R7
IO_L60N_2
W4
IO_L62P_D5_2
Y4
IO_L62N_D6_2
U6
IO_L63P_2
V5
IO_L63N_2
AA2
IO_L64P_D8_2
AB2
IO_L64N_D9_2
T6
IO_L65P_INIT_B_2
T5
IO_L65N_CSO_B_2
AA1
PROGRAM_B_2
AA11
VCCO
_2
AA15
VCCO
_2
AA19
VCCO
_2
AA3
VCCO
_2
AA7
VCCO
_2
T13
VCCO
_2
T9
VCCO
_2
V12
VCCO
_2
V16
VCCO
_2
V8
VCCO
_2
W5
VCCO
_2
U4-C
XC6SLX25FGG484
R90
4K7
R91
4K7
R92
0R
R97
0R
R101
680r
C159
0.1uF
C160
10uF
C161
0.1uF
C162
0.1uF
C163
0.1uF
C164
0.1uF
C165
0.1uF
C185
0.1uF
C186
0.1uF
C138
10nF
C139
10nF
C140
10nF
C141
10nF
1
2
4
U802
SN74LVC1G08DCKR
C124
0.1
uF
R132
0R
R133
100K
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
J4-A
ASP-134603-01
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
J4-B
ASP-134603-01
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
G27
G28
G29
G30
G31
G32
G33
G34
G35
G36
G37
G38
G39
G40
J4-C
ASP-134603-01
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
H30
H31
H32
H33
H34
H35
H36
H37
H38
H39
H40
J4-D
ASP-134603-01
FPGA_DONE
GREEN
R216
10K
C219
0.1uF
C236
0.1uF
R224
10K
1
VCCA
2
GND
3
A
4
B
5
DIR
6
VCCB
U803
74LVCH1T45GW
1
VCCA
2
T/R0
3
A0
4
A1
5
A2
6
A3
7
T/R3
8
GND
9
OE
10
T/R2
11
B3
12
B2
13
B1
14
B0
15
T/R1
16
VCCB
17
EP
U801
FXL4TD245BQX
FMC_LA00_P_CC
FMC_LA00_N_CC
FMC_LA01_P_CC
FMC_LA01_N_CC
FMC_LA02_P
FMC_LA02_N
FMC_LA03_P
FMC_LA03_N
FMC_LA04_P
FMC_LA04_N
FMC_LA05_P
FMC_LA05_N
FMC_LA06_P
FMC_LA06_N
FMC_LA07_P
FMC_LA07_N
FMC_LA08_P
FMC_LA08_N
FMC_LA09_P
FMC_LA09_N
FMC_LA10_P
FMC_LA10_N
FMC_LA11_P
FMC_LA11_N
FMC_LA12_P
FMC_LA12_N
FMC_LA13_P
FMC_LA13_N
FMC_LA14_P
FMC_LA14_N
FMC_LA15_P
FMC_LA15_N
FMC_LA16_P
FMC_LA16_N
FMC_LA17_P_CC
FMC_LA17_N_CC
FMC_LA18_P_CC
FMC_LA18_N_CC
FMC_LA19_P
FMC_LA19_N
FMC_LA20_P
FMC_LA20_N
FMC_LA21_P
FMC_LA21_N
FMC_LA22_P
FMC_LA22_N
FMC_LA23_P
FMC_LA23_N
FMC_LA24_P
FMC_LA24_N
FMC_LA25_P
FMC_LA25_N
FMC_LA26_P
FMC_LA26_N
FMC_LA27_P
FMC_LA27_N
FMC_LA28_P
FMC_LA28_N
FMC_LA29_P
FMC_LA29_N
FMC_LA30_P
FMC_LA30_N
FMC_LA31_P
FMC_LA31_N
FMC_LA32_P
FMC_LA32_N
FMC_LA33_P
FMC_LA33_N
FMC_CLK0_M2C_P
FMC_CLK0_M2C_N
FMC_CLK1_M2C_P
FMC_CLK1_M2C_N
FPGA_CCLK
FPGA_DONE
FPGA_DIN
FPGA_INIT_B
FPGA_PROGRAM_B
FPGA_PROGRAM_B
FPGA_INIT_B
FPGA_DIN
FPGA_CCLK
PH14/ERXDV
PH15/COL
PH12/ERXD3
PH11/ETXD3
+3.3V
VADJ_FPGA
VADJ_FPGA
VADJ_FPGA
VADJ_FPGA
PH10/ERXD2
+3.3V
FMC_LA02_P
FMC_LA02_N
FMC_LA04_P
FMC_LA04_N
FMC_LA07_P
FMC_LA07_N
FMC_LA11_P
FMC_LA11_N
FMC_LA15_P
FMC_LA15_N
FMC_LA19_P
FMC_LA19_N
FMC_LA21_P
FMC_LA21_N
FMC_LA24_P
FMC_LA24_N
FMC_LA28_P
FMC_LA28_N
FMC_LA30_P
FMC_LA30_N
FMC_LA32_P
FMC_LA32_N
FMC_LA00_P_CC
FMC_LA00_N_CC
FMC_LA03_P
FMC_LA03_N
FMC_LA08_P
FMC_LA08_N
FMC_LA12_P
FMC_LA12_N
FMC_LA16_P
FMC_LA16_N
FMC_LA20_P
FMC_LA20_N
FMC_LA22_P
FMC_LA22_N
FMC_LA25_P
FMC_LA25_N
FMC_LA29_P
FMC_LA29_N
FMC_LA31_P
FMC_LA31_N
FMC_LA33_P
FMC_LA33_N
FMC_LA01_P_CC
FMC_LA01_N_CC
FMC_LA05_P
FMC_LA05_N
FMC_LA09_P
FMC_LA09_N
FMC_LA13_P
FMC_LA13_N
FMC_LA17_P_CC
FMC_LA17_N_CC
FMC_LA23_P
FMC_LA23_N
FMC_LA26_P
FMC_LA26_N
FMC_LA06_P
FMC_LA06_N
FMC_LA10_P
FMC_LA10_N
FMC_LA14_P
FMC_LA14_N
FMC_LA18_P_CC
FMC_LA18_N_CC
FMC_LA27_P
FMC_LA27_N
VADJ_FMC
VADJ_FMC
3V3_FMC
3V3_FMC
3V3_FMC
3V3_FMC
FMC_CLK0_M2C_P
FMC_CLK0_M2C_N
FMC_CLK1_M2C_P
FMC_CLK1_M2C_N
+3.3V
+12_VIN_SWITCHED
+12_VIN_SWITCHED
PJ2/SCL
SDA_FMC
FMC_TCK
FMC_TDI
FMC_TDO
FMC_TMS
FMC_PG_C2M
FMC_PRSNT_M2C_L
FMC_PG_C2M
+3.3V
POR
+3.3V
VADJ_FPGA
FPGA_DONE
VADJ_FPGA
+3.3V
+3.3V
1.1
SDP-H1
EW + DP + MMcC
TBD
<QC By>
<Released By>
06/Jun/12
<Checked Date>
<QC Date>
<Release Date>
ANALOG DEVICES
<Code>
A2
TBD SAP #
<Scale>
9
13
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
A
B
C
D
DATE:
1
2
3
4
5
6
D
C
B
A
LTR
ECO NO:
APPROVED:
DDR2 Decoupling
FPGA Decoupling
(FPGA BANK 3 - SDRAM)
Y2
IO_L1P_3
Y1
IO_L1N_VREF_3
W3
IO_L2P_3
W1
IO_L2N_3
T4
IO_L9P_3
T3
IO_L9N_3
U4
IO_L10P_3
V3
IO_L10N_3
M5
IO_L31P_3
M4
IO_L31N_VREF_3
V2
IO_L32P_M3DQ14_3
V1
IO_L32N_M3DQ15_3
U3
IO_L33P_M3DQ12_3
U1
IO_L33N_M3DQ13_3
T2
IO_L34P_M3UDQS_3
T1
IO_L34N_M3UDQSN_3
R3
IO_L35P_M3DQ10_3
R1
IO_L35N_M3DQ11_3
P2
IO_L36P_M3DQ8_3
P1
IO_L36N_M3DQ9_3
N3
IO_L37P_M3DQ0_3
N1
IO_L37N_M3DQ1_3
M2
IO_L38P_M3DQ2_3
M1
IO_L38N_M3DQ3_3
L3
IO_L39P_M3LDQS_3
L1
IO_L39N_M3LDQSN_3
K2
IO_L40P_M3DQ6_3
K1
IO_L40N_M3DQ7_3
J3
IO_L41P_GCLK27_M3DQ4_3
J1
IO_L41N_GCLK26_M3DQ5_3
M3
IO_L42P_GCLK25_TRDY2_M3UDM_3
L4
IO_L42N_GCLK24_M3LDM_3
K5
IO_L43P_GCLK23_M3RASN_3
K4
IO_L43N_GCLK22_IRDY2_M3CASN_3
K3
IO_L44P_GCLK21_M3A5_3
J4
IO_L44N_GCLK20_M3A6_3
K6
IO_L45P_M3A3_3
J6
IO_L45N_M3ODT_3
H4
IO_L46P_M3CLK_3
H3
IO_L46N_M3CLKN_3
H2
IO_L47P_M3A0_3
H1
IO_L47N_M3A1_3
G3
IO_L48P_M3BA0_3
G1
IO_L48N_M3BA1_3
H6
IO_L49P_M3A7_3
H5
IO_L49N_M3A2_3
F2
IO_L50P_M3WE_3
F1
IO_L50N_M3BA2_3
G4
IO_L51P_M3A10_3
F3
IO_L51N_M3A4_3
E3
IO_L52P_M3A8_3
E1
IO_L52N_M3A9_3
D2
IO_L53P_M3CKE_3
D1
IO_L53N_M3A12_3
C3
IO_L54P_M3RESET_3
C1
IO_L54N_M3A11_3
G6
IO_L55P_M3A13_3
F5
IO_L55N_M3A14_3
J7
IO_L59P_3
H8
IO_L59N_3
B2
IO_L60P_3
B1
IO_L60N_3
A2
IO_L83P_3
B3
IO_L83N_VREF_3
C2
VCCO
_3
F4
VCCO
_3
F6
VCCO
_3
G2
VCCO
_3
J5
VCCO
_3
L2
VCCO
_3
L7
VCCO
_3
N5
VCCO
_3
R2
VCCO
_3
U5
VCCO
_3
W2
VCCO
_3
U4-D
XC6SLX25FGG484
K9
ODT
K2
CKE
J8
CK
K8
CK
L8
CS
K7
RAS
L7
CAS
K3
WE
R2
ADDR12
P7
ADDR11
M2
ADDR10
P3
ADDR9
P8
ADDR8
P2
ADDR7
N7
ADDR6
N3
ADDR5
N8
ADDR4
N2
ADDR3
M7
ADDR2
M3
ADDR1
M8
ADDR0
L3
BA1
L2
BA0
B9
D15
B1
D14
D9
D13
D1
D12
D3
D11
D7
D10
C2
D9
C8
D8
F9
D7
F1
D6
H9
D5
H1
D4
H3
D3
H7
D2
G2
D1
G8
D0
B7
UDQS
A8
UDQS
F7
LDQS
E8
LDQS
B3
UDM
F3
LDM
J2
VREF
J1
VD
DL
G9
VD
DQ
G7
VD
DQ
G3
VD
DQ
G1
VD
DQ
E9
VD
DQ
C9
VD
DQ
C7
VD
DQ
C3
VD
DQ
C1
VD
DQ
A9
VD
DQ
R1
VD
D
M9
VD
D
J9
VD
D
E1
VD
D
A1
VD
D
J7
VSSD
L
H8
VSSQ
H2
VSSQ
F8
VSSQ
F2
VSSQ
E7
VSSQ
D8
VSSQ
D2
VSSQ
B8
VSSQ
B2
VSSQ
A7
VSSQ
P9
VSS
N1
VSS
J3
VSS
E3
VSS
A3
VSS
U903
MT47H32M16HR_DDR2
R79
47r
R80
47r
R82
4K7
R83
100
R81
4K7
R84
4K7
C9
0.1
uF
C33
0.1
uF
C35
0.1
uF
C36
0.1
uF
C171
0.1uF
C172
10uF
C173
0.1uF
C174
0.1uF
C175
0.1uF
C63
10nF
C64
10nF
C65
10nF
C68
10nF
C69
10nF
C71
10nF
C122
10nF
C123
10nF
C150
10uF
C151
1nF
C41
0.1
uF
C152
0.1
uF
C43
1nF
C50
1nF
C53
1nF
C8
0.1uF
C252
0.1uF
R135
0R
R13
47r
R56
47r
R155
47r
R177
47r
R178
47r
R181
47r
R183
47r
R185
47r
R187
47r
R188
47r
R190
47r
R191
47r
R193
47r
R194
47r
R195
47r
R207
47r
R208
DNP
R209
100
1V8_DDR2_VDDQ
DDR2_ADDR[0:12]
DDR2_ADDR0
DDR2_ADDR1
DDR2_ADDR2
DDR2_ADDR3
DDR2_ADDR4
DDR2_ADDR5
DDR2_ADDR6
DDR2_ADDR7
DDR2_ADDR8
DDR2_ADDR9
DDR2_ADDR10
DDR2_ADDR11
DDR2_ADDR12
DDR2_DATA[0:15]
DDR2_DATA0
DDR2_DATA1
DDR2_DATA2
DDR2_DATA3
DDR2_DATA4
DDR2_DATA5
DDR2_DATA6
DDR2_DATA7
DDR2_DATA8
DDR2_DATA9
DDR2_DATA10
DDR2_DATA11
DDR2_DATA12
DDR2_DATA13
DDR2_DATA14
DDR2_DATA15
DDR2_BANK0
DDR2_BANK1
DDR2_CMD_RAS
DDR2_CMD_CAS
DDR2_CTL_ODT
DDR2_CMD_WE
DDR2_LDM
DDR2_CTL_CKE
DDR2_UDM
DDR2_CK_N
DDR2_CK_P
DDR2_UDQS_N
DDR2_UDQS_P
DDR2_LDQS_N
DDR2_LDQS_P
DDR2_ADDR[0:12]
DDR2_ADDR0
DDR2_ADDR1
DDR2_ADDR2
DDR2_ADDR3
DDR2_ADDR4
DDR2_ADDR5
DDR2_ADDR6
DDR2_ADDR7
DDR2_ADDR8
DDR2_ADDR9
DDR2_ADDR10
DDR2_ADDR11
DDR2_ADDR12
DDR2_DATA[0:15]
DDR2_DATA0
DDR2_DATA1
DDR2_DATA2
DDR2_DATA3
DDR2_DATA4
DDR2_DATA5
DDR2_DATA6
DDR2_DATA7
DDR2_DATA8
DDR2_DATA9
DDR2_DATA10
DDR2_DATA11
DDR2_DATA12
DDR2_DATA13
DDR2_DATA14
DDR2_DATA15
1V8_DDR2_VDDQ
1V8_DDR2_VDDQ
1V8_DDR2_VDDQ
GND
GND
GND
DDR2_UDM
DDR2_LDM
DDR2_UDQS_P
DDR2_UDQS_N
DDR2_LDQS_P
DDR2_LDQS_N
DDR2_CMD_RAS
DDR2_CMD_CAS
DDR2_CMD_WE
DDR2_BANK1
DDR2_BANK0
0V9_DDR2_VTT
DDR2_CTL_ODT
DDR2_CTL_CKE
GND
DDR2_CK_P
DDR2_CK_N
GND
GND
1V8_DDR2_VDDQ
GND
1V8_DDR2_VDDQ
GND
1V8_DDR2_VDDQ
GND
0V9_DDR2_VREF
GND
0V9_DDR2_VREF
GND
GND
SDP-H1
EW + DP + MMcC
TBD
<QC By>
<Released By>
06/Jun/12
<Checked Date>
<QC Date>
<Release Date>
ANALOG DEVICES
<Code>
A2
TBD SAP #
1.1
<Scale>
10
13
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
A
B
C
D
DATE:
1
2
3
4
5
6
D
C
B
A
LTR
ECO NO:
APPROVED:
Xilinx FPGA JTAG Connector
87832-1420-TB32
(FPGA POWER)
G15
TCK
E18
TD
I
C18
TM
S
A19
TD
O
N15
SU
SPEN
D
U4-E
XC6SLX25FG
G484
A1
GND
A22
GND
AA13
GND
AA17
GND
AA5
GND
AA9
GND
AB1
GND
AB22
GND
B13
GND
B17
GND
B5
GND
B9
GND
D18
GND
D4
GND
E11
GND
E15
GND
E2
GND
E21
GND
E7
GND
G18
GND
G5
GND
H7
GND
J11
GND
J13
GND
J15
GND
J2
GND
J21
GND
J9
GND
K10
GND
K12
GND
K14
GND
L11
GND
L13
GND
L18
GND
L5
GND
L9
GND
M10
GND
M12
GND
M14
GND
N11
GND
N13
GND
N17
GND
N2
GND
N21
GND
N9
GND
P10
GND
P12
GND
P14
GND
R18
GND
R5
GND
U2
GND
U21
GND
U7
GND
V10
GND
V14
GND
V4
GND
W16
GND
W19
GND
W7
GND
D16
VCCAUX
F11
VCCAUX
G12
VCCAUX
H15
VCCAUX
H9
VCCAUX
K15
VCCAUX
L8
VCCAUX
M15
VCCAUX
N8
VCCAUX
R10
VCCAUX
R12
VCCAUX
R6
VCCAUX
U11
VCCAUX
V6
VCCAUX
J10
VCCINT
J12
VCCINT
J14
VCCINT
J8
VCCINT
K11
VCCINT
K13
VCCINT
K9
VCCINT
L10
VCCINT
L12
VCCINT
L14
VCCINT
M11
VCCINT
M13
VCCINT
M9
VCCINT
N10
VCCINT
N12
VCCINT
N14
VCCINT
P11
VCCINT
P13
VCCINT
P9
VCCINT
R14
VCCINT
U4-F
XC6SLX25FG
G484
C74
4.7uF
C75
4.7uF
C81
0.1uF
C82
10uF
C84
0.1uF
C85
0.1uF
C86
0.1uF
C90
4.7uF
C91
0.1uF
C92
10uF
C93
0.1uF
C77
1nF
C80
0.1uF
C99
0.1uF
C105
0.1uF
C108
0.1uF
C109
0.1uF
C110
0.1uF
C119
1nF
C120
1nF
C76
1nF
C79
1nF
C121
1nF
J6-1
J6-2
J6-3
J6-4
J6-5
J6-6
J6-7
J6-8
J6-9
J6-10
J6-11
J6-12
J6-13
J6-14
1
IN
2
VDD
3
GND
4
S1
5
D
6
S2
U1001
ADG839YKSZ
C130
0.1uF
R89
0R
C183
0.1uF
C184
0.1uF
C114
10nF
C115
10nF
C116
10nF
C117
10nF
C87
10nF
C88
10nF
C89
10nF
C94
10nF
C95
10nF
C96
10nF
C97
10nF
C98
10nF
C111
10uF
C112
10uF
R65
0R
1
VCCA
2
T/R0
3
A0
4
A1
5
A2
6
A3
7
T/R3
8
GND
9
OE
10
T/R2
11
B3
12
B2
13
B1
14
B0
15
T/R1
16
VCCB
17
EP
U25
FXL4TD245BQX
GND
1V23_FPGA_CORE
2V5_FPGA
1V23_FPGA_CORE
GND
GND
2V5_FPGA
2V5_FPGA
GND
GND
FPGA_TDO
FPGA_TMS
FPGA_TDI
FPGA_TCK
GND
2V5_FPGA
XIL_JTAG_TDO
FPGA_TMS
FPGA_TCK
2V5_FPGA
3V3_FPGA_VCC0
FPGA_TDI
FMC_TDO_2V5
FPGA_TDO
XIL_JTAG_TDO
2V5_FPGA
GND
GND
FMC_PRSNT_M2C_L
GND
GND
FMC_TDO
FMC_TCK
FMC_TMS
FMC_TDI
FPGA_TDO
FPGA_TMS
FPGA_TCK
FMC_TDO_2V5
GND
FMC_PRSNT_M2C_L
2V5_FPGA
3V3_FPGA_VCC0
GND
2V5_FPGA
2V5_FPGA
SDP-H1
EW + DP + MMcC
1.1
TBD
<QC By>
<Released By>
06/Jun/12
<Checked Date>
<QC Date>
<Release Date>
ANALOG DEVICES
<Code>
A2
TBD SAP #
<Scale>
11
13
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
A
B
C
D
DATE:
1
2
3
4
5
6
D
C
B
A
LTR
ECO NO:
APPROVED:
Power supply #1 for:
CH1: 12Vin. 3.3Vout 3A for FMC Conn
CH2: 12Vin. VADJ 2A for FMC Conn (1.2V, 1.8V, 2.5V, 3.3V)
Starts with internal 1050KHz clock but
Channels track input voltage to create programmable VADJ
Power supply #2 for:
For setting VADJ to 1.2V, 1.8V, 2.5V or 3.3V
CH2: 12Vin. 5Vout 1.84A for Intermediate
CH1: 12Vin. VADJ 0.5A for FPGA VCC2 (1.2V, 1.8V, 2.5V, 3.3V)
Enable at 10Vin
also accepts external sync clock
Starts with internal 350KHz clock but
also accepts external sync clock
Level shift FMC_PG_C2M
from +5v to +3.3v
Preset VADJ to 2.5V (454.545mV)
When VADJ_SET is 600mV, VADJ output is 3.3V
Preset VADJ to
3.3V (600mV)
(POWER SUPPLY PART 1)
1
PGOOD1
2
SCFG
3
SYNC
4
GND
5
INTVCC
6
RT
7
MODE
8
PGOOD2
9
FB2
10
CO
MP2
11
SS2
12
TRK2
13
EN
2
14
PVIN
2
15
PVIN
2
16
SW2
17
SW2
18
BST2
19
DL2
20
VDRV
21
PGND
22
DL1
23
BST1
24
SW1
25
SW1
26
PVIN
1
27
PVIN
1
28
EN
1
29
TRK1
30
SS1
31
CO
MP1
32
FB1
33
GN
D_PAD
U7
ADP2323ACPZ
C59
0.1uF
C125
0.1uF
L3
4.7µH
C135
3.3nF
C136
470pF
C137
22pF
R66
31K6
C142
560pF
R67
30K9
R68
61K9
R70
16K5
R71
121K
R72
10K
R73
10K
C181
1uF
R74
71K5
1
PGOOD1
2
SCFG
3
SYNC
4
GND
5
INTVCC
6
RT
7
MODE
8
PGOOD2
9
FB2
10
CO
MP2
11
SS2
12
TRK2
13
EN
2
14
PVIN
2
15
PVIN
2
16
SW2
17
SW2
18
BST2
19
DL2
20
VDRV
21
PGND
22
DL1
23
BST1
24
SW1
25
SW1
26
PVIN
1
27
PVIN
1
28
EN
1
29
TRK1
30
SS1
31
CO
MP1
32
FB1
33
GN
D_PAD
U8
ADP2323ACPZ
C187
0.1uF
C188
0.1uF
L4
8.2uH
L5
8.2µH
C193
56nF
C195
4.7nF
C196
68pF
R76
20K5
C197
1.8nF
C198
82pF
R77
17K8
R78
61K9
R87
61K9
C199
1uF
R113
47K
C201
22uF
R114
100K
R115
100K
R124
20K
1
ADDR
2
SCL
3
SDA
4
VDD
5
GND
6
VOUT
U22
AD5622YKSZ-2
R127
48K7
1
IN
2
VD
D
3
GN
D
4
S1
5
D
6
S2
U10
ADG819BRTZ
R129
42K7
R106
C133
1uF
C134
1uF
R69
13K7
R75
13K7
R85
13K7
C180
22pF
C182
27nF
R118
100K
R130
7K87
R131
10K
R128
13K7
L2
2.2µH
C239
0.1uF
C238
0.1uF
C237
0.1uF
D1
D2
G
S
D3
D4
Q3
SI3456DDV-T1-GE3
D1
D2
G
S
D3
D4
Q4
SI3456DDV-T1-GE3
R169
0R
R1206
R176
0R
R1206
R179
0R
R1206
R180
0R
R1206
R120
100K
C132
10µF
C200
10µF
C191
10µF
C192
10µF
R93
0R
R199
0R
R201
1K5
R202
DNP
R203
DNP
R204
DNP
D1
D2
G
S
D3
D4
Q1
SI3456DDV-T1-GE3
D1
D2
G
S
D3
D4
Q2
SI3456DDV-T1-GE3
C126
22uF
C189
47µF
C190
47µF
C203
47µF
C218
47µF
G
S
D
Q9
2N
7002P,2
15
R213
0R
FMC_PWR_GD
GREEN
C194
27nF
R223
10K
R221
93K1
R220
10K
SYS_PWR
GREEN
R222
1K5
R219
93K1
R218
10K
C240
0.1uF
C241
0.1uF
R142
10K
R108
10K
R117
4K7
1
+
3
-
2
GND
5
VCC
4
U26
ADCMP370AKS
1
+
3
-
2
GND
5
VCC
4
U27
ADCMP370AKS
R96
DNP
C242
DNP
R116
20K
FMC_VADJ_PWR_GD
PS_1050KHZ_SYNC_CLK
FMC_POWER_EN
PS_350KHZ_SYNC_CLK
DDR2_PWR_GD
VADJ_SET
VADJ_SET
FMC_VADJ_PWR_GD
FMC_PG_C2M
+12_VIN
+12_VIN
3V3_FMC
VADJ_FPGA
+12_VIN
+12_VIN
VADJ_FMC
+5V
PJ2/SCL
SDA_DAC
+3.3V
VADJ_EN
VADJ_SET
+3.3V
VADJ_2V5_SET
VADJ_2V5_SET
+3.3V
+3.3V
AGND2
AGND2
AGND2
AGND2
AGND2
AGND2
AGND2
AGND2
AGND2
AGND2
AGND2
AGND2
AGND2
AGND1
AGND1
AGND1
AGND1
AGND1
AGND1
AGND1
AGND1
AGND1
AGND1
AGND1
AGND1
AGND1
AGND1
AGND1
AGND2
AGND2
VADJ_SET
AGND2
AGND2
AGND2
VADJ_SET
VADJ_INTVCC
VADJ_INTVCC
VADJ_INTVCC
VADJ_INTVCC
VADJ_INTVCC
AGND2
AGND2
GND
EW + DP + MMcC
TBD
<QC By>
<Released By>
06/Jun/12
<Checked Date>
<QC Date>
<Release Date>
ANALOG DEVICES
SDP-H1
<Code>
A2
TBD SAP #
1.1
<Scale>
12
13
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
A
B
C
D
DATE:
1
2
3
4
5
6
D
C
B
A
LTR
ECO NO:
APPROVED:
4.25-4.75Vin 3.3Vout 250mA
Power supply #3 for:
Power supply #5 for FPGA VCC0
CH2: 5Vin. 2.5Vout 1A for FPGA Vccaux, VCC1 + SRAM
CH1: 5Vin. 1.23Vout 2A for FPGA core
Starts with internal 1050KHz clock but
also accepts external sync clock
Enabled by SDP powering up or BF booting
Pull-downs to keep ADP2323 clock sync
lines low while FPGA is unconfigured
Level shift FMC_PG_C2M
from +5v to +3.3v
(POWER SUPPLY PART 2)
Main power input
Center Positive
1
PGOOD1
2
SCFG
3
SYNC
4
GND
5
INTVCC
6
RT
7
MODE
8
PGOOD2
9
FB2
10
CO
MP2
11
SS2
12
TRK2
13
EN
2
14
PVIN
2
15
PVIN
2
16
SW2
17
SW2
18
BST2
19
DL2
20
VDRV
21
PGND
22
DL1
23
BST1
24
SW1
25
SW1
26
PVIN
1
27
PVIN
1
28
EN
1
29
TRK1
30
SS1
31
CO
MP1
32
FB1
33
GN
D_PAD
U17
ADP2323ACPZ
C204
0.1uF
C205
0.1uF
L7
2.2µH
C210
56nF
C211
56nF
C212
820pF
R138
43K2
C214
1nF
C215
22pF
R139
22K1
R144
10K
R145
10K
C216
1uF
R146
71K5
C220
4.7uF
C221
4.7uF
R149
100K
R150
100K
R151
DNP
R152
0R
R86
20K
R109
200K
C207
1uF
R121
93K1
R143
29K4
C208
22pF
R122
100K
R148
47K
R153
100K
R154
100K
L6
1µH
D1
D2
G
S
D3
D4
Q5
SI3456DDV-T1-GE3
D1
D2
G
S
D3
D4
Q6
SI3456DDV-T1-GE3
R182
0R
R1206
R184
0R
R1206
R192
0R
R1206
C209
10µF
C213
10µF
R147
0R
R198
0R
1
R2
2
D2
3
D2
4
S2
5
ON/OFF
6
R1,C1
U24
SI3861BDV
R196
20K
R197
0R
C44
DNP
C256
L9
IND-VLP8040T-220M
22µH
C257
C217
0.1uF
R205
DNP
R1206
R206
DNP
C131
22uF
C202
47µF
C206
47µF
C255
10µF
1
VOUT
2
VOUT
3
OUTSEN
4
GND
5
EN
6
NC
7
VIN
8
VIN
9
EP
U12
ADP124ACPZ-3.3
R212
0R
R140
23K2
R112
22K1
TP2
TP3
J7-1
J7-2
J7-3
PS_1050KHZ_SYNC_CLK
FPGA_CORE_PWR_GD
FPGA_CORE_PWR_GD
FPGA_2V5_PWR_GD
BOOT_COMPLETE
PS_350KH
Z_SYN
C_CLK
PS_1050KH
Z_SYN
C_CLK
2V5_FPGA
3V3_FPGA_VCC0
+3.3V
+5V
+5V
3V3_FPGA_VCC0
+5V
1V23_FPGA_CORE
+12_VIN
FMC_POWER_EN
+12_VIN_SWITCHED
AGND3
AGND3
AGND3
AGND3
AGND3
AGND3
AGND3
AGND3
AGND3
AGND3
AGND3
AGND3
AGND3
EW + DP + MMcC
SDP-H1
TBD
<QC By>
<Released By>
06/Jun/12
<Checked Date>
<QC Date>
<Release Date>
ANALOG DEVICES
<Code>
A2
TBD SAP #
1.1
<Scale>
13
13
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
A
B
C
D
DATE:
1
2
3
4
5
6
D
C
B
A
LTR
ECO NO:
APPROVED:
Connect as close as
possible to the load via
a low noise PCB trace
Connect as close as
possible to the load via
a low noise PCB trace
1.8V supply to DDR2
0.9V for DDR2 termination
0.9V reference voltage
See table 8 of PM6670AS datasheet
See table 8 of PM6670AS datasheet
See table 9 of PM6670AS datasheet
Select normal or low-ESR compensation
Logic supply taken from intermediate 5V
DDR2 power supplied from 12V line
Switcher/LDO for DDR2 supply, termination and reference
(POWER SUPPLY PART 3)
1
VTTGND
2
VTTSNS
3
DD
RSEL
4
VTTREF
5
SG
ND
6
AVCC
7
VREF
8
VO
SC
9
VSNS
10
MODE
11
CO
MP
12
DSCG
13
S5
14
S3
15
PG
16
PGND
17
LGATE
18
VCC
19
CSNS
20
PHASE
21
HGATE
22
BO
OT
23
LDOIN
24
VTT
25
GN
D_PAD
U18
PM6670AS
R156
3R9
R157
330K
R158
18K
R161
0R
R162
DNP
R163
0R
R164
DNP
R165
DNP
R166
DNP
R167
DNP
R168
0R
R170
330R
D3
L8
8.2uH
C229
100µF
C230
10µF
C231
820pF
D5
R171
4R7
R172
15K
R173
23K2
C234
5.6nF
C235
DNP
C227
10uF
C222
10uF
C247
10uF
C223
56nF
C226
0.1uF
R123
10K
R126
100K
C248
10µF
C249
100µF
C250
100µF
C251
100µF
G
S
D
Q7
DMN2020LSN
G
S
D
Q8
DMN2020LSN
C232
0.1uF
C228
0.1uF
C224
0.1uF
C233
1nF
D6
R159
20K
R160
20K
R186
0R
R1206
R189
0R
R1206
R175
0R
R174
DNP
C225
0.1uF
R211
0R
DDR2_VADJ
DDR2_MODE
DD
R2_VAD
J
PM
6670AS_VREF
DD
R2_SEL
PM6670AS_VREF
DDR2_SEL
DD
R2_D
ISCH
ARG
E
PM6670AS_VREF
DDR2_DISCHARGE
DDR2_MODE
1V8_DDR2_VDDQ
+12_VIN
0V9_DDR2_VTT
0V9_DDR2_VREF
+5V
1V8_DDR2_VDDQ
+5V
1V8_DDR2_VDDQ
DDR2_AVCC
DDR2_AVCC
DDR2_AVCC
DDR2_PWR_GD
FPGA_2V5_PWR_GD
+12_VIN
DDR2_AVCC
AGND4
AGND4
AGND4
AGND4
AGND4
AGND4
AGND4
AGND4
AGND4
AGND4
AGND4
AGND4
AGND4
AGND4