a voltage-controlled dstatcom for power-quality improvement

IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 29, NO. 3, JUNE 2014 1499

A Voltage-Controlled DSTATCOMfor Power-Quality Improvement

Chandan Kumar, Student Member, IEEE, and Mahesh K. Mishra, Senior Member, IEEE

Abstract—This paper proposes a new algorithm to generate ref-erence voltage for a distribution static compensator (DSTATCOM)operating in voltage-control mode. The proposed scheme exhibitsseveral advantages compared to traditional voltage-controlledDSTATCOM where the reference voltage is arbitrarily taken as1.0 p.u. The proposed scheme ensures that unity power factor(UPF) is achieved at the load terminal during nominal operation,which is not possible in the traditional method. Also, the compen-sator injects lower currents and, therefore, reduces losses in thefeeder and voltage-source inverter. Further, a saving in the ratingof DSTATCOM is achieved which increases its capacity to mitigatevoltage sag. Nearly UPF is maintained, while regulating voltageat the load terminal, during load change. The state-space modelof DSTATCOM is incorporated with the deadbeat predictivecontroller for fast load voltage regulation during voltage distur-bances. With these features, this scheme allows DSTATCOM totackle power-quality issues by providing power factor correction,harmonic elimination, load balancing, and voltage regulationbased on the load requirement. Simulation and experimentalresults are presented to demonstrate the efficacy of the proposedalgorithm.

Index Terms—Current control mode, power quality (PQ),voltage-control mode, voltage-source inverter.

I. INTRODUCTION

A DISTRIBUTION system suffers from current as well asvoltage-related power-quality (PQ) problems, which in-

clude poor power factor, distorted source current, and voltagedisturbances [1], [2]. A DSTATCOM, connected at the pointof common coupling (PCC), has been utilized to mitigate bothtypes of PQ problems [2]–[12]. When operating in current con-trol mode (CCM), it injects reactive and harmonic componentsof load currents to make source currents balanced, sinusoidal,and in phase with the PCC voltages [3]–[7]. In voltage-con-trol mode (VCM) [2], [8]–[12], the DSTATCOM regulates PCCvoltage at a reference value to protect critical loads from voltagedisturbances, such as sag, swell, and unbalances. However, theadvantages of CCM and VCM cannot be achieved simultane-ously with one active filter device, since two modes are inde-pendent of each other.

Manuscript received April 07, 2013; revised July 23, 2013; acceptedFebruary 28, 2014. Date of publication April 17, 2014; date of currentversion May 20, 2014. This work was supported by the Department ofScience and Technology, India, under Project Grant DST/TM/SERI/2k10/47(G). Paper no. TPWRD-00399-2013.The authors are with the Department of Electrical Engineering, In-

dian Institute of Technology Madras, Chennai 600 036, India (e-mail:[email protected]; [email protected]).Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/TPWRD.2014.2310234

In CCM operation, the DSTATCOM cannot compensate forvoltage disturbances. Hence, CCM operation of DSTATCOM isnot useful under voltage disturbances, which is a major disad-vantage of this mode of operation [13]. Traditionally, in VCMoperation, the DSTATCOM regulates the PCC voltage at 1.0 p.u.[2], [8]–[11]. However, a load works satisfactorily for a permis-sible voltage range [14]. Hence, it is not necessary to regulatethe PCC voltage at 1.0 p.u. While maintaining 1.0-p.u. voltage,DSTATCOM compensates for the voltage drop in feeder. Forthis, the compensator has to supply additional reactive currentswhich increases the source currents. This increases losses in thevoltage-source inverter (VSI) and feeder. Another important as-pect is the rating of the VSI. Due to increased current injection,the VSI is de-rated in steady-state condition. Consequently, itscapability to mitigate deep voltage sag decreases. Also, UPFcannot be achieved when the PCC voltage is 1 p.u. In the litera-ture, so far, the operation of DSTATCOM is not reported wherethe advantages of both modes are achieved based on load re-quirements while overcoming their demerits.This paper considers the operation of DSTATCOM in VCM

and proposes a control algorithm to obtain the reference loadterminal voltage. This algorithm provides the combined advan-tages of CCM and VCM. The UPF operation at the PCC isachieved at nominal load, whereas fast voltage regulation is pro-vided during voltage disturbances. Also, the reactive and har-monic component of load current is supplied by the compen-sator at any time of operation. The deadbeat predictive con-troller [15]–[17] is used to generate switching pulses. The con-trol strategy is tested with a three-phase four-wire distributionsystem. The effectiveness of the proposed algorithm is validatedthrough detailed simulation and experimental results.

II. PROPOSED CONTROL SCHEME

Circuit diagram of a DSTATCOM-compensated distributionsystem is shown in Fig. 1. It uses a three-phase, four-wire,two-level, neutral-point-clamped VSI. This structure allowsindependent control to each leg of the VSI [7]. Fig. 2 shows thesingle-phase equivalent representation of Fig. 1. Variable is aswitching function, and can be either or depending uponswitching state. Filter inductance and resistance are and ,respectively. Shunt capacitor eliminates high-switchingfrequency components.First, discrete modeling of the system is presented to obtain a

discrete voltage control law, and it is shown that the PCC voltagecan be regulated to the desired value with properly chosen pa-rameters of the VSI. Then, a procedure to design VSI parame-ters is presented. A proportional-integral (PI) controller is usedto regulate the dc capacitor voltage at a reference value. Based

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1500 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 29, NO. 3, JUNE 2014

Fig. 1. Circuit diagram of the DSTATCOM-compensated distribution system.

Fig. 2. Single-phase equivalent circuit of DSTATCOM.

on instantaneous symmetrical component theory and complexFourier transform, a reference voltage magnitude generationscheme is proposed that provides the advantages of CCM atnominal load. The overall controller block diagram is shown inFig. 3. These steps are explained as follows.

A. System Modeling and Generation of the Voltage-ControlLaw

The state-space equations for the circuit shown in Fig. 2 aregiven by

(1)

where

The general time-domain solution of (1) to compute the statevector with known initial value , is given as follows:

(2)

The equivalent discrete solution of the continuous state is ob-tained by replacing and as follows:

(3)In (3), and represent the th sample and sampling period,respectively. During the consecutive sampling period, the valueof is held constant, and can be taken as . After simpli-fication and changing the integration variable, (3) is written as[18]

(4)

Equation (4) is rewritten as follows:

(5)

where and are sampled matrices, with a sampling time of. For small sampling time, matrices and are calculated

as follows:

(6)

(7)

From (6) and (7), ,, , ,

, and . Hence, the capacitor voltage using(5) is given as

(8)As seen from (8), the terminal voltage can bemaintained at a ref-erence value depending upon the VSI parameters , , ,, and sampling time . Therefore, VSI parameters must be

chosen carefully. Let be the reference load terminal voltage.A cost function is chosen as follows [8]:

(9)

The cost function is differentiated with respect to and itsminimum is obtained at

(10)

The deadbeat voltage-control law, from (8) and (10), is given as

(11)

KUMAR AND MISHRA: VOLTAGE-CONTROLLED DSTATCOM FOR PQ IMPROVEMENT 1501

Fig. 3. Overall block diagram of the controller to control DSTATCOM in a distribution system.

In (11), is the future reference voltage which is un-known. One-step-ahead prediction of this voltage is done usinga second-order Lagrange extrapolation formula as follows:

(12)

The term is valid for a wide frequency range [17] andwhen substituted in (11), yields to a one-step-ahead deadbeatvoltage-control law. Finally, is converted into the ON/OFFswitching command to the corresponding VSI switches using adeadbeat hysteresis controller [17].

B. Design of VSI Parameters

DSTATCOM regulates terminal voltage satisfactorily, de-pending upon the properly chosen VSI parameters. The designprocedure of these parameters is presented as follows.1) Voltage Across DC Bus ( ): The dc bus voltage is taken

twice the peak of the phase voltage of the source for satisfactoryperformance [19]. Therefore, for a line voltage of 400 V, the dcbus voltage is maintained at 650 V.2) DC Capacitance : Values of dc capacitors are

chosen based on a period of sag/swell and change in dc busvoltage during transients. Let the total load rating be kVA.In the worst case, the load power may vary from minimum tomaximum that is, from 0 to kVA. The compensator needsto exchange real power during transient to maintain the loadpower demand. This transfer of real power during the tran-sient will result in the deviation of capacitor voltage from itsreference value. The voltage continues to decrease until thecapacitor voltage controller comes into action. Consider thatthe voltage controller takes cycles, that is, seconds to act,where is the system time period. Hence, maximum energyexchange by the compensator during transient will be .This energy will be equal to the change in the capacitor storedenergy. Therefore

(13)

where and are the reference dc bus voltage and max-imum-allowed voltage during transients, respectively. Hence

(14)

Here, 10 kVA, 650 V, 1, andor . Using (14), capacitor values are found to be 2630and 2152 . The capacitor value 2600 is chosen to achievesatisfactory performance during all operating conditions.3) Filter Inductance : Filter inductance should pro-

vide reasonably high switching frequency and a sufficient rateof change of current such that VSI currents follow desired cur-rents. The following equation represents inductor dynamics:

(15)

The inductance is designed to provide good tracking per-formance at a maximum switching frequency ( ) which isachieved at the zero of the source voltage in the hysteresis con-troller. Neglecting , is given by

(16)

where is the ripple in the current. With 10 kHz and0.75 A (5% of rated current), the value of using (16) is

found to be 21.8 mH, and 22 mH is used in realizing the filter.4) Shunt Capacitor : The shunt capacitor should not

resonate with feeder inductance at the fundamental frequency( ). Capacitance, at which resonance will occur, is given as

(17)

For proper operation, must be chosen very small comparedto . Here, a value of 5 F is chosen which provides animpedance of 637 at . This does not allow the capacitorto draw significant fundamental reactive current.


C. Controller for DC Bus Capacitor Voltage

Average real power balance at the PCC will be

(18)

where , , and are the average PCC power, loadpower, and losses in the VSI, respectively. The power availableat the PCC, which is taken from the source, depends upon theangle between source and PCC voltages, that is, load angle .Hence, must be maintained constant to keep constant.The voltage of the dc bus of DSTATCOM can be maintained

at its reference value by taking inverter losses from thesource. If the capacitor voltage is regulated to a constant refer-ence value, is a constant value. Consequently, is also aconstant value. Thus, it is evident that dc-link voltage can beregulated by generating a suitable value of . This includesthe effect of losses in the VSI and, therefore, it takes care ofthe term in its action. To calculate load angle , the aver-aged dc-link voltage ( ) is compared with a referencevoltage, and error is passed through a PI controller. The outputof the PI controller, which is load angle , is given as follows:

(19)

where is the voltage error.Terms and are proportional and integral gains, re-spectively. must lie between 0 to 90 for the power flowfrom the source to PCC. Hence, controller gains must be chosencarefully.

D. Proposed Method To Generate Reference Terminal Voltages

Reference terminal voltages are generated such that, at nom-inal load, all advantages of CCM operation are achieved whileDSTATCOM is operating in VCM. Hence, the DSTATCOMwill inject reactive and harmonic components of load current.To achieve this, first the fundamental positive-sequence com-ponent of load currents is computed. Then, it is assumed thatthese currents come from the source and considered as referencesource currents at nominal load. With these source currents andfor UPF at the PCC, the magnitude of the PCC voltage is calcu-lated. Let three-phase load currents , , and berepresented by the following equations:

(20)

where represent three phases, is the harmonicnumber, and is the maximum harmonic order. repre-sents the phase angle of the th harmonic with respect to ref-erence in phase- and is similar to other phases. Using instan-taneous symmetrical component theory, instantaneous zero-se-quence , positive-sequence , and negative-sequence

current components are calculated as follows:

(21)

where is a complex operator and defined by .

The fundamental positive-sequence component of load cur-rent , calculated by finding the complex Fourier coefficient,is expressed as follows:

(22)

is a complex quantity, contains magnitude and phase angleinformation, and can be expressed in phasor form as follows:

(23)

Hence, the instantaneous fundamental positive-sequence com-ponent of load current in phase- , , is expressed as

(24)

The fundamental positive-sequence component of load currentsmust be supplied by the source at nominal load. Hence, it willbe treated as reference source currents. For UPF at nominal op-eration, the nominal load angle is used. By knowing ,fundamental positive-sequence currents in phases and can beeasily computed by providing a phase displacement ofand , respectively, and are given as

(25)

When reference source currents derived in (25) are supplied bythe source, three-phase terminal voltages can be computed usingthe following equations:

(26)

Let the rms value of reference terminal and source voltagesbe and , respectively. For UPF, the source current and ter-minal voltage will be in phase. However, to obtain the expres-sion of independent of , we assume the PCC voltage as areference phasor for the time-being. Hence, phase- quantities,by considering UPF at the PCC, will be

(27)

Substituting (27) into (26), the phasor equation will be

(28)

Simplifying the above equation

(29)

Equating real and imaginary parts of both sides of (29), thefollowing equation is obtained:

(30)


Fig. 4. Before compensation. (a) Terminal voltages. (b) Source currents.

To remove from (30), both sides are squared and added toobtain the following:

(31)

After rearranging (31), the expression for reference load voltagemagnitude will be

(32)

Finally, using from (32), the load angle from (19), and thephase- source voltage as reference, three-phase reference ter-minal voltages are given as

(33)

III. SIMULATION RESULTS

The control scheme is implemented using PSCAD software.Simulation parameters are given in Table I. Terminal voltagesand source currents before compensation are plotted in Fig. 4.Distorted and unbalanced source currents flowing through thefeeder make terminal voltages unbalanced and distorted. Threeconditions, namely, nominal operation, operation during sag,and operation during load change are compared between the tra-ditional and proposed method. In the traditional method, the ref-erence voltage is 1.0 p.u. [2], [8]–[11], whereas in the proposedmethod, (32) is used to find the reference voltage.

A. Nominal Operation

Initially, the traditional method is considered. Fig. 5(a)–(c)shows the regulated terminal voltages and corresponding sourcecurrents in phases , , and , respectively. These waveforms arebalanced and sinusoidal. However, source currents lead respec-tive terminal voltages which show that the compensator suppliesreactive current to the source to overcome feeder drop, in addi-tion to supplying load reactive and harmonic currents. Fig. 6(a)

TABLE ISIMULATION PARAMETERS

Fig. 5. Terminal voltages and source currents using the traditional method.(a) Phase- . (b) Phase- . (c) Phase- .

Fig. 6. (a) Voltage at the dc bus. (b) Load angle.

shows the dc bus voltage regulated at a nominal voltage of 1300V. Fig. 6(b) shows the load angle settled around 8.50 .Using the proposedmethod, terminal voltages and source cur-

rents in phases , , and are shown in Fig. 7(a)–(c), respec-tively. It can be seen that the respective terminal voltages andsource currents are in phase with each other, in addition to beingbalanced and sinusoidal. Therefore, UPF is achieved at the loadterminal.For the considered system, waveforms of load reactive

power ( ), compensator reactive power ( ), and reac-tive power at the PCC ( ) in the traditional and proposed


Fig. 7. Terminal voltages and source currents using the proposed method.(a) Phase- . (b) Phase- . (c) Phase- .

Fig. 8. Load reactive power ( ), compensator reactive power ( ), andreactive power at PCC ( ). (a) Traditional method. (b) Proposed method.

methods are given in Fig. 8(a) and (b), respectively. In thetraditional method, the compensator needs to overcome voltagedrop across the feeder by supplying reactive power into thesource. As shown in Fig. 8(a), reactive power that is suppliedby the compensator and has a value of 4.7 kVAr is significantlymore than the load reactive power demand of 2.8 kVAr. Thisadditional reactive power of 1.9 kVAr goes into the source.This confirms that significant reactive current flows along thefeeder in the traditional method. However, in the proposedmethod, UPF is achieved at the PCC by maintaining suitablevoltage magnitude. Thus, the reactive power supplied by thecompensator is the same as that of the load reactive power de-mand. Consequently, reactive power exchanged by the sourceat the PCC is zero. These waveforms are given in Fig. 8(b).Fig. 9(a) and (b) shows the source rms currents in phase-

for the traditional and proposed methods, respectively. Thesource current has decreased from 11.35 to 10.5 A in theproposed method. Consequently, it reduces the ohmic lossesin the feeder. Fig. 10(a) and (b) shows the compensator rmscurrents in phase- for the traditional and proposed methods,respectively. The current has decreased from 8.4 to 5.2 A in

Fig. 9. Phase- source rms currents. (a) Traditional method. (b) Proposedmethod.

Fig. 10. Phase- compensator rms currents. (a) Traditional method. (b) Pro-posed method.

the proposed method. Losses in the VSI ( ) represented byresistance , and rating of VSI ( ) are defined as follows:

(34)

(35)

Using (34) and (35), VSI losses are reduced by 61.68% and only61.9% VSI rating is utilized in the proposed method.In the traditional method, DSTATCOM maintains a load

terminal voltage at 1.0 p.u. For this, it needs to compensatefor the entire feeder drop. Hence, at the steady state, the com-pensator supplies reactive power to the source to overcomethis drop. However, in the proposed scheme, the compensatordoes not compensate for the feeder drop in the steady-statecondition. Hence, a lesser rating of VSI is utilized in the steadystate. This savings in rating is utilized to mitigate deep sag, andDSTATCOM capacity to mitigate deep sag increases.

B. Operation During Sag

To create sag, source voltage is lowered by 20% from its nom-inal value at 0.6 s as shown in Fig. 11(a). Sag is removedat 1.0 s as shown in Fig. 11(b). Since voltage regulationcapability does not depend upon reference voltage, it is notshown separately for the traditional method. Fig. 11(c) and (d)shows terminal voltages regulated at their reference value.The controller provides a fast voltage regulation at the loadterminal. Fig. 11(e) and (f) shows the total dc bus voltageand the load angle, respectively. During the transient period,capacitors supply real power to maintain load power whichresults in discharging of capacitors. Consequently, increasesto draw more power from the source compared to normaloperation. After some time, the dc bus voltage again reaches


Fig. 11. (a) Source voltages during normal to sag. (b) Source voltages duringsag to normal. (c) Terminal voltages during normal to sag. (d) Terminal voltagesduring sag to normal. (e) Voltage at the dc bus. (f) Load angle. (g) Compensatorrms current in the traditional method. (h) Compensator rms current in the pro-posed method.

the reference voltage whereas the load angle settles down at17.4 . However, the load angle again settles down at nominalvalue once the sag gets cleared. Compensator rms currentsin the traditional and proposed method in phase- are shownin Fig. 11(g) and (h), respectively. In the proposed method,compensator rms current has decreased to 21.3 from 24.8 A.Loss reduction and percentage loss reduction in the VSI aregiven as

Also, savings in utilization of the VSI rating will be

If the rating of VSI is limited to mitigate 20% sag, then thissavings in rating can be used to mitigate additional sag.To show the capability of DSTATCOM to mitigate deep sag

for a longer time, the source voltage is decreased to 60% of thenominal value for 1 to 3 s duration as shown in Fig. 12(a).

Fig. 12. (a) Source voltages. (b) Terminal voltages. (c) Voltage at the dc bus.(d) Compensator rms current in the proposed method.

Fig. 13. Terminal voltage and source current in phase- during load change.(a) Traditional method. (b) Proposed method.

The terminal voltages, maintained at the reference value, areshown in Fig. 12(b). The voltage across the dc bus is shownin Fig. 12(c). During transients, this voltage deviates from itsreference voltage. However, it is brought back to the referencevalue once steady state is reached. Fig. 12(d) shows the phase-rms compensator current which is large, nearly 47 A, duringthe sag period. These waveforms confirm that the DSTATCOMhas the capability to mitigate deep sag independent of duration.However, it requires a high current rating of the VSI.

C. Operation During Load Change

To show the impact of load changes on system performance,load is increased to 140% of its nominal value. Under this condi-tion, the traditional method gives less power factor as the com-pensator will supply more reactive current to maintain the ref-erence voltage. The voltage and current waveforms, as shownin Fig. 13(a), confirm this. In proposed method, a load changewill result in small deviation in terminal voltage from its refer-ence voltage. Compensator just needs to supply extra reactivecurrent to overcome this small extra feeder drop, hence, nearlyUPF is maintained while regulating the terminal voltage at itsreference voltage. It is evident from Fig. 13(b).


Fig. 14. Experimental results without the compensator.

Fig. 15. Experimental results with the traditional scheme.

IV. EXPERIMENTAL RESULTS

The proposed idea and control strategy are experimentallyverified on a reduced scale setup. To implement the algorithm,the digital signal processor (DSP) TMS320F2812 interfacedwith the host computer is used.Fig. 14 shows the uncompensated waveforms which include

source voltage ( ), terminal voltage ( ), and source current( ). It is seen that the distorted source current flowing throughthe feeder makes the terminal voltage distorted.First, the DSTATCOM operates with the traditional method

and the obtained results are shown in Fig. 15. It shows terminalvoltage ( ), source current ( ), load current ( ), and in-jected current ( ). Here, is sinusoidal even though isdistorted, implying that the compensator supplies reactive andharmonic component of . However, it can be noticed thatthe leads , indicating that the compensator supplies addi-tional reactive current to overcome feeder drop as well.Fig. 16 shows the waveforms with the proposed scheme.

Here, is a sinusoidal waveform in phase with . Hence,the compensator supplies only reactive and harmonic compo-nent of . It provides the advantages of CCM. The differencebetween injected currents in Figs. 15 and 16 can be obtainedby observing their peak-to-peak or rms values. The rms valueof the injected current is reduced to 0.54 A from 0.76 A inthe proposed scheme compared to the traditional scheme. Inaddition, source current is also reduced to 1.86 A from 1.98 Ain the proposed scheme. This results in the reduction of lossesin the VSI as well as in the feeder. Therefore, the capability ofDSTATCOM to mitigate deep sag is increased.

Fig. 16. Experimental results with the proposed scheme.

Fig. 17. Experimental results before, during, and after sag.

A voltage sag of 20% is created by using a programmableac power source. Fig. 17 shows the source voltage, terminalvoltage, dc-link voltage, and injected filter current waveformsbefore, during, and after the sag. It is seen that the terminalvoltage is sinusoidal and maintained at the reference voltage be-fore, during, and after the sag without any significant transient.Hence, the proposed scheme is able to provide fast voltage reg-ulation. During voltage sag, the dc link supplies real power tothe load which results in discharging of the capacitor; hence,voltage decreases. However, the PI controller acts to bring backvoltage at the reference value. Once sag gets cleared, voltageis slowly brought back to its reference by controlling the loadangle. Injected filter current ( ) increases rapidly to supportthe terminal voltage during the sag period, as shown in Fig. 17.Injected and source currents will be more when the referencevoltage is set to 1.0 p.u. It will result in more losses; however,they are not shown here.The experimental results are quite consistent with the simu-

lation results. They establish the effectiveness of the proposedcontrol algorithm.

V. CONCLUSION

In this paper, a control algorithm has been proposed for thegeneration of reference load voltage for a voltage-controlledDSTATCOM. The performance of the proposed scheme is com-pared with the traditional voltage-controlled DSTATCOM. Theproposed method provides the following advantages: 1) at nom-inal load, the compensator injects reactive and harmonic com-ponents of load currents, resulting in UPF; 2) nearly UPF ismaintained for a load change; 3) fast voltage regulation has been


achieved during voltage disturbances; and 4) losses in the VSIand feeder are reduced considerably, and have higher sag sup-porting capability with the same VSI rating compared to the tra-ditional scheme. The simulation and experimental results showthat the proposed scheme provides DSTATCOM, a capability toimprove several PQ problems (related to voltage and current).

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Chandan Kumar (S’13) received his B.Sc. degreein electrical engineering from Muzaffarpur Instituteof Technology, Muzaffarpur, India, in 2009 and theM.Tech. degree in electrical engineering from the Na-tional Institute of Technology, Trichy, India, in 2011.Currently, he is a Research Student with the De-

partment of Electrical Engineering, Indian Instituteof Technology Madras, Chennai, India. His researchinterests include active power filters, power quality,and renewable energy.

Mahesh K. Mishra (S’00–M’02–SM’10) receivedthe B.Tech. degree in electrical engineering from theCollege of Technology, Pantnagar, India, in 1991, theM.E. degree in electrical engineering from the Uni-versity of Roorkee, Roorkee, India, in 1993, and thePh.D. degree in electrical engineering from the In-dian Institute of Technology, Kanpur, India, in 2002.He has teaching and research experience of about

23 years. For about ten years, he was with theElectrical Engineering Department, VisvesvarayaNational Institute of Technology, Nagpur, India.

Currently, he is a Professor in the Electrical Engineering Department, IndianInstitute of Technology Madras, Chennai. His interests are in the areas of powerdistribution systems, power electronics, microgrids, and renewable energysystems.Dr. Mahesh is a life member of the Indian Society of Technical Education.

a voltage-controlled dstatcom for power-quality improvement

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