a versatile 700-1200-v ic process for analog and switching applications

1582 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL 38, NO 7. JULY 1991

A Versatile 700-1200-V IC Process for Analog and Switching Applications

Adriaan W . Ludikhuize

Abstract-An IC process with a wide range of devices up to 1200 V is described. In addition to low-voltage bipolars and CMOS and 230-V VDMOS it provides 700-V high-side LDMOS, HV-PMOS (EPMOS) and low-voltage circuitry, low-side 1200 V LDMOS and 700-V LIGBT, as well as 700-V interconnection. These features have been realized by using a substrate of higher resistance in a previously published 250-300-V IC process and by adaptation in the Resurf structure for lateral DMOS. Application examples for flyback and half-bridge power conversion and as a power-bridge driver are given.

I. INTRODUCTION WIDE variety of high-voltage and smart power struc- A tures for operation above 100 V has been published.

The present IC process uses conventional junction isolation with a high-resistance substrate and an epitaxial layer. Devices for high voltages normally require thick layers. The maximum economic epitaxial thickness in junction- isolated IC's is about 25 pm, assuming up-down diffu- sions for isolation and collector wall. This results in about 250 V as a maximum rating for vertically operating integrated devices such as vertical DMOS (VDMOS) transistors. The technology usually also provides low-voltage bipolar and CMOS components.

Higher voltage capability in IC's is obtained with lateral structures using the Resurf design [ l ] , [2]. In this way, operation up to 1200 V has been reached for low- side lateral DMOS (LDMOS) [3]. For video-output amplifier circuits and half-bridges additional features like high-side LDMOS and complementary HV-PMOS are needed. For these applications, a 250-300-V IC process has been developed [4]; with wider clearances the same process meanwhile has shown 700-V capability for low- side LDMOS [ 5 ] .

For consumer goods dealing with the rectified voltage in European 230-V ac and American 277-V ac off-line applications a related process has been developed for 700- 1200 V with capability to handle some mains-born tran- sients, as was previously reported [ 5 ] , [6]. Here, in a broader way, the technology of this process, the adapated Resurf design for LDMOS transistors and recent 700-V LIGBT results will be discussed and followed by an over- view of further process performance and three typical application examples.

Manuscript received October 5. 1990; revised February 4. 1991. The author is with Philips Research Laboratories. P.O. Box 80.000.

IEEE Log Number 9100057. NL5600 JA Eindhoven, The Netherlands.

11. HIGH-VOLTAGE 700- 1200-V IC TECHNOLOGY The fabrication steps of the present IC process are the

same as those of the previously published Philips 250- 300-V IC process [4] using 13 masks (including scratch protection). Only the substrate resistivity has been changed for the higher voltages.

cm p-type silicon, in which buried layers of phosphorus, antimony, and boron are applied by masked implantation. After 23-pm epitaxy of 5.9 Q cm the deep collector wall and isolation are diffused. Then 0.1-pm gate oxide is grown, and polysil- icon is deposited, doped, and patterned. This is followed by masked implantation of boron at 9 kQ/sq, boron at 285 Q/sq, and phosphorus at 10 Q/sq. Subsequently, dielectric layers are deposited consisting of 0.8 pm of oxide, a thin nitride, and 1.6 pm of oxide, in which oversize and normal contact windows are defined. Finally AI-Si is deposited and patterned, and a nitride scratch protection is applied with openings to the bond pads.

A schematic cross section of the principal devices is given in Fig. 1 . The low-voltage devices consist of bipolar with a maximum V,., rating of 80 V for n-p-n and 230 V for p-n-p and of CMOS with 8- and 15-V operating voltage. On the buried n+ layer as used for the bipolar devices, vertical DMOS is obtained with BVds = 250 V. The modified substrate resistivity has no influence on these devices, and their properties are the same as reported in [4]. For the higher voltages the substrate doping is important.

The high-side rating of LDMOS and HV-PMOS to the substrate is limited by punchthrough of the high-side pt junctions (Fig. 2). Punchthrough occurs when the depletion layer from the substrate junction reaches a long way in the epitaxial layer and starts attacking the built-in bar- rier of the upper p-n junction. Equation (1) in [4] gives as appoximation for the punchthrough voltage Vp,

Processing starts on (100) 9 0 4

where thJ is the epitaxial thickness (of constant doping) between the upper p-layer and the substrate. From (1) it follows that a lower substrate doping for the same epitaxial layer with Nep, > 6.2 X lOI4 cm-3 will increase VpI above 280 V as obtained for the previous process (with 30 Q cm and th,(eff) > 16 pm). For VpI above 700 V the substrate doping NSub must be below 1.5 x lOI4 cm-3 ( p above 80 Q . cm at r,,(eff) > 17 pm).

0018-938319110700-1582$01.00 @ 1991 IEEE

LUDIKHUIZE: A VERSATILE 700-1200-V IC PROCESS

S G D S G D Vdd Vss S G D B E C

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S G D

LDMOS EPMOS High-side CMOS VDMOS npn 1200SL-700SH 700V 700V 250V 80Vcea

Fig. I . Cross section of the principal devices (700-1200-V IC process).

LDMOS-SH EPMOS-DH

Fig. 2. Punchthrough to substrate of high-side p junctions

t------ \ / I 1-4 p substrate I

Fig. 3 . Breakdown calculation of buried n t layer to substrate (735 V 'for 80-Q . cm substrate and radius = 100 pm).

The high-side rating of LV circuitry built on a buried nf layer is limited by edge breakdown of this buried layer to the substrate. When the deeper diffused buried sinker is used as a guard ring, the 2-D calculation (Fig. 3 ) shows that an 80-0 cm substrate is sufficient to increase the breakdown voltage from 450 to above 700 V. So, by decreasing the substrate doping by a factor of about 3 , sufficiently high voltage ratings are obtained for both items. The epitaxial Resurf operation, however, is severely worsened by doing this, as is discussed in the LDMOS design section.

111. LATERAL DMOS TRANSISTORS (LDMOS) Fig. 4 reviews important features for LDMOS design

and application. A high drain voltage capability for low- side operation (Fig. 4(a)) is obtained by Resurf coopera- tion of top, side, and substrate depletion layers. Before breakdown occurs at the edges of the back gate or the stepped field plate, the lateral FET in the drain drift region must be pinched off. This sets a maximum to doping and thickness of the epitaxial layer, dependent on the substrate. After pinch-off, higher drain voltages will be spread toward the drain until ultimately, for sufficiently wide spacing, the vertical breakdown limit to the substrate is reached. A high source-to-substrate voltage capability for high-side operation (Fig. 4(b)) is obtained when depletion from the substrate does not cause punchthrough to the

__-_----------_ 0 6

/ p;- ___------ - - 4 -

LDMOS-SH at high Vs,sub

(b)

high-side (b) device Fig. 4 Cross sectlon of Resurf LDMOS transistor as low-side (a) and as

backgate. This sets a minimum to doping and thickness of the epitaxial layer, dependent on the substrate. Fur- thermore, for circuit application, it is important to note that at high-side operation the on-resistance increases due to a decreasing conductive cross section, and that forward biasing of the internal diode from back gate to drain must be prevented since it is part of a high-gain p-n-p transistor to the substrate.

When the substrate doping is decreased, the depletion by the substrate in the epitaxial drift region is reduced, and the equipotential lines are shifted toward the source, implying a lower drain voltage capability. Fig. 5(a) shows the potential lines of a 700-V LDMOS design in the previous process on a 30-0 cm substrate, using a stepped field plate for enhanced top-sided depletion. The calculation with a 2-D Poisson solver agrees with the measured breakdown above 700 V at sufficiently wide spacings. When the substrate resistivity increases to 80 0 * cm, as shown in Fig. 5(b), the equipotential lines are concen- trated at the source side and premature breakdown is calculated at about 300 V at the field plate; walk-out and instability limit the measured values to about 400 V. So for higher voltages with the same epitaxial layer (with dope times thickness of about 1.6 x 10l2 cm-2) in some way the depletion of the epitaxial FET in the drain must be enhanced again.

For low-side LDMOS, enhanced depletion can be obtained by using a lightly doped buried p-layer locally un- der the source, which causes locally more depletion from the substrate side [7]. Since the available buried p-layer in the present process has a rather high doping level, it cannot extend too far toward the drain and provides only low-side LDMOS up to about 650 V in this way.

For LDMOS with high-side capability only enhanced depletion from the top side is a possible solution, other- wise punchthrough to the high-side back gate will occur.

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30 Ohmcm s u b s t r a t e

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 38. NO. 7. JULY 1991

80 Ohmcm s u b s t r a t e

I p s u b s t r a t e 80 Ohmcm 1

Fig. 5 . Calculated equipotential lines for LDMOS with stepped field plate at 700 V for substrates of 30 Q . cm (a) and 80 Q . cm (b).

For this the available lightly doped top-side p-region can be used, which (in the silicon) provides a lower pinch-off value than a stepped field plate (on the silicon) [4]. Cal- culated pinch-off voltages of the lateral FET between the substrate and the field plate (oxide 0.8 pm) or between the substrate and the top-side p-layer as found with [4, eqs. (2) and (3)] are 130 and 80 V for the previous process, and 180 and 110 V for the present one. This gives only an indication of the effect of the lightly doped p-region, since, due to the short channel of the FET, the voltages in the source region will increase above the pinch-off voltages. In Fig. 6(b), a 2-D calculation with a lightly doped top-side p-region is shown; at 700 V, smoothly spreaded equipotential lines are obtained as before (Fig. 6(a)). For DMOS, the p-region must be inter- rupted close to the source, as is shown, since electrons from the channel must be able to pass [8]. Furthermore, the p-layer in the process has been optimized for the HV-PMOS, and has a rather high dose of about 2 X l o i 2 cm-2. Therefore, the p-region is split into floating rings to reduce the average doping level. For calculations on these floating rings a special algorithm has been added to the Poisson solver. With these rings, low-side LDMOS up to almost 1400 V at wide spacings is realized (Fig. 7), approaching the vertical breakdown limit of the new process, as well as high-side LDMOS of more than 800 V .

A larger drift length for higher SV,, involves a higher on-resistance. A typical LDMOS on-resistance times device active area (& * A,,,) is shown versus breakdown voltage in Fig. 8(a). Power devices have been made with resistances of 0.27 Cl mm2 at 35 V to about 48 Cl * mm2 at 1100 V. For high voltages, Ron * A,,, increases with breakdown voltage at an exponent of about 1.7. The p-rings in an LDMOS structure increase the on-resistance by about 25%; at the same time, they also improve the output impedance, extend the voltage range, and allow for high-side devices. Both with and without rings the on- resistance for high-side operation increases by about 30- 40% at 300 V , which is a lower factor than in the previous process, due to the lower substrate doping. In Fig. 8(b), a comparison is given of typical on-resistance times device total area (Ron * A,,,,) versus V,,, for IC transistors

s t e p p e d f i e l d p l a t e f loa t ing p - r i n g s

Fig. 7. Measured I,,)-V+ characteristics of low-side Resurf LDMOS with wide spacings.

BV (V) 200 500 1000

(a) (b)

Fig. 8. Typical on-resistance of DMOS transistors, for commercial dis- crete VDMOS (i~) and for devices of the present process: VDMOS ( X ) ,

LDMOS with fieldplate (+), and LDMOS with p-rings (*). In (a) as R,,, * A,,, versus breakdown voltage, in (b) as R,,,, * A,,,, versus maximum voltage.

of several square millimeters and for large commercial VDMOS transistors. For discretes, the total chip area is considered, and for IC the chip area including the isolation. As V,,,, of LDMOS, 90% of the breakdown value is assumed. The slope of the graph for LDMOS indicates a voltage dependence of 1.8, which is lower than for dis- crete VDMOS (about 2.1) or for the vertical silicon limit (about 2.4). It means that above about 400 V, LDMOS shows a lower typical on-resistance than vertical DMOS.

The floating rings are used here in the active transistor area, which may cause switching problems as was discussed in [5] and [6]. When the drain voltage increases, the rings will follow the drain voltage until punchthrough to the main junction charges them negatively and depletes

LUDIKHUIZE: A VERSATILE 700- 1200-V IC PROCESS I585

them. When the drain voltage now decreases at device turn-on, the rings remain charged and their negative potential involves a high device on-resistance until holes are supplied by punchthrough or leakage. As shown in [5] and [6], a suitable layout has increased the on-resistance by only 6% after 200 ns.

IV. LATERAL INSULATED GATE BIPOLAR TRANSISTOR (LIGBT)

A cross section of an LIGBT with a “shorted anode” is shown in Fig. 9. The device is in fact an LDMOS with a p injector (anode) connected to the drain. This shorted construction is advantageous for a relatively fast turn-off. The off-state blocking voltage is limited by punchthrough of the p-anode to the substrate, which is above 700 V in the present process. Fig. 10 presents the static properties of a 700-V LIGBT with 0.55-mm2 active area. At low drain current LIGBT device behaves like an LDMOS. At increasing current and on-state voltage (at 1.7 V in Fig. IO) , the epitaxial voltage drop causes hole injection from the anode. This anode is part of two p-n-p transistors: one to the substrate which draws only a small current due to the high substrate resistivity, and one to the back gate. The latter gives the wanted conductivity modulation to- gether with electrons from the DMOS channel and reduces the on-state voltage. As a typical value at 3Vc1.,, 330 mA is obtained corresponding to 60 A cmp2 for the active area; this is a good value [9], being five times higher than the comparable LDMOS and less dependent on temperature.

The current in the back gate flows through a parasitic base resistance which may cause forward biasing of the internal n-p-n transistor at the DMOS source. This results in snap-back behavior; if p-n-p and n-p-n have sufficient gain, latch-up occurs and gate control is lost. For this sea- son, a low ohmic contact to the back gate must be provided.

The static currents to the substrate must be considered as well. The hole current in the substrate for the device of Fig. 10 is about 5-10% of the draidanode current, the minority (electron) current as measurcd in an adjacent island is only a few nanoamperes. Thus a good substrate connection and some layout distance to sensitive devices will be acceptable for most IC applications. For a good switching performance, the anode has to have its n and p areas positioned not exactly like those in Fig. 9, but al- ternating in the direction perpendicular to this figure. In this way, 200-11s turn-off recovery has been obtained. The switching behavior is discussed below in a flyback application.

V. OTHER COMPONENTS A N D PROCESS FEATURES The HV extended-drain PMOS transistor (EPMOS,

Fig. 11) consists of a PMOS with an epitaxial back gate and a lowly doped p extension in the drain, optimized for this device at about 9 kQ/sq [4]. At high drain voltage the drift region is pinched gradually by the top-sided

Fig. 9. Cross section of Resurf LIGBT with shorted anode (to drain)

Fig. 10. Measured [,,,-V,,$ characteristics of 700-V LIGBT anode (0.55-mm’ active area).

D G S

with shorted

Fig. 1 I . Cross section of extended-drain PMOS (EPMOS) transistor.

stepped field plate and the bottom-sided epitaxial and n f buried layers. For wide spacings in the present process a breakdown value above 700 V is obtained (Fig. 12), limited by the buried-layer breakdown. The HV-PMOS is less suitable for power application due to the higher back-gate resistance, the longer layout dimensions, and the lower hole mobility, but it is useful for analog and monitoring functions.

For island isolation above 150 V the same p-implantation is used at isolation edges as rings or mul- tiple floating rings, resulting in a better spread of the potential. This provides improved breakdown to above 1200 V for island isolation and to above 700 V for HV interconnection [4]. Furthermore, a wide variety of JFET’s up to 1200 V is available with pinch-off voltages between 5 and 180 V for many functions, as well as various diodes, resistors, and small capacitors.

As a special feature of the process, the buried p-layer placed on the buried n-layer can also be used up to above 700 V. By this feature, high-side circuitry consisting of CMOS and vertical, isolated n-p-n and p-n-p transistors with up to 15 V capability can be made in the same n +

1586 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 38, NO. 7. JULY 1991

Fig. 12. Measured l , , -V+ characteristics for EPMOS with wide spacings.

TABLE 1 COMPARISON OF MAXIMUM DEVICE RATINGS

Previous Process Present Process Item in Process Target Min. Values Realized Values

Substrate ( Q . cm) LDMOS low side V,,, LDMOS high side V>.,",, Low voltage on n + to sub Isolated subs-island to sub EPMOS low side V,,, EPMOS high side V , ,ub

VDMOS V,, LIGBT low-side Vdr Interconnection

30 700 V 280 V 400 V

80 v 400 V 280 V 230 V

(280 V) 700 V

90 1350 V 950 V 850 V 850 V 780 V 780 V 260 V 720 V

1000 v

Application target video amplifier mains related

tub. This has been used in a driver circuit for power bridges [lo]. It offers a smaller layout, lower parasitic capacitances, and lower d V / d t inside the high-side circuitry. It also allows an injection-free voltage swing of the ground side of low-voltage circuitry below the substrate voltage of as much as 15 V, which is limited by the 15-V positive supply voltage on the n+ layer.

Table I summarizes a wide range of voltages and devices as realized in the present IC process. The left col- umn gives the target values of the previous process [4] for comparison.

VI. APPLICATION EXAMPLES Many circuits are possible with the presented technol-

ogy. For economic reasons the application will be focused on interface and low-power functions. As examples, a 6-W flyback power conversion application, a 15-W half- bridge, and a 700-V driver circuit for power bridges will be considered.

In the flyback power converter circuit of Fig. 13, the test transistor is switched on and the current in the coil increases linearly with time. At a chosen current level the transistor is switched off and the drain voltage rises steeply until it is clamped to about 70 V above the supply rail while at the same time the secondary winding is deliver- ing the energy of the coil to the load. Fig. 14(a) shows the waveform for a 750V/20 C2 LDMOS transistor of 1.75-mm2 chip area at 650 V dc. A hard gate drive pro- duces a sharp initial current peak rising to 1 A in 10 ns, caused by discharge of parasitic capacitors, mainly of the

Fig. 13. Flyback converter test circuit

coil; for better visibility a softer gate drive has been used. After this, the current increases with time. At 0.36 A the transistor is turned off, the current drops rapidly, and the drain voltage rises to 720 V in about 70 ns, which means 10 kV/ps. It shows the good SOAR behavior of this LDMOS design. The small current after transistor turn- off is caused by the depletion capacitances in the transistor (about 5 pF). At a frequency of 40 kHz, the converted power is about 6 W. The device losses, consisting mainly of conduction loss in R,, (increasing with temperature) are Po, = ff * R,, - I ; * ton = 0.04 W (with f = frequency and I , = maximum current of the sawtooth waveform). The losses caused by the turn-on peak amount to Pcap = if C V 2 = 0 . 3 8 W in this case. Fig 14(b) shows the waveforms for a 700-V LIGBT of 0.71-mm2 chip area. It shows again the sharp current peak at turn- on. At about 0.3 A (due to the layout 9.5-V gate drive was the maximum for this sample) the transistor is turned off, the current drops quickly, but then has a typical turn- off tail lasting about 200 ns, while the anode voltage rises at the same time. Device losses now consist of conduction loss over V,,, (increasing slowly with temperature) and turn-off loss proportional to the switching frequency. At 50 kHz, the converted power is about 5 W. The on-state loss is roughly Po, = if ; V,, * I, * t,, = 0.02 W. The turn-off loss is Pturn.oR = 6 f . Z, . V, ttall, which in the present example at 50 kHz, I,n = 0.3 A, V, = 500 V, t = 200 ns is 0.25 W. At higher current, lower frequency, and higher temperature, the advantage over LDMOS be- comes more pronounced.

The schematic diagram for an integrated 450-700-V half-bridge power converter is shown in Fig. 15. When the low-side transistor T1 is on, the current in the coil increases from right to left, and bootstrap capacitor C, is charged via a HV diode D5 to 12 V. Now T1 is turned off rapidly via a diode. The current in the charged coil continues and drives the output above the supply rail. This coil current should never turn on the internal diode of high-side transistor T2, since this is part of a high-gain parasitic p-n-p transistor to the substrate with a high voltage on the collector. Therefore, a high-side diode 0 2 is required, which must have a low parasitic p-n-p current to the substrate. A low-voltage n-p-n diode with high-side capability meets these demands. The coil current must be conducted by the external flyback diode 0 4 . Now transistor T2 is turned on with some delay (break before make), realized by a resistor to capacitor C,. The current in the coil decreases to zero and increases from left to right.

1587 LUDIKHUIZE: A VERSATILE 700-1200-V IC PROCESS

Fig. 16. Waveforms of half-bridge circuit switching 15 W into 3 mH + 500 fl from rectified 230 V ac. operating without diodes D1 and 0 3 . Horiz: 5 ps/div; vert: output current (0.1 A/div), output voltage (100 V/div) and substrate current (10 mA/div).

(b)

Fig. 14. 700-V devices at flyback conversion of about 6 W. Horiz: 200 ns/div. Vert: Id at 0.1 A/div. V,,$ at 200 V/div (current display 20-ns delay) for LDMOS at V,,, = 650 V (a) and for LIGBT at V,,, = 500 V (b).

Fig. 15. Schematic diagram of integrated half-bridge

Then T2 is turned off rapidly by switching the level-shift transistor T3 on; at 0.7 V the gate is protected by a diode. The current in the charged coil continues and discharges the output below zero. This turns on the intemal diode of T1, but also the parasitic n-drain to p-substrate diode, which thus injects minorities (electrons) into the substrate. A test circuit has been shown to function in this way (Fig. 16); at 0.3 A current it injects about 10 mA into the substrate (this value will probably depend on the layout). The current will partly be collected by the n-island of the high-side transistor and causes dissipation (about 0.15 W for 15-W output at 300 V at room temperature). An additional external flyback diode 0 3 reduces the substrate current considerably. A much safer solution for higher temperature uses a high-side series diode 0 1 ; its anode must not be connected to an n-island. A low- voltage p-n-p diode with high-side capability meets this

demand. Finally, with some delay T1 is tumed on again. Of all the components in Fig. 15, apart from the load, only the flyback diode(s) and the capacitors C, and C,, cannot be integrated in the present process. Fig. 16 has been obtained from an integrated 450-V half-bridge with an 1 1 4 low-side LDMOS of 1 .43-mm2 and an 8 4 high- side LDMOS of 2. 18-mm2 chip area. The dissipation for 15-W output to a fluorescent lamp circuit at room temperature is about 0.5 W.

The level-shift circuit in Fig. 15 may not function cor- rectly for every application. When T2 is tumed off, its source goes down rapidly and the gate must follow, oth- erwise T2 is turned on again. Thus the level shifter T3 must be large enough to sink the charge related to C,, (Miller effect). However, a large current capability of T3 gives also losses and current spikes by short-circuiting the charged output capacitances. Also the break-before-make function may not operate properly and involves a slowly rising gate voltage.

A much better solution is provided by a dedicated bridge-driver circuit. A schematic diagram of such a driver circuit for 700-V power bridges [IO] is shown in Fig. 17. It makes use of many process features, such as 800-V low- side LDMOS for the level-shift transistors, 700-V for the high-side island with CMOS and bipolar LV components, and 700 V for the interconnection. The input signals are converted, including shoot-through protection and break- before-make delay, in the logic block to short set and reset pulses of about 3 mA for the level shifters. The level shifters drive the high-side and low-side blocks, each with a differential input stage, a latch, and an output stage with 0.5-A source and sink current to the gates of the power transistors. Since the set and reset currents are pulsed, the total chip dissipation is very low. In the photograph of the chip of 5 mm2, as shown in Fig. 18, the various blocks are clearly visible. Of all the components in Fig. 17, apart from the power transistors and the load, only the capaci-

1588 IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 38. NO. 7 . JULY 1991

HV

V

C

H L

Fig. 17. Schematic diagram of integrated half-bridge driver. Fig. 19. Waveforms of power bridge and bridge driver at = 700 V and P,,,, = 150 W (1.8 mH + 330 R load). Horiz: 10 ps/div; vert: bridge output current ( I A/div), output voltage (500 V/div), and gate voltages

Fig. 18. Photomicrograph of bridge-driver circuit

of high-side (500 V/div) and low-side (20 V/div) power transistor.

Fig. 20. Waveforms of power bridge and bridge driver at V<,< = 6( without d V / d t slope reduction. Horiz: 200 ns/div: vert: bridge output rent ( I A/div), output voltage (500 V/div), and gate voltage of low (20 V/div) and high-side (100 V/div) power transistor (1.8 mH + 3 load, P,,,, = 120 W).

10 v cur-

-side 30 R

power converter described above), the RFI problems orig- inating from the high dV/dt may be reduced by a large output capacitor (dashed in Fig. 19). However, a quick switchover of the bridge now involves dissipation of the capacitive energy in the power transistors, and again a high d V / d t .

For this situation as a special feature a slew-sense circuit is included [ 101. By means of a simple integrable capacitor, the d V / d t is sensed and used for a delayed turn- on. In Fig. 20 the bridge output without slope reduction is shown in more detail. First, for a rising output the low- side gate is discharged to its source and the coil causes a slew-up to 600 V in 70 ns; with 700-11s delay from the shoot-through protection the high-side gate is turned on. For a falling output the high-side gate is discharged to its source and the coil causes a slew-down to 0 V in 70 ns; with 500-11s delay from the shoot-through protection the low-side gate is turned on. In Fig. 21 the same bridge

Fig. 21. Waveforms for the same bridge with 1.2-nF output capacitor for d V / d t slope reduction and 1.5-pF sense capacitor for slew sense delay. Horiz: 500 ns/div; vert: bridge output current ( 1 A/div), output voltage (500 V/div), and gate voltage of low-side (20 V/div) and high-side (100 V/div) power transistor.

with a 1.2-nF slope reduction capacitor and with slew- sense delay is shown. For a rising output, again the low- side gate is discharged to its source; the coil now charges 1.2 nF and causes a smooth slew-up in 1 p s to 600 V (notice the different time scale). After an additional 500 ns from the shoot-through protection the high-side gate is turned on. For a falling output the high-side gate is discharged to its source, the output slews down to 0 V in 1 p s , and after an additional 500-ns delay from the shoot- through protection the low-side gate is turned on. For more details and additional integrated features the reader is referred to [ 101.

LUDIKHUIZE: A VERSATILE 700- 1200-V IC PROCESS

VII. CONCLUSION A versatile IC process has been described with a wide

variety of devices up to 1200 V. The application examples show the potential for off-line interface and low- power IC’s made in this process. Integration of high- power functions (above about 50-100-W output) is not envisaged for economic reasons.

ACKNOWLEDGMENT The author wishes to thank his colleagues for their

stimulating contributions, in particular H. Punter for processing, J . de Boet for device simulation, A . Emmerik for device discussion, F. Schoofs for many application top- ics, and C . Dupont for bridge driver work.

REFERENCES 111 J . A. Appels and H. M. J . Vaes, “High voltage thin layer devices

(Resurfdevices),” in IEDM Tech. D i g . , 1979, pp. 238-241.

~

677-683, 1990.

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H. M . J . Vaes and J . A . Appels, “High voltage, high current lateral devices,” in IEDM Tech. Dig . , 1980, pp. 87-90. M . F. Chang et a l . . “Lateral HVIC with 1200 V bipolar and field- effect devices,” IEEE Trans. Electron Devices, vol. ED-33, pp.

A. W. Ludikhuize. “A versatile 250/300 V IC process for analog and switching applications,” IEEE Trans. Electron Devices, vol. ED-33.

- , “Design aspects of high-voltage devices for a versatile 700-1200 V IC process,” in Electrochem. Soc. Spring Meet. Ext. Abstr.. 1989,

- , “Design aspects of high-voltage devices for a versatile 700- 1200 V IC process,” in Proc. Svmp. on H V and Smurt Powzer IC’s, M. A. Shibib, Ed. (Electrochem. SOL.. Proc., vol. 89-15, pp. 133- 138, 1989). E. H . Stupp et al. , “Low specific on-resistance 400 V LDMOST,” in IEDM Tech. Dig, 1981, pp. 426-429. A . W. Ludikhuize, “High-voltage DMOS and PMOS in analog IC’s,” in IEDM Tech. Dig . . 1982, pp. 81-84. Y. Yamaguchi et ul., “New anode structure for HV LIGBTs,” in Ext. Abstr. 22nd Int. Con$ Sol.Si. Dev. and Mat. (Sendai, Japan, 1990), pp. 677-680. F. A . C. M . Schoofs and C. N . G . Dupont, “A 700-V interface IC for power bridge circuits,” IEEE J . Solid State Circuits, vol. 2 5 , pp.

1992-2001, 1986.

pp. 2008-2015, 1986.

pp. 399-400.

a versatile 700-1200-v ic process for analog and switching applications

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