a variable gain amplifier for uwb systemsa variable gain amplifier for uwb systems eecs 413 final...
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![Page 1: A Variable Gain Amplifier for UWB SystemsA Variable Gain Amplifier for UWB Systems EECS 413 Final Project Presentation Advisor: Prof. David Wentzloff Ting Chang Hsin‐Han Huang Variable](https://reader033.vdocuments.us/reader033/viewer/2022060209/5f04762e7e708231d40e15cb/html5/thumbnails/1.jpg)
A Variable Gain Amplifier for UWB Systems
EECS 413 Final Project Presentation
Advisor: Prof. David Wentzloff
Ting Chang
Hsin‐Han Huang
Abhishek Mitra
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MotivationMotivationBlock diagram of a UWB transmitter and receiver:
Design an amplifier with:‐ Variable gain range > 30dB‐ Bandwidth > 528MHz ‐ Gains controlled by adigital counterpart
‐ Common‐mode feedback‐ A stable biasing circuit
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Block Diagram of proposed VGABlock Diagram of proposed VGA
Constant gm Biasing Circuit
CMFB
Input Output
Gilbert Cell Post Amp
p
Digital Control Circuit
B1
B2
B3
B4
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Variable Gain Amplifier (VGA)Variable Gain Amplifier (VGA)
●Gilbert Cell‐M1‐M4: cross‐connectedM1 M4: cross connected‐M5‐M6: diode‐connected‐M7‐M8: PMOS current source
( )/W L
Gain depends on the ratios of gm
( )( ) ( )1,2,3,4
1 21 25,6
/ 2/V
W LA I I
W L I I= −
+
●Tradeoffs: gain, bandwidth, headroom, power
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VGA PMOS Current Source LoadVGA ‐ PMOS Current Source Load
6
1Gain gm∝
6 6gm II I I
∝
=
M8 removes 75% of the total current
6 8totalI I I= −
Gain doubles
Issues: value of I6 & size of M8
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Common Mode Feedback (CMFB)Common‐Mode Feedback (CMFB)Keeps output DC voltage level at constant in order toKeeps output DC voltage level at constant in order to drive the following stage properly
● CM level sensing using PMOS’s operating indeep triode region as large resistors
●Working together with a capacitor, AC signalscan be removed
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Digital Control Circuit: 2 choicesDigital Control Circuit: 2 choices
• Choice 1: Convert from control inputs to analog controlto analog control voltage using R‐2R ladder
• Choice 2: Use binary weighted currents to control the gain
OUR CHOICE !!
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Digital Control Circuit: RequirementsDigital Control Circuit: Requirements
• Single Stack in Current Path to increase headroom• Single Stack in Current Path to increase headroom
• Makes use of a subtraction topology
• Base currents are setup at the tail of the Gilbert Cell
C Mi f h• Current Mirrors are set up from the constant gm Biasing Circuit and CMFB
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Digital Control Circuit: WorkingDigital Control Circuit: WorkingI1+5uA 2I1+5uA I2+475uA
B2
‐‐‐Mirrored CurrentCurrent Path
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Digital Control Circuit: PerformanceDigital Control Circuit: Performance
• Linear dependence of Gain on Differential current
• Moderate power• Moderate power consumption
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Post AmplifierPost Amplifier
1gLinearity?
11
mm
m S S
gGg R R
= ≈+
Headroom?
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Post AmplifierPost Amplifier
1m Sg sR CG +1 11 || ( )
m Sm m
m Sm S
gG gg Rg R
sC
= =++
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Constant Gm BiasingConstant‐Gm BiasingSt t
3 4 2SG SG SV V I R= +Start‐up circuit
2 2I I1I 2I
1 22' '
2 2( / ) ( / )th th S
P p P p
I IV V I Rk W L k K W L
+ = + +
2
2 2
2 1 11( / )
IC W L R K
⎛ ⎞= −⎜ ⎟⎝ ⎠
2 2( / )P OX N SC W L R Kμ ⎜ ⎟⎝ ⎠
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Simulation ResultsSimulation Results
F R
1820
Frequency Response
121416
681012
ain (V/V
)
246G
a
0
1.00E+04 1.00E+06 1.00E+08
F (H )Frequency (Hz)
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Simulation ResultsSimulation Results‐ Corners
0.725
Corners
0 3
0.4
0.5
0.6
15
20
0
0.1
0.2
0.3
0
5
10
0
1.00E+04 1.00E+05 1.00E+06 1.00E+07 1.00E+08 1.00E+09 1.00E+10
SS_0C FF_75C SS_75C FF_0C TT
0
1.00E+04 1.00E+05 1.00E+06 1.00E+07 1.00E+08 1.00E+09 1.00E+10
SS_0C FF_75C SS_75C FF_0C TT
Maximum Gain Minimum Gain
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Simulation ResultsSimulation Results
12
Power
8
10
ower (m
W)
4
6P
0
2
TT SS_0C SS_75C FF_0C FF_75C
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ConclusionsConclusions
• A Gilbert Cell with gain proportional to
PMOS t l d d bl th i
IΔ
• PMOS current source loads doubles the gain
• Step currents set by a Digital Control circuit p y g
• CMFB stabilizes output DC voltage level
d h d k• A 6‐dB Post‐Amp with inductive peaking
• A design of constant‐gm biasing circuitdes g o co s a g b as g c cu
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Result TableResult Table
tion
TT SS_0C SS_75C FF_0C FF_75C
Max Gain (dB) 25.38 25.76 25.42 24.49 24.97
Max Gain (V/V) 18.568 19.412 18.654 16.778 17.714
Extrac Min Gain (dB) ‐6.073 ‐4.734 ‐3.707 ‐10.92 ‐6.140
Min Gain (V/V) 0.4970 0.5798 0.6526 0.2844 0.4932
Bandwidth (MHz) 689 635 517 939 775
Power (mW) 9 101 8 950 11 36 7 048 10 58Power (mW) 9.101 8.950 11.36 7.048 10.58
atics
Max Gain (dB) 25.38 25.76 25.41 25.08 24.97
Max Gain (V/V) 18.568 19.412 18.652 17.946 17.716
Min Gain (dB) ‐6.069 ‐4.734 ‐3.707 ‐9.005 ‐6.136
Sche
m
( )
Min Gain (V/V) 0.4972 0.5798 0.6526 0.3546 0.4934
Bandwidth (MHz) 899 821 637 1333 1030
Power (mW) 9.266 9.020 11.36 8.600 10.76
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Thank You !Thank You !
Questions?Questions?
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ReferencesReferences
[1] Chia‐Hsin Wu et. al., “A 2GHz CMOS Variable Gain Amplifier with 50 dB Linear‐in‐Magnitude Controlled Gain Range for 10GBase‐LX4 Ethernet”, ISSCC 2004.
[2] Quoc‐Hoang Duong et.al, “An All CMOS 743MHz Variable Gain Amplifier for UWB Systems”, IEEE International Symposium on Circuits and Systems 2006.
[3] Sivasankari Krishnanji, “Design of a Variable Gain Amplifier for an Ultra Wideband Receiver”, Master’s Thesis, Texas A&M University.
[4] Po‐Chiun Huang, Li‐Yu Chiou, Chorng‐Kuang Wang, “A 3.3V CMOS Wideband Exponential Control variable‐gain‐amplifier”, Proceedings of the IEEE International Symposium on Circuits and Systems, 1998.y p y ,