a true-zero load stable capacitor-free cmos low drop-out regulator with excessive gain reduction a...
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A True-Zero Load Stable Capacitor-Free A True-Zero Load Stable Capacitor-Free CMOS Low Drop-out Regulator with CMOS Low Drop-out Regulator with
Excessive Gain ReductionExcessive Gain Reduction
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John Hu and Mohammed IsmailJohn Hu and Mohammed IsmailThe Analog VLSI LaboratoryThe Analog VLSI LaboratoryThe Ohio State UniversityThe Ohio State University
Presented at ICECS 2010Presented at ICECS 2010December 15, 2010December 15, 2010
Outline Outline
Introduction Issue: Capacitor-Free Low Drop-Out (LDO) Problem: True-Zero Load Stability
Approach Method: Excessive Gain Reduction Schematic Design
Results Simulations Measurements
Conclusion
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Capacitor-Free LDO RegulatorCapacitor-Free LDO Regulator
External capacitor-free low drop-out (LDO) regulators are popular because of the benefit in space and cost
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iPhone 3G, 2009. iPhone 4, 2010.
True Zero-Load StabilityTrue Zero-Load Stability
Conventional Miller-based pole splitting topologies suffer from zero-load oscillation
There is a short-cut solution:requiring a minimum Iout
Drawbacks Standby efficiency degradation
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Proposed MethodProposed Method
Observation: not all DC gain contributes to Miller Effect
Excessive Gain (G1)Reduction
Given the same totalDC gain, morecan be distributedto G2 and G3 toenhance the Miller effect
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Schematic DesignSchematic Design
Conventional: G1: opamp G2: positive
gain stage G3: MPT
Proposed: G1’ G2’: positive
gain stage G3’: MPT
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Simulations: Bode PlotSimulations: Bode Plot
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Simulations: Load TransientSimulations: Load Transient
Load Regulation: (conventional vs. proposed) Both are stable when power is unlimited Only the proposed is stable during true zero-load (sleep mode)
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Conclusion from SimulationsConclusion from Simulations
Power Efficiency Improvement When true zero-load stability (TZLS) is required (sleep mode),
the proposed method reduces the battery current by 67.5% [2]
Area efficiency Conventional: 23 pF to achieve true zero-load stability [3] Proposed: 4.5 pF [4]
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Chip FabricationChip Fabrication
A dual-core LDO was fabricated in MOSIS 0.5 um CMOS under the same specs
One conventional, one proposed.
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Test BoardTest Board
PCB with off-chip load test solutions High power rating resistors, NMOS, “stay alive” Ioutmin options:
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Test SetupTest Setup
Test Equipment and Connections
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Measurement ResultsMeasurement Results
Transient load regulation (conventional): Vin=3.7 V, Vout=3.5 V. Stability with “stay alive” current.
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Measurement ResultsMeasurement Results
Transient load regulation: 50% chance of over current (Iout > 1 A, chip heats up.)
Reason: gate of the PMOS pass element floating: top level layout error
Correlation with simulation
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ConclusionConclusion
Conclusions A true zero-load stable CMOS capacitor-free low drop-
out regulator is presented It reduces the excessive gain (G1) and re-distributes
the gain to Miller-enhancing stages (G2, G3) As a result, system power efficiency during standby
can be improved by 67.5%
Future Work Further analysis of the excessive gain reduction technique
and battery life extending IC design methods Lessons learned for future first-time-right silicon
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Selected ReferencesSelected References
1. K. N. Leung and P. Mok, “A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation”, IEEE J. Solid-State Circuits, vol. 38, no. 10, pp. 1691-1702, Oct. 2003
2. S. K. Lau, P. K. T. Mok, and K. N. Leung, “A low-dropout regulator for SoC with Q-reduction”, IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 658-664, Mar. 2007
3. R. Milliken, J. Silva-Martinez, and E. Sanchez-Sincencio, “Full on-chip CMOS low-dropout voltage regulator”, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no.9, pp. 1879-1890, Sep. 2007
4. J. Hu, W. Liu, and M. Ismail, “Sleep-mode ready, area-efficient capacitor-free low-dropout regulator with input current-differencing”, Analog Integrated Circuits and Signal Processing, vol. 63, no.1, pp.107-112, Apr. 2010
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Thank you!Thank you!