JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.6, DECEMBER, 2016 ISSN(Print) 1598-1657 https://doi.org/10.5573/JSTS.2016.16.6.754 ISSN(Online) 2233-4866

Manuscript received Jan. 8, 2016; accepted Sep. 21, 2016 1 Department of Electronics Eng., Kwangwoon University, Seoul, Korea 2 Silicon R&D, Corp., Seongnam-si, Gyeonggi-do, R. O. Korea 3 LIGNEX1 CO, LTD., Yongin-si, Gyeonggi-do, R. O. Korea E-mail : yseo71@kw.ac.kr

A Transformer Feedback CMOS LNA for UWB Application

Ji Yeon Jeon1, Sang Gyun Kim1, Seung Hwan Jung2, In Bok Kim3, and Yun Seong Eo1,2

Abstract—A transformer feedback low-noise amplifier (LNA) is implemented in a standard 0.18 μm CMOS process, which exploits drain-to-gate transformer feedback technique for wideband input matching and operates across entire 3~5 GHz ultra-wideband (UWB). The proposed LNA achieves power gain above 9.5 dB, input return loss less than 15.0 dB, and noise figure below 4.8 dB, while consuming 8.1 mW from a 1.8-V supply. To the authors’ knowledge, drain-to-gate transformer feedback for wideband input matching cascode LNA is the first adopted technique for UWB application. Index Terms—Transformer feedback, wideband input matching, LNA, CMOS, UWB

I. INTRODUCTION

Despite of the slight difference in worldwide, ultra-wideband (UWB) system using the unlicensed frequency band from 3.1 to 10.6 GHz has been drawing attention as a technical solution for the low power and high data-rate wireless communications systems. Especially, 3~5 GHz frequency bands are used for indoor communication and sensor application in Japan, Europe, and Korea.

One of the most critical blocks in the UWB receiver is the low-noise and wideband amplifier since LNA have a great impact on receiver performance such as the

sensitivity. Especially, LNA should provide a low noise figure and gain flatness through the entire UWB frequency band while maintaining wideband input matching. Various UWB LNA topologies for wideband input matching have been reported such as the LC ladder [1], common-gate (CG) amplifier, and resistive shunt feedback [2]. The LC ladder topology incorporating on-chip inductor and capacitor as a matching network shows good performance for wideband matching. However, the adoption of the LC filter at the input stage mandates a number of reactive components, which occupies large chip area and deteriorates noise performance. CG amplifier also has wideband input characteristic due to its intrinsic low input impedance (~1/gm), but usually has poor noise performances and trade-off between the gain and input matching. Another approach for wideband input matching is the resistive shunt feedback LNA, which accompanies with degradation of the noise performance due to feedback resistor and trade-offs between NF and input matching.

Among the various wideband input matching topologies, a reactive (transformer) feedback is one of the applicable candidates in respect of the area efficiency and the moderate NF degradation. Up to now, numerous transformer feedback structures have been published [3-7]. Reactive components should be used inevitably for wideband input and output matching or inter-stage matching [1], while the silicon area increases in comparison with resistive feedback or CG amplifier. Therefore, the feedback topology using reactive component such as an integrated transformer is useful technique to design the wideband LNA. The reactive feedback LNA using integrated transformers also has the virtue of providing DC coupled bias and lower noise

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.6, DECEMBER, 2016 755

contribution. Therefore, the integrated transformer is greatly attractive component due to its area efficiency while providing two or more reactance.

This paper is organized as follows. In section II, the proposed Drain-Gate (D-G) reactive feedback topology is introduced at first. In section III, circuit description is presented in detail with the analytical expressions of its input impedance and transfer function. The experimental results along with the comparison to prior arts are presented in section IV. Finally, the conclusions are followed in section V.

II. PROPOSED D-G REACTIVE FEEDBACK

TOPOLOGY

In previously published literature [3], reactive D-G feedback topology is adopted to neutralize the gate-drain capacitance (Cgd) by Miller multiplication; as a result the stability of amplifier is improved over a wide bandwidth. However, Miller effect is less significant in cascode structure due to unity voltage gain of common source part which for low values of load impedance [9]. Thus, transformer feedback from drain to gate in cascode LNA can be applicable as an alternative way to achieve wideband input matching. Fig. 1 shows the proposed D-G transformer feedback LNA. The secondary inductance L2 of the transformer senses the output current and a fraction is fed back to the input of LNA through the primary inductance L1. Hence, the input impedance of LNA is set close to 50-Ω over a wideband via the transformer feedback.

From the small signal model for D-G feedback LNA, input admittance and voltage gain can be derived as follows.

21

22

1

( )1 (1 )

om

in go

g kgn n sL

Y s sCg sL k

æ öæ ö æ ö+ × + ç ÷ç ÷ç ÷ è øè ø è ø= ++ × -

(1)

( )'

2 ' 22 2'

2

/( ) , (1 )

1mo

in o

g sL k nVs L L k

V sL g× +

= - = × -+ ×

(2)

where gm is the device transconductance, go is the output conductance, and Cg is the input capacitance of the LNA. Also, the transformer coefficients can be design parameters such as coupling factor (k), turn ratio

(n2=L1/L2), and mutual inductance (M=k√L1L2) of the transformer. In Eq. (1), if the second term of denominator is carefully selected to be less than one, the real term of Yin(s) can be expressed as follows,

2Re oin m

g kY gn n

æ ö= + ×ç ÷è ø

(3)

Since the input impedance is a function of transformer

parameters, applying reactive feedback to match the amplifier input stage with 50-Ω is feasible. One drawback of this topology is that the trade-off exists between a high voltage gain and input 50-Ω matching with respect to the turn-ratio [8].

To overcome this limitation, the cascode structure has been adopted, and the lower input admittance (~20 mS) can be achieved while gm is high enough to have proper voltage gain of the LNA through selecting the turn-ratio and coupling factor carefully (e.g. gm is 40 mS~50 mS, k/n is 0.5).

III. CIRCUIT DESCRIPTION

1. D-G Feedback LNA The schematic of the proposed UWB LNA consists of

two stage amplifier, including source follower buffer for measurement purpose, as shown in Fig. 2. The main stage is the common-source (CS) amplifier with reactive feedback using on-chip transformer. As a cascode structure, CG transistor (M2) was inserted to obtain a high gain and good reverse isolation at the same time.

1 2M k L L= ×

Fig. 1. Transformer based drain-gate feedback topology.

756 JI YEON JEON et al : A TRANSFORMER FEEDBACK CMOS LNA FOR UWB APPLICATION

For the DC blocking purpose, Cb and Cc are added at the input/output of LNA. Although feedforward effects are minor due to relatively lower current at the input stage in comparison to the output, the feedback resistor Rf, which is located between the input and the self-inductance L1, acts as a feedforward controller by adjusting a signal current at the feedback path of LNA.

Knowing from Eqs. (1, 3), 20-mS input admittance can be achieved in the range of the resonant frequency (1/√L1Cg). For the low-band UWB (3~5 GHz) input matching, the series inductor Lg is added to cancel out the imaginary part. Without Lg for simplification, the calculated input impedance of LNA can be described as Eq. (4) including the effects of the feedback and Rf.

1

1 1

2

( ) / /1

1 ( ) ( )

fin g

m

o o d

sL RZ s sC

g sL kg sC R sL n

+=

× æ ö+ ×ç ÷+ + × + è ø (4)

'1 2 2

11

1 '2 2

1 1

( )( )

1 ( ) ( )

fm d d

d

f fgo o d d

R kg sL R R sLsL nV

sR RV

g sC sL R R sLsL sL

é ù- × + + × + +ê ú

ë û=é ù

+ + + × + + × +ê úë û

(5) Eq. (5) is also depicted as a transfer function taking the

feedforward effects into consideration. The first step in this design, the input transistor is carefully sized as a compromise between gain (gm with a current bias) and input impedance matching. Once the transistor aspect ratio (W/L) has been selected, the device transconduc- tance is fixed for a given choice of bias current (in this

case 4.5 mA). From Eq. (4), the second term in numerator determines a real term of the input impedance. Also, in order to obtain a broadband response, the shunt peaking load is employed using a resistor Rd and self-inductance L2 which is a part of on-chip transformer. The effective bandwidth can be extended by optimizing the self-inductance L2. After carefully choosing the transconductance of input transistor and the self-inductance L2, the turn-ratio of the transformer attaining the input matching to 50-Ω is determined from the feedback factor (k/n) in Eq. (4).

The simulated input matching S11 with a series inductor Lg is shown in Fig. 3(a). To achieve the input matching of the entire low-band UWB, a complex zero is placed around 4.0 GHz through the considerate selection of the design variables, such as transformer parameters and Lg. By optimizing the feedback factor (k/n) and gm1, the calculated real-term of the input impedance can be close to 50-Ω from 2.5 GHz to 6.8 GHz as shown in Fig. 3(b). Thus, the proposed D-G reactive feedback paves the way for broadband input matching using on-chip transformer.

2. Transformer Design for Reactive Feedback

In the design of the wideband transformer feedback

LNA, the parameters of active transistor and parasitic components in the transformer determine the input reflection coefficient. Also, the circuit layout plays a critical role in the design of wideband circuit.

Thus, the layout of transformer should be co-designed with that of active transistors for both miniaturizing the geometry and minimizing the effects of layout parasitic. The layout of the D-G Transformer is shown in Fig. 4. Especially, since the self-inductance (L2) acts as a shunt peaking load to obtain a broadband response, the

Lg CbM1

M2

VDD

Rf

Rd

L2L1Vb

MSF

Rb

Cc

Ibvin

vo

Vg1

Vd1

Fig. 2. The schematic of the proposed UWB LNA employing reactive feedback using on-chip transformer.

0.0 2.0G 4.0G 6.0G 8.0G 10.0G-200

-100

0

100

200

Z in[o

hm]

Frequency [Hz]0.0 2.0G 4.0G 6.0G 8.0G 10.0G

-40

-30

-20

-10

0

S 11 [d

B]

Frequency [Hz]

Fig. 3. Simulated input response using Eq. (4) with L1=4 nH, L2=5 nH, k=0.7, gm=40 mS, Cg=140 fF, Lg=2.5 nH, Rf=500 Ω (a) Zin, (solid line-ReZin, dashed line-ImZin), (b) S11 in dB.

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.6, DECEMBER, 2016 757

significant transformer parameters such as self-inductance, turn ratio, and coupling factor should be accurately extracted and modeled through the reliable electro-magnetic (EM) tools to achieve the desired performance.

Ultimately, the transformer geometry and parameters are optimized to obtain the wideband 50-Ω input matching. From the iterative EM simulation and optimization, the inner diameters of self-inductor L1 and L2 are designed to be 20 μm and 30 μm, respectively, which lead to the total area of 330 x 330 μm2. Also, the metal width and spacing are 4 μm and 6 μm to have the wanted inductances and Q-factor, respectively. EM simulation reveals that the optimized values of self-inductances are L1 = 3.9 nH and L2 = 4.8 nH at 4.0 GHz, and the obtained mutual inductance is 1.76 nH with the coupling factor of 0.72. And both of the self-inductors have same Q-factor of 6 at 4.0 GHz as shown in Fig. 5, respectively. Therefore, the real term of the proposed transformer feedback LNA is using the feedback factor (k/n = 0.8).

IV. MEASUREMENT RESULTS

The proposed D-G transformer feedback LNA is implemented in a 0.18-μm CMOS technology. Fig. 6 shows the chip microphotograph and chip core area without pads is 850 x 550 μm2. S-parameters of the proposed D-G transformer feedback LNA were measured by utilizing RF on-chip probing with Agilent E8363C two-port network analyzer. As shown in Fig. 7, the measured input reflection coefficient is below -10 dB from 2.5 GHz to 6.8 GHz and the power gain is more than 9.5 dB in the lower UWB band. The 3-dB bandwidth up to 5.5 GHz can cover the entire lower UWB band. Also, the measured noise figure as shown in Fig. 8 is less than 4.8 dB in the target UWB band. The measured input referred IP3 is higher than -13.0 dBm and the 1-dB compression power is -20.0 dBm in the frequency range of 3~5 GHz. DC measurement reveals the power consumption of 8.1 mW excluding source-follower buffer from a 1.8-V power supply. Circuit performances of the proposed D-G transformer feedback

Fig. 4. Layout of the D-G Transformer.

0.0 2.0G 4.0G 6.0G 8.0G 10.0G0

2

4

6

8

10

Q2

Q1

K-factor

L1

Frequency[Hz]

L 1, L 2 [

nH]

L2

0

2

4

6

8

Q-fa

ctor

, K-fa

ctor

Fig. 5. EM simulation results of the transformer.

Fig. 6. Fabricated chip microphotograph.

0.0 2.0G 4.0G 6.0G 8.0G 10.0G-30

-20

-10

0

10

20

Spa

ram

eter [d

B]

Frequency [GHz]

S11

S21

Fig. 7. Measured (solid-line) and simulated (dashed-line) S-parameters of the proposed LNA.

758 JI YEON JEON et al : A TRANSFORMER FEEDBACK CMOS LNA FOR UWB APPLICATION

LNA and the performance comparison of the previously designed 3~5 GHz UWB LNA are summarized in Table 1.

V. CONCLUSIONS

The proposed D-G transformer feedback LNA has been realized in a 0.18-μm CMOS process. To achieve a wideband input matching, a reactive feedback from drain to gate in the cascade LNA is adopted using on-chip transformer. Also, on-chip transformer and its layout are judiciously designed to obtain the wide-band input matching and the proper gain of LNA, simultaneously. The proposed D-G transformer feedback LNA achieves the power gain more than 9.5 dB and noise figure less than 4.8 dB, while maintaining input impedance matching from 2.5 to 6.8 GHz.

ACKNOWLEDGMENTS

This work has been supported by LIGNEX1 and also by the Technology Innovation Program (10053023, The Development of RF MEMS Devices Core Technology for Multi-band IoT System Applications) funded by the Ministry of Trade, Industry & Energy (MI, Korea).

REFERENCES

[1] A. Bevilacqua, et Al., “A Fully Integrated CMOS LNA for 3-5GHz Ultrawideband Wireless Receivers,” IEEE Microwave and Wireless Components Letters, vol. 16, no. 3, pp. 134-136, Mar. 2006.

[2] C.-W. Kim et al., “An Ultra-Wideband CMOS Low Noise Amplifier for 3-5GHz UWB system,” IEEE J. of Solid-State Circuits, vol. 40, no. 2, pp. 554-547, Feb 2005.

[3] Van der Heijden et al., “On the design of unilateral dual-loop feedback low-noise amplifiers with simultaneous noise, impedance, and IIP3 match,” IEEE J. of Solid-State Circuits, vol. 39, no. 10, pp. 1727-1736, Oct 2004.

[4] Antonio Liscidini et al., “Common Gate Transformer Feedback LNA in a High IIP3 Current Mode RF CMOS Front-End,” IEEE CICC, pp. 25-28, Sept 2006.

[5] Michael T. Reiha et al., “A 1.2 V Reactive-Feedback 3.1-10.6 GHz Low-Noise Amplifier in 0.13μm CMOS,” IEEE J. of Solid-State Circuits, vol. 42, no. 5, pp. 1023-1033, May 2004.

[6] Dong Hun Shin et al., “A Low-Power, 3-5-GHz CMOS UWB LNA Using Transformer Matching Technique,” IEEE ASSCC, pp. 95-98, Nov 2007.

[7] Venumadhav Bhagavatula et al., “Analysis and Design of a Transformer-Feedback-Based Wideband Receiver,” IEEE J. of Solid-State Circuits, vol. 61, no. 3, pp. 1347-1358, Mar 2013.

[8] Venumadhav Bhagavatula et al., “Transformer Feedback based CMOS Amplifier,” IEEE ISCAS, pp. 237-240, May 2012.

[9] B. Razavi, Design of Analog CMOS Integrated Circuits. New York McGraw-Hill, 2001.

Table 1. Performance summary and Comparison of Previous Low-band UWB Application

References S11 [dB]

Gain [dB]

NF [dB]

IIP3 [dBm]

PDC [mW]

Area** [mm2] Technology

[1] < -10.0 6.4~9.5 3.5~5.5 -0.8 16.5*@1.2V ~1.08 0.13 μm [2] < -9.0 9.8 2.3 -7.0 12.6*@1.8V ~0.63 0.18 μm

[5] < -11.0 15.1±1.4 2.5±0.34 -8.2~-5.1 9.0 @1.2V ~0.87 0.13 μm This work < -15.0 9.5~11.5 4.2~4.5 -13.0. 8.1*@1.8V ~0.47 0.18 μm

*Excluding output buffer, ** Including I/O pad

1 2 3 4 5 62

4

6

8

NF

[dB]

Frequency [Hz]

Measurement Sch. + Parasitic Extraction

Fig. 8. Measured and simulated noise figure.

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Ji Yeon Jeon received B.S., and M.S. degrees in electronics engineering from Kwangwoon University, Seoul, Korea, in 2014, and 2016. Since 2016, she has been working for Hanwha Thales, Korea. Her research interests are RF/Analog integrated

circuit and systems design in CMOS technology.

Sang Gyun Kim received B.S., and M.S. degrees in electronics engineering from Kwangwoon University, Seoul, Korea, in 2012, and 2014. Since 2014, he has been working toward the Ph. D. degree at the same university. His research

interests are RF/Analog integrated circuit and systems design in CMOS technology.

Seung Hwan Jung received the Ph.D. degrees in Electronic and Electrical Engineering from Kwang- woon University, Seoul, Korea, in 2011. Since 2009, he has been working for Silicon R&D, Korea, where he has involved in the

development of mobile TV RF front-end, GPS and UWB/FMCW radar. His research interests include CMOS RF/analog IC design for wired and wireless communication, UWB/FMCW radar transceivers.

In Bok Kim received the Ph.D. degrees in Electronic Engineering from Kyungpook National University, Daegu, Korea, in 2015. Since 2015, he has working for LIGNEX1 CO, LTD, where he has involved in development of RF Fuse sensor and

RF/MW radar system. His research interests are RF/MW system, Ultra-wideband component and radar system.

Yun Seong Eo received the B.S., M.S., and Ph.D.degrees from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1993, 1995, and 2001, respectively. From 2000, he was with LG Electronics Institute of Technology,

Seoul, Korea, where he was involved in designing the RFICs such as VCO, LNA, and PA using InGaP HBT devices. In September 2002, he joined Samsung Advanced Institute of Technology at Yongin, Korea, where he had worked on developing the 5 GHz CMOS PA and RF transceivers for 802.11n, 900 MHz RFID, and 2.4 GHz ZigBee applications. Since September 2005, he joined the Kwangwoon University, Seoul, Korea, where he is currently a Professor in the Electronics Engineering Department. Since 2009, he also founded a Silicon R&D inc. as the CEO, where he has developed a CMOS UWB and FMCW radar ICs. His current interest includes the UWB and FMCW radar ICs, and the various RF transceiver ICs.