a study on interfacial properties of la o gate dielectrics with thickness scaling · 2012-05-10 ·...
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Doctorial Thesis
A Study on Interfacial Properties of La2O3 Gate Dielectrics with Thickness
Scaling
A Dissertation Submitted to the Department of
Electronics and Applied Physics
Interdisciplinary Graduate School of Science and Engineering
Tokyo Institute of Technology
Maimaitirexiati Maimaiti
08D53430
February 08, 2012
Supervisor: Professor Hiroshi Iwai
Co-supervisor: Professor Parhat Ahmet
i
Abstract
Aggressive scaling of Si-based metal-oxide-semiconductor field-effect-transistors
(MOSFETs) has led to the replacement of gate oxide from SiO2 to high dielectric
constant (high-k) material in order to enable continuous down-scaling. Poor interface
between high-k material and Si-substrate results in degradation of the device
performance. Also achieving a direct high-k/Si-sub contact has been a major issue in the
device research field as the EOT of the high-k gate insulator becomes small. In this
thesis, we have investigated the interfacial properties and scaling potential of gate stacks
with La2O3 as the gate oxide insulator. Direct contact between La2O3 and Si substrate is
capable forming La-rich silicate interfacial layer with high dielectric constant and good
electrical properties. In order to achieve such a desirable La-rich silicate, in-situ
high-temperature annealing was conducted to control the silicate composition. Electrical
characterizations such as capacitance-voltage and conductance method were employed
to evaluate the La2O3/ La-silicate/Si interfaces. Also process guidelines were developed
to minimize the defect sites within the La2O3 gate insulator after heat treatment. Remote
Coulomb Scattering (RCS) plays an important role on the effective mobility degradation
of La2O3 gate MOSFETs with small EOT. The location of the charges which cause
Remote Coulomb Scattering (RCS) of the MOSFET channel carriers was analyzed.
ii
Table of Contents
Contents
Contents ii
List of symbols v
List of acronyms vii
List of tables viii
List of figures ix
Chapter 1 Introduction
1.1 Brief history of semiconductor devices 1
1.2 MOS device scaling 4
1.3 High-k gate dielectric materials 6
1.4 Lanthanum oxide (La2O3) gate dielectrics 12
1.5 Objective of this study 15
Reference 19
Chapter 2 Fabrication and Characterization Methods
2.1 Fabrication of MOS capacitors and MOSFETs 26
2.2 Physical characterizations of gate dielectrics 35
2.3 Electrical characterizations of MOS devices 46
2.4 Summary 54
Reference 55
iii
Chapter 3 Interfacial Silicate Layer Formation
3.1 Introduction 59
3.2 Kinetics of silicate reaction 60
3.3 FTIR absorption spectroscopy of silicate layers 63
3.4 Characterization of La-silicates 66
3.5 Advantage of La2O3 gate dielectrics over CeOx 70
3.6 Summary 78
References 79
Chapter 4 Evaluation of Interface and Oxide Trap States in La2O3/La-silicate Capacitors
4.1 Introduction 84
4.2 Conductance spectra of La2O3 MOS capacitance 85
4.3 A proposed method for La2O3/Si trap states characterization 88
4.4 Effect of annealing temperature on trap states in L2O3 gate stacks 92
4.5 Summary 95
Reference 96
Chapter 5 Interfacial Properties and Effect of Annealing
5.1 Introduction 98
5.2 The effect of air exposure 100
5.3 In-situ post metallization annealing 101
5.4 Annealing temperature effects on interfacial property 102
5.5 Summary 103
References 105
Chapter 6 Impact of Metal Gate on Interfacial Properties
6.1 Introduction 107
iv
6.2 Effect of metal gate material on interfacial property 109
6.3 Effect of metal gate thickness on interfacial property 114
6.4 Summary 117
Reference 118
Chapter 7 Effective Mobility Analyses Based on Remote Coulomb Scattering Model
7.1 Introduction 121
7.2 Remote charge scattering model 122
7.3 RCS induced mobility degradation mechanism 125
7.4 Suggestion to improve the mobility 134
Reference 135
Chapter 8 Summary
8.1 Summaries of this thesis 141
8.2 Recommendation for further works 144
Publications and Presentations 146
Acknowledgement 151
Appendix
A. MATLAB code for RCS-limited electron mobility calculation
154
v
List of Symbols
Symbol Unit Description
dC [F/cm2] Depletion layer capacitance mC [F/cm2] Measurement capacitance oxC [F/cm2] Oxide capacitance gbC [F/cm2] Gate-body capacitance gcC [F/cm2] Gate-channel capacitance pC [F/cm2] Equivalent parallel capacitance
silicateC [F/cm2] La-silicate capacitance itD [cm-2/eV] Interface trap density
slowD [cm-2/eV] Slow trap density aE [eV] Activation energy FE [eV] Fermi-level energy iE [eV] Intrinsic energy level
E [eV] Electron energy cE [eV] Conduction band energy level vE [eV] Valance band energy level
effE [MV/cm] Effective field o [F/cm] Vacuum dielectric permittivity Si [F/cm] Dielectric permittivity of Silicon
2SiO [F/cm] Dielectric permittivity of SiO2
32OLa [F/cm] Dielectric permittivity of La2O3
silicate [F/cm] Dielectric permittivity of La-silicate ()f Fermi-Dirac distribution function f [Hz] Frequency [Hz] Angular frequency
pG [S] Parallel conductance mG [S] Measurement conductance tG [S] Tunneling conductance
L [m] Channel length W [m] Channel width
dI [A] Drain current gJ [A/cm2] Leakage current density dV [V] Drain voltage gV [V] Gate voltage
FBV [V] Flat band voltage thV [V] Subthreshold voltage FBV [V] Flat band voltage shift inQ [C/cm2] Inversion layer electronic charge density dg [S] Channel conductance SS. Subthreshold slop
vi
itR [] Resistance related to interface traps n Refractive index of dielectrics
s [V] Surface potential s [V] Average surface potential
Standard deviation of surface potential in [cm-2] Charge density at the interface
)(ro Ionic conductivity o Pre-factor for capture cross section it [cm2] Capture cross section for interface traps
slow [cm2] Capture cross section for slow traps [cm-3] Charge density in the oxide
SN [cm-2] Inversion charge density RCCN [cm-3] RCC density [nm] Attenuation wave function coefficient q [C] Electronic charge
0m [kg] Electron rest mass tm [kg] Transverse effective mass of electrons lm [kg] Longitudinal effective mass of electrons
h [J/s] Planck constant [J/s] Reduced Planck constant k [m-1] Wave vector
Bk [J/k] Boltzmann’s constant Fk [m-1] Fermi wave number it [s] Time constant for interface traps
slow [s] Time constant for slow traps RCS [s] Scattering time for RCS [V] Scattering potential
qA [V-1] Fourier-Bessel transform of
R [cm2/Vs] Pre-factor for mobility eff [cm2/Vs] Effective mobility add [cm2/Vs] Additional scattering mobility RCS [cm2/Vs] RCS-limited mobility t [oC] Celsius temperature T [K] Absolute temperature
Tox [nm] Oxide thickness Tsilicate [nm] La-silicate thickness TPhys [nm] Physical thickness of gate oxide Al Aluminum Si Silicon
SiO2 Silicon oxide La2O3 Lanthanum oxide
W Tungsten TaN Tantalum nitride
vii
List of Acronyms
Acronyms Description ITRS International technology roadmap for semiconductors MOS Metal-oxide-semiconductor
MOSFET Metal-oxide-semiconductor field-effect transistor LSI Large-scaled-integrated circuit
VLSI Very- large-scaled-integrated circuit ULSI Ultra-large-scaled-integrated circuit EOT Equivalent oxide thickness
E-beam Electron-beam High-k High dielectric permittivity materials
F.G Forming gas IL Interfacial layer
PMA Post-metallization annealing RTA Rapid thermal annealing RIE Reactive-ion etching RF Radio-frequency
DIW Diluted-ion water UHV Ultra-high vacuum FT Fourier transform
FTIR Fourier transform of infrared spectroscopy LO Longitudinal optical phone mode TO Transverse optical phonon mode
TEM Tunneling electron microscope XPS X-ray photoelectron microscopy XRD X-ray diffraction
GI-XRD Grazing incident X-ray diffraction BE Binding energy CB Conduction band VB Valance band
IMFP Inelastic mean free path RCC Remote Coulomb charge RCS Remote Coulomb scattering RSR Remote surface roughness RPS Remote phonon scattering
viii
List of Tables
Table 1.1 Scaling rules for constant-field scaling 5
Table 1.2 Parameters of mostly studied high-k dielectrics and SiO2 7
Table 2.1 Sources and related effects of various contaminations 29
Table 2.2 Etching methods for contaminations in gate stacks 32
Table 2.3 Vacuum pumps and their classification for MOS device
processes
35
Table 2.4 Binding energies for gate dielectric materials studied in this
thesis
43
Table 3.1 Densities and thicknesses of each layer in
SiO2/La2O3/La-silicate/Si sample by XRR method
69
Table 6.1 Estimated net charge concentrations at the interfaces of La2O3
gate stacks
112
ix
List of figures
Chapter 1
Figure 1.1 Size of transistor decreased by x7.0 , and number of transistor in
a microprocessor increased x2 in every two year
3
Figure 1.2 Leakage current variation with EOT thinning 5
Figure 1.3 High-k dielectrics suppress leakage current 7
Figure 1.4 Band gap versus dielectric constants 13
Figure 1.5 After annealing, a La-silicate interfacial layer formed between
La2O3 and Si-substrate
13
Figure 1.6 (a) TEM image and (b) XPS spectra for La2O3 MOS capacitors 14
Figure 1.7 (a) TEM image and (b) XPS analysis of MOS capacitors with
HfO2 gate dielectrics
14
Figure 1.8 Outline of this thesis 16
Chapter 2
Figure 2.1 Fabrication process flow for MOS capacitors 27
Figure 2.2 Fabrication process flow for nMOSFETs 28
x
Figure 2.3 Si wafer cleaning process 29
Figure 2.4 Schematic illustration of E-beam evaporation system 30
Figure 2.5 Schematic illustration of RF sputtering system 31
Figure 2.6 Schematic illustration of RIE system La2O3 and Si-substrate 32
Figure 2.7 Schematic illustration for ULVAC QHC-P610CP RTA system 34
Figure 2.8 Schematic illustration of a vacuum process chamber for
fabrication of MOS devices
34
Figure 2.9 Schematic illustration of ellipsometer 36
Figure 2.10 Schematic illustration of transmission electron microscope 38
Figure 2.11 Schematic illustration of X-ray irradiation on materials 41
Figure 2.12 XPS core-level spectra of O 1s for HfO2 42
Figure 2.13 Schematic illustration for FTIR measurement system 44
Figure 2.14 Equivalent circuits of MOS capacitors: (a) An equivalent circuit
model for MOS capacitor; (b) The measurement circuit, (c) The
simplified circuit of (a)
48
Figure 2.15 Determination of threshold voltage by the linear extrapolation
technique
49
Figure 2.16 Id -Vg characteristics in logarithmic scale for typical MOSFETs 50
xi
Figure 2.17 Id -Vg and dg characteristics for nMOSFETs 51
Figure 2.18 Schematic configurations for (a) gate-to-channel and (b)
gate-to-body capacitances measurements for nMOSFETs
53
Figure 2.19 Characteristics for (a) gate-to-channel and (b) gate-to-body
capacitances for nMOSFET
53
Chapter 3
Figure 3.1 EOT increment with annealing temperature 61
Figure 3.2 Schematic illustration of concentrations of oxygen atoms in gate
oxide
62
Figure 3.3 Arrhenius plot of the formed silicate layer thickness and
annealing temperature
62
Figure 3.4 FTIR absorption spectroscopy of for samples annealed at
temperatures of 200 to 800 oC and also as-deposited for
W/La2O3 structure
64
Figure 3.5 Annealing temperature dependency of absorption peaks in FTIR
spectra
65
Figure 3.6 O 1s spectra for samples of as deposited and annealed at 300 oC
xii
~ 900 oC for SiO2/La2O3/nSi structure 68
Figure 3.7 Reflective X-ray intensity trend versus irradiating angle by
GI-XRD method
68
Figure 3.8 Grazed incident XRD spectra for La2O3 and HfO2 gate stacked
layers after thermal annealing at 500 oC in F.G ambient
69
Figure 3.9 (a) Ce 3d5/2 and (b) Si 1s spectra for 2 and 3-nm thick
Ce-oxide/Si after annealing at 900 oC
71
Figure 3.10 (a) O 1s and (b) VB spectra of Ce-silicates on Si (1 0 0) 72
Figure 3.11 Measured and deconvoluted Ce 3d5/2 spectra obtained from
capacitor structure: (a) before and (b) after annealing
75
Figure 3.12 (a) Si 1s spectra obtained from W/Ce-oxide/Si structure before
and after annealing. The subtracted spectrum is also shown. (b)
TEM cross-sectional images before and after annealing
76
Chapter 4
Figure 4.1 Capacitance versus gate bias for a sample annealed at 600 oC.
The dots correspond to the measured capacitances for the
frequency range from 1 kHz to 1 MHz, and the solid line
xiii
corresponds to the ideal curve of SiO2 85
Figure 4.2 Gp/ω as a function of frequency. The left y-axis is for La2O3 gate
stack capacitor, which is annealed at 600 oC. The solid lines
correspond to the fitting curves by our modified model with the
fitting parameters of 475 10~ ,s10~ ,s10~ itslow . The right
y-axis is for SiO2 capacitor. The conductance data for both
La2O3 and SiO2 sample correspond to the eV 12.0s . All
data are taken by the measured voltage amplitude of 100 mV
86
Figure 4.3 Interface trap time constant ( it ) and slow trap time constant
( slow ) versus electron energy; the closed dots represent it and
the closed triangles represent slow
87
Figure 4.4 The energy distribution of the Dit and Dslow within the band gap
of Si
89
Figure 4.5 Band diagram representing the proposed interpretation of the
location of trap sites for La2O3 gated MOS capacitors
91
Figure 4.6 Dependencies of (a) Dit and Dslow, (b) capture cross-sections, and
(c) VFB on annealing temperature
94
xiv
Chapter 5
Figure 5.1 Schematic diagram of preventing oxygen atoms diffusing into
La2O3 gate dielectrics
99
Figure 5.2 (a) measured capacitance variance with PMA delay time;
(b) EOT variance with PMA delay time
101
Figure 5.3 (a) measured capacitance and (b) extracted EOT for samples
annealed by in-situ and ex-situ approaches respectively
102
Figure 5.4 Measured capacitances for samples with in-situ PMA at (a)
700 oC, (b) 800 oC, and (c) 900 oC, respectively
103
Chapter 6
Figure 6.1 Schematic illustration of controlling of the supplement of
oxygen atoms in the metal gate
109
Figure 6.2 C-V characteristics of (a) TaN/La2O3/Si, (b) W/La2O3/Si, and
(c) TaN/W/La2O3/Si MOS capacitors
110
Figure 6.3 EOT dependence of flat band voltage for (a) TaN, (b) W, and (c)
TaN/W metal gated La2O3 MOS capacitors with PMA in F.G for
xv
30 min at 800 oC 111
Figure 6.4 C-V characteristics for samples with (a) W(60 nm), and (b)
W(8 nm) metal gate electrodes
114
Figure 6.5 W thickness dependence of C-V characteristics for
TaN/W/La2O3/Si MOS capacitors with in-situ PMA in F.G for
30 min at 800 oC
115
Figure 6.6 Flat band voltage as a function of the thickness of W metal gate
in La2O3/Si MOS capacitors with in-situ PMA in F.G for 30 min
at 800 oC
116
Chapter 7
Figure 7.1 Schematic cross-section of La2O3 gate stacked MOSFET 123
Figure 7.2 Calculated RCS-limited electron mobility versus inversion
charge density
125
Figure 7.3 Measured C-V characteristics for the fabricated MOS capacitors
after PMA 800 oC in F.G for 30 min; (a) EOT dependence of
capacitance value; (b) Capacitance dependence on measurement
frequency; in both figures, the solid lines refer to the ideal curve
xvi
and the symbols refer to measurement data 127
Figure 7.4 EOT versus the thickness of the deposited La2O3 film. The
closed symbols correspond to the total EOT extracted from the
C-V measurement; the solid line refers to the fitting curve,
considering the formation of interfacial silicate layer (TLa-silicate)
within La2O3 layer (TLa-oxide)
129
Figure 7.5 The measured electrical characterizations of W/La2O3 gate
stacked MOSFETs annealed at 800 oC in F.G for 30 minutes; (a)
Id -Vd characteristics, and (b) Gate-to-channel (Cgc), and
gate-to-body (Cgb) capacitance characteristics
1291
Figure 7.6 Mobility versus inversion layer charge density; (a) measured
effective electron mobility, and (b) extracted additional
scattering-limited electron mobility for samples with PMA
800 oC in F.G for 30 min; the measured device size is
L/W 10/10 m and measurement frequency is 100 kHz
130
Figure 7.7 Mobility versus the thickness of La2O3 layer. TLa-oxide is extracted
from the total EOT by considering the formation of La-silicate
layer. The closed symbols correspond to the measurement data
xvii
of eff at Eeff = 0.3 MV/cm. The solid line refers to theoretical
modeling
131
Figure 7.8 Conductance spectra for W/La2O3/Si MOS capacitors with PMA
800 oC in F.G for 30 min. The dark and light symbols correspond
to samples with EOT = 0.8 nm and EOT = 1.2 nm, respectively.
The conductance spectra were measured with E-Ei range from
-0.5 to -0.8 eV
133
1
Chapter 1 Introduction
Since the invention of the first bipolar transistor in 1947 [1], and the realization of the
first integrated circuit in 1958 [2], semiconductor device dimensions have continuously
shrunk and their performance has dramatically improved. In this chapter, at first the
history of semiconductor devices is briefly summarized. The major driving force
behind the semiconductor technology, i.e. the Scaling Law, is explained. The necessity
for introduction of high-k dielectrics into MOSFET gate insulator and the related
integration issues are explained. Finally, the objective of this thesis is described.
1.1 Brief History of Semiconductor Devices
In 1906, L. D Forest invented the first vacuum tube which was used for rectifying,
amplifying, and switching electrical signals [3]. Before the advent of the semiconductor
transistor, vacuum tubes had been widely applied to electrical devices, and had played
an important role in the development of electronics. However, even small vacuum tubes
have dimensions of several cubic centimeters and substantially consume a larger
amount of power.
2
In 1925, J.E. Lilienfeld proposed a field-effect-transistor (FET) [4]. In 1947, J.
Brattain and W. Bardeen invented the first point-contact junction transistor [1, 5], and in
1948 W. Shockley proposed bipolar junction transistor (BJT) [6]. These three scientists
received the Nobel Physics Prize in 1956 for their research on semiconductors and their
discovery of the transistor [7]. The term ‘bipolar’ means that the operation involves both
electron and hole carriers. In contrast, the FET is a ‘unipolar’ transistor that involves
only one type of carriers for its operation. In 1951, W. Shockley invented junction
field-effect transistor (JFET) [8]. JFET was a revolutionary replacement of the vacuum
tube by a solid-state device, and it paved the way for smaller and cheaper electronic
devices. In 1958, J. Kilby realized the first integrated circuit and received the Nobel
Physics Prize for his innovation and pioneering work [9]. In 1960, D. Kahng fabricated
metal-oxide-semiconductor field-effect transistors (MOSFETs) on Si-substrate using
SiO2, for the first time [10]. MOSFETs rapidly replaced the JFET and had a profound
effect on microelectronics [11]. However, MOSFETs suffered from large standby power
dissipation due to their single-polarity. In 1963 the complementary
metal-oxide-semiconductor (CMOS) field-effect transistor (FET), which uses both n-
and p-type MOSFETs, brought major breakthrough to the integrated circuits [12]. In
1970, large scale integrated circuits (VLSIs) were realized, and transistor dimensions
3
shrunk to a several micrometers. By the year 2000, transistors were only a several
hundred nanometers in size. As shown in Figure 1.1, the size of transistor in a
microprocessor has shrunk nearly 100, 000 times within 40 years, and as of 2011 an
advanced microprocessor included as many as 3.1 billion transistors [13].
Transistors which are the fundamental building elements of the modern VLSI, are
used in almost every electronic device these days, playing a crucial role in every aspect
of modern human life. The recent advances in information technology (Mini Laptop,
iPhone, the Internet, and satellite etc.) demand an ever higher operational speed, lower
power consumption, smaller size, and lighter weight. Electronics and information
Figure 1.1 Size of transistor decreased by 0.7x, and number of transistor in a
microprocessor increased 2x in every two year [14].
Nu
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4
technology based on VLSI has brought great convenience and comfort to life, and also
has greatly contributed to the development of modern industry [15].
1.2 MOS Device Scaling
The continuous progress of VLSI performance has been made possible by the
downsizing of transistors or “scaling”. The device feature size decreases by
approximately x7.0 in every two or three years and the number of transistors on a
VLSI chip doubled in every two years as shown in Figure 1.1. This trend is called as
“Moore’s Law” which was first stated by Gordon Moore [16]. As shown in table 1.1, by
the scaling rule, when the device dimension is scaled down with factor the supply
voltage of MOSFETs should be reduced by the same factor . The doping concentration
should be increased by the same factor , keeping the electric field in MOSFETs
constant. Moreover, power dissipation per circuit is reduced by . By the scaling
method and Moore’s Law, transistor size has shrunk to obtain higher performance and
low fabrication costs.
As the result of continuous reduction of the SiO2 layer thickness, the physical
thickness of SiO2 has already reached less than 1.2 nm, and the gate leakage current
caused by direct-tunneling exceeds 1A/cm2 at 1 V as shown in Figure 1.2 [17]. Thus,
5
the stand-by power consumption is remarkably increased. In order to suppress the
power consumption caused by leakage current, the conventional dielectric layer of SiO2
is needed to be replaced by new type of materials.
Table 1.1 Scaling rules for constant-field scaling
MOSFET device parameters Multiplicative factor ( >1)
Scaling assumption Device dimension (tox, L, W)
Supply voltage (V) Doping concentration (Na, Nd)
1/ 1/
Behavior of device parameters
Electric field Carrier velocity
Capacitance ( oxtAC / ) Drift current (I)
1 1
1/ 1/
Behavior of circuit parameters
Power density ( )/ AP Power dissipation ( IV ) Circuit density ( A/1 )
Circuit speed
1 1/2
2
Figure 1.2 Leakage current increases as EOT thinning [17].
6
1.3 High-k Gate Dielectric materials
High-k dielectric constant (high-k) materials are widely studied for continuing the
scaling trend of MOSFETs. In this section, an introduction of high-k dielectrics is
explained and their related issues are described. Also, the published results for high-k
gate technology are summarized.
1. Introduction of high-k dielectrics
1) Replacement of SiO2 gate oxide with high-k dielectrics
It is necessary to replace SiO2 by high-k materials in order to supress the gate leakage
current for the further downscaling of MOSFETs. By using the high-k materials, the
gate leakage current is suppressed at smaller EOT values as shown Figure 1.3 [18]. The
relation between EOT and the thickness of the high-k layer is expressed as:
khighkhigh
SiO TEOT
2 , (1.1)
where 2SiO , khigh are the dielectric constants of SiO2 and high-k dielectrics. Thigh-k is
the physical thickness of high-k dielectrics gate oxide.
2) Requirements for high-k gate dielectrics
The guidelines for selecting an alternative gate dielectric material includes a number of
7
Table 1.2 Parameters of mostly used high-k dielectrics and SiO2
Material Dielectric
constant
Band gap
[eV]
Interface trap
density [cm-2/eV]Phase status
SiO2 3.9 8.9 10101 Amorphous
Gd2O3 12 5 13102.1 [19] Crystal (T > 400 oC)
Al2O3 12.5 8.8 11101.4 [20] Amorphous (T < 700 oC) [21]
Y2O3 15 6 12103.1 [22] Crystal (T > 400 oC) [23]
CeO2 20-26 5.5 11102 Crystal (T > 400 oC) [24]
HfO2 22 5.6 11101 [25] Crystal (T > 700 oC)
ZrO2 24 4.7 ~ 5.7 11103 [26] Crystal (T > 400 oC)
Ta2O3 25 4.4 11102 [27] ?
La2O3 27 5.8 11106.1 [28] Amorphous
factors such as a higher dielectric constant value, a large band gap and high band offset
to silicon conduction or valence bands, thermodynamic stability, interface quality,
process compatibility, and reliability. Table 1.2 compares dielectric constant, band gap,
Figure 1.3 High-k dielectrics suppress leakage current [18].
8
and interface state density of SiO2 gate oxide insulator with commonly used high-k
dielectrics.
2. Main problems in the high-k dielectrics
Some semiconductor companies such as Intel have already successfully introduced
high-k dielectric materials in their products. However, the EOT value needs to be
reduced in every new generation of the products, and there are many issues facing
further EOT scaling. To solve these problems, many researchers have been performed in
the world. Some of the notable results are introduced in the following.
1) Interfacial quality
Compared to conventional SiO2 MOSFETs, high-k dielectric gate stacked MOSFETs
have degraded interfacial properties in general. Lai et al. proposed a scheme of “hybrid”
HK/MG integration for high performance 28 nm CMOSFETs. For high quality
interfacial layer (IL) oxide/Si interface, IL oxide was formed with high/medium thermal
process [29]. They achieved a low leakage current density in the device treated with a
high temperature and optimizing HfO2 high-k dielectrics by TiN metal and LaOx
capping layer. They also achieved a 30 % performance improvement and a low
threshold voltage (Vth) of 0.25 V for PFET by gate last process.
2) Flat band voltage suppression and threshold voltage control
9
In the high-k dielectric gate stacked MOSFETs, flat band voltage (VFB) shift and Vth
shift are widely observed compared to conventional SiO2 MOSFETs. Brunet et al.
reported that HfO2 and HfZrO oxide suffer large Vth instabilities up to 230 mV when
transistor channel width is scaled down to 80 nm [30]. Morooka et al. reported that
reduction of Mg/La atoms in bulk high-k dielectric layer and piling Mg/La atoms up
near the high-k dielectrics/IL interface and modulation of La/Mg diffusion from high-k
dielectric layer can suppress the increase in Vth instability. They achieved a Vth reduction
over 400 mV [31]. Meanwhile, Maeng et al. demonstrated interface state density (Dit)
improvement and VFB by capping TiO2 layer over HfO2 gate dielectrics [32].
3) Ultrathin EOT devices
Ando et al. for the first time realized extremely scaled nMOSFETs with high-k/metal
gate (HK/MG) stacks using a gate-first process. [33] They capped the HfO2 layer by La
and Al, followed by TiN as a gate electrode. Finally, they doped some scavenging
elements in TiN. By their remote interfacial layer scavenging technique, they were able
to fabricate a device with EOT of 0.42 nm. Meanwhile, they observed no extrinsic
mobility degradation in the case of La capping over HfO2. By depositing La2O3 on a
thin CeO2, Kakushima et al. realized LaCe-silicate MOSFET with EOT of 0.64 nm and
extremely low gate leakage current of 0.65 A/cm2 [34].
10
4) Leakage current suppression
By employing bottom interfacial SiOx layer modification techniques such as k-boosting
capping, TaN-alloy gate electrode, and effective work function tuning techniques, Choi
et al. successfully demonstrated extremely thin FET devices with EOT of 0.55 nm,
leakage current of 0.6 A/cm2, and Tinv of 0.95 nm [35]. Xiong et al. showed that band
gap, conduction band offset and conduction band minimum are simultaneously
increased by doping Gd in HfO2 gate dielectrics with reduction of oxygen vacancies.
Also the leakage current density was reduced by almost an order of magnitude. They
obtained the EOT of 0.81 nm and leakage current of 0.9 mA/cm2 at 1 V gate
voltage [36].
5) Mobility degradation
It is widely observed that carrier mobility in the channel of inversion mode MOSFETs
with high-k dielectrics is largely degraded compared to the conventional MOSFETs
with SiO2 dielectric. Robertson showed that mobility value is largely reduced (to less
than 110 cm2/Vs) in HfO2 and HfSiO dielectric layer MOSFETs [37]. Therefore, he
suggested that the effect of complete gate stack and its thickness must be considered for
a gate dielectric with a higher dielectric constant than HfO2.
6) Suppress Fermi level pinning
11
Liu and Robertson showed that adding group III elements such as La, Y, Sc and Al can
passivates oxygen vacancies in the HfO2, ZrO2 and suppress Fermi level pinning [38].
They also showed that Effective Work Function (EWF) can be suppressed by adding La
or Al into HfO2 which passivates oxygen vacancies.
7) Thermal stability
Thermal stability is also one of the most important factors that should be considered.
Kwon and Chabal showed that Ta-O bonds in TaN layer of the gate stacks
(TaN/high-k/SiO2/Si) are very sensitive to the annealing temperature during post
deposition annealing (PDA) [39]. Zafari et al. showed that gate stacks with high-k
dielectric layers such as oxide/HfO2 and oxide/Al2O3, are inherently instable due to the
oxygen vacancies which exist in the HfO2 layer. These oxygen vacancies lead to Vth
instability due to the charge trapping, negative bias temperature instability, hot carrier
stressing, de-trapping kinetics and transient charge trapping effects [40].
8) Parasitic gate charge
In ultra-thin high-k dielectric gate stacked MOSFETs, parasitic gate charge is a major
issue. Komaragiri et al. demonstrated that the drain current performance is highly
improved by using a p-type poly gate instead of an n-type poly gate in an
nMOSFET [41].
12
9) Permittivity and barrier height
In high-k dielectrics, permittivity has a trade-off relation with conduction or valance
band barrier height. Thus the permittivity value of the chosen high-k material must be
chosen accordingly to control the gate leakage current density [42].
1.4 Lanthanum Oxide (La2O3) Gate Dielectrics
Various high-k materials have been investigated as gate oxide insulator, including
Gd2O3 [43], CeO2 [44], Y2O3 [45-46], Al2O3 [47], TiO2 [48], ZrO2 [49], HfO2 [50] and
silicates of Hf, Zr, and Y [51-53]. However, there is a tradeoff relationship between
dielectric constant value of a high-k material and its band offset as shown in Figure
1.4 [16]. La2O3 is considered as one of the most promising candidate for high-k
dielectrics for the following reasons:
1) Lanthanum oxide (La2O3), has a wide band gap (Eg = 5.6 eV) and a relatively high
dielectric constant ( 4.2332OLa ) (Figure 1.4).
2) La2O3 can form a direct contact with Si-substrate without formation of SiO2 layer at
the Si-substrate interface [55]. A silicate layer at the La2O3/Si-substrate interface is
formed after annealing as shown in Figure 1.5. Both TEM image and XPS spectra
confirm the formation of a La-silicate Interfacial Layer (IL) with a high dielectric
13
constant (8~14), as shown in Figure 1.6. This is in contrast with HfO2-based oxides
which promote the formation of a SiOx IL (Figure 1.7). Recent theoretical studies have
explained the physical nature of La-silicate formation in La2O3 and SiO2 formation in
HfO2 [56].
Figure 1.5 After annealing a La-silicate interfacial layer formed
between La2O3 and Si-substrate.
Si
La2O3
W
Si
La2O3
W
Before annealing
Si
La2O3
W
La-silicate
After annealing
Si
La2O3
W
La-silicate
After annealing
Figure 1.4 Band gap versus dielectric constants [54].
La2O3
14
However, like most of the high-k materials, the La2O3 exhibit higher surface states, Dit ~
1011~12 cm-2eV [28], and large flatband voltage shift due to high fixed charge density in
the dielectric layer [18], depending on the process condition. These high surface states
and fixed charges lead to degradation of the device performance. Therefore, interfacial
Figure 1.7 (a) TEM image and (b) XPS analysis of MOS capacitors with HfO2 gate
dielectrics [57].
(a) (b)
SiOx-IL
HfO2
W
1 nm
k=4
k=16
500 oC 30min
1837184018431846
Binding energy (eV)
Inte
nsi
ty (
a.u
)
Si sub.
Hf SilicateSiO2
500 oC
1837184018431846
Binding energy (eV)
Inte
nsi
ty (
a.u
)
Si sub.
Hf SilicateSiO2
500 oC
XPS Si1s spectrum
Figure 1.6 (a) TEM image and (b) XPS spectra of La2O3 MOS capacitors [57].
La2O3
La-silicate
W
500 oC, 30 min
1 nm
k=8~14
k=23
1837184018431846
Binding energy (eV)
Inte
nsi
ty (
a.u
)
as depo.
300 oC
La-silicate
Si sub.
500 oC
1837184018431846
Binding energy (eV)
Inte
nsi
ty (
a.u
)
as depo.
300 oC
La-silicate
Si sub.
500 oC
XPS Si1s spectra(a) (b)
15
property improvement is one of the important issues for the development of La2O3 gate
MOSFETs with small EOT.
1.5 Objective of This Study
The purpose of this thesis is to study the interfacial properties of La2O3 gate dielectrics
and provide guidelines for improving their performance. Mobility degradation
mechanism, including Remote Coulomb Scattering effects, in thin-EOT MOSFETs with
La2O3 gate dielectrics is studied.
Figure 1.8 shows the outline of this thesis. The following are the brief descriptions of
each chapter:
In Chapter 1, a brief history of transistors is given and the scaling law for the
MOSFETs is summarized. Then, the problem of the conventional SiO2 gate insulator
thinning is explained and the necessity of the introduction of high-k gate dielectrics as
the solution is described. After the review of the recent high-k gate insulator research,
purpose of the thesis research is described.
In Chapter 2, the fabrication processes of MOS capacitors and MOSFETs with high-k
gate insulator are explained. Then, methods for the physical and electrical
characterization of the above MOS samples are described.
16
In Chapter 3, the results of the study on the formation mechanism of La-silicate
interfacial layer (IL) at the La2O3/Si interface are described. From the analyses using
TEM and XPS techniques, the formation of the La-silicate IL with high dielectric
constant value (8 ~ 14) was confirmed. EOT increment by increasing the annealing
temperature was evaluated. The results of Fourier Transform Infrared (FTIR)
spectroscopy indicate that high temperature annealing above 600 oC is necessary for
Figure 1.8 Outline of this thesis.
Chapter 1 Introduction
Chapter 2 Fabrication and characterization method
Chapter 3 Interfacial silicate layer formation
Chapter 4 Evaluation of interface and oxide trap states in La2O3/La-silicate capacitors
Chapter 5 Interfacial properties and effect of annealing
Chapter 8 Summary
Chapter 7 Effective mobility analyses based on remote Coulomb scattering model
Chapter 6 Impact of metal gate on interfacial properties
Chapter 1 Introduction
Chapter 2 Fabrication and characterization method
Chapter 3 Interfacial silicate layer formation
Chapter 4 Evaluation of interface and oxide trap states in La2O3/La-silicate capacitors
Chapter 5 Interfacial properties and effect of annealing
Chapter 8 Summary
Chapter 7 Effective mobility analyses based on remote Coulomb scattering model
Chapter 6 Impact of metal gate on interfacial properties
17
relaxing the stretch of the SiO4 tetrahedral network in the La-silicate layer so as to
improve the interfacial properties.
In Chapter 4, the results of the investigation on the electrical characteristics of MOS
devices with La2O3 gate dielectrics are given. A novel interpretation of the conductance
spectra was developed in order to analyze the location of the trapping sites. Two distinct
peaks in the conductance spectra revealed that a large number of slow trap states exists
within the gate insulator. It was found that Post Metallization Annealing (PMA) in the
forming gas ambient is not effective for reducing this type of the number of the slow
traps which are mainly located at the La2O3/La-silicate interface.
In Chapter 5, the results of the study on the effect of PMA on the interfacial properties
of the La2O3/La-silicate MOS capacitor are shown. Samples treated with in-situ
annealing result in smaller EOT in comparison with the samples treated with ex-situ
annealing. The results indicate that in-situ annealing is preferable for reducing the EOT
of La2O3 gate stack MOS capacitors.
In Chapter 6, the results of the study on the effect of the choice of gate-electrode metal
material as well as that of the metal thickness on the interfacial silicate layer formation
and the interfacial property are described. According to the experiments, W gate
electrode devices showed better interfacial properties compared with those of TaN.
18
Moreover, it was found that increasing the W physical thickness is effective for
lowering the interfacial state density. Controlling the amount of oxygen supplied from
the gate electrode metal during the thermal process is considered the key for obtaining
the good quality of the gate oxide and its interface.
In Chapter 7, the results of the investigation on the effect of RCS on the electron
mobility are described. It was confirmed that RCS by charges located near the metal
gate/high-k interface cause mobility degradation in La2O3 gate stacked MOSFETs with
small EOT. It was shown that suppressing the diffusion of gate metal atoms into the
gate oxide high-k insulator is effective for suppressing RCS.
Finally, in Chapter 8, summary and conclusions of the thesis research are given.
19
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26
Chapter 2 Fabrication and Characterization Methods
In this chapter, sample fabrication and characterization methods for MOS capacitors and
nMOSFETs used in this study are described.
2.1 Fabrications of MOS Capacitors and MOSFETs
The process fabrication of MOS capacitors and MOSFETs involves the steps of surface
cleaning of Si-substrate, oxide layer deposition, gate electrode deposition, thermal
annealing, patterning and contacting of electrodes.
1) Fabrication process for MOS capacitors
Two types of Si wafers were used in our experiments. 1: Commercially available wafer
with a 400 nm thick thermally grown SiO2 layer on both sides (front and back) of the
Si (1 0 0) substrate. 2: plane Si (1 0 0) wafer.
In Figure 2.1, fabrication process flow for MOS capacitors is shown.
SiO2 (400 nm)/Si-sub with doping concentration of 315 103 cm were first degreased
by acetone and ethanol. Substrates were then patterned by photo lithography for gate
electrodes and the SiO2 layer of the gate area was etched away. Standard SPM and
27
Gate pre-patterning
Surface pre-cleaning
Figure 2.1 Fabrication process flow
for MOS capacitors.
Back electrode contact
Surface cleaning
Oxide layer deposition
Gate electrode sputter
Gate patterning
Gate area forming
Thermal annealing
SiO2 wet etching
n-type Si (1 0 0) wafer
diluted-HF (1%) cleaning was performed on gate areas. Substrates were loaded to an
ultra-high vacuum chamber equipped with electron-beam (E-beam) guns. High-k thin
films were deposited on the Si-substrate using E-beam evaporation at controlled rate
and pressure. Metal gate electrodes were
formed by Radio Frequency (RF) sputtering
system. Metal gate electrodes were patterned
by photo lithography and the gate area was
formed by reactive ion etching (RIE). This
was followed by heat treating devices in a
Rapid Thermal Annealing (RTA) unit.
Finally, Al metal was deposited by thermal
evaporating to form back contact. The
experimental conditions and parameters for
these fabrication processes will be described
in detail in the following sections.
2) Fabrication process for MOSFETs
Figure 2.2 shows the fabrication flow of nMOSFETs. First, p-type Si (1 0 0) substrates
with pre-formed source and drain were cleaned by SPM, and diluted-HF treatment. The
28
substrate doping concentration is 3 1016 cm-3. High-k layer and metal gate electrode
were deposited by E-beam evaporation system and RF sputtering system, respectively.
Metal gate area was patterned by RIE. Thermal annealing was conducted in a RTA
system. Next, high-k and 400 nm thick SiO2 layers which cover the source/drain were
removed by RIE and wet etching. Al contacts for source/drain as well as backside
contact were deposited by thermal evaporation.
3) Surface cleaning of substrates
Surface cleaning of substrates is an important step in MOS device fabrication process.
The sources and the related effects on device performance of the Si-substrate
contaminations are shown in table 2.1.
Figure 2.2 Fabrication process flow for nMOSFETs.
p-type Si substrate
SPM, HF last treatment
Deposition of high-k(La2O3)
Metal gate deposition ( W by RF sputtering)
Back side Al contact
PMA (500℃, 30min)F.G. (N2:H2=97%:3%)
Gate patterning
S/D holing and Al wiring
p-type Si substrate
SPM, HF last treatment SPM, HF last treatment
Deposition of high-k(La2O3)Deposition of high-k(La2O3)
Metal gate deposition ( W by RF sputtering) Metal gate deposition ( W by RF sputtering)
Back side Al contact Back side Al contact
PMA (500℃, 30min)F.G. (N2:H2=97%:3%) PMA (500℃, 30min)F.G. (N2:H2=97%:3%)
Gate patterning Gate patterning
S/D holing and Al wiringS/D holing and Al wiring
29
DIW
HF (1%)
DIW
H2O2:H2SO4 = 1:4
DIW 5 min
5 min
30 sec
5 min
Figure 2.3 Si wafer cleaning process.
5 min
Table 2.1 Sources and related effects of various contaminations
Contamination Possible source Effects
Particles Equipment, ambient, gas,
DIW, chemical
Low oxide breakdown (BKD); Poly-Si
and metal bridging-induced low yield;
Metal Equipment, chemical, reactive ion
etching, implantation, ash removing
Low BKD field; Junction leakage;
Vth shift;
Organic Vapor in room, residue of photo-resister,
storage containers, chemical Change in oxidation rate;
Micro roughness Initial wafer material, chemical Low oxide BKD field;
Low mobility of carrier;
Native oxide Ambient moisture, DIW, rinse Degraded gate oxide; High contact
resistance; Poor siliside formation;
Figure 2.3 shows the processes flow for Si wafer cleaning. First, the Si wafer is rinsed
with Diluted Ion Water (DIW) for 5 minutes.
Next, the Si wafer is rinsed in SPM
(H2O2:H2SO4 = 1:4) solution followed by a HF
(1%) solution dip. This step results in hydrogen
termination of substrate’s surface (HF-last) and
is effective for reducing defects at oxide/Si-sub
interface.
4) Gate oxide deposition by electron-beam evaporation system
In this study La2O3 dielectric film is deposited by the E-beam evaporation method in the
ultra high vacuum deposition chamber, as shown in Figure 2.4. There are eight
30
compartments to allocate various solid high-k material sources at the bottom of the
chamber. The Si-substrate is heated and its temperature is maintained at 250 to 300 oC
during La2O3 deposition. Electron beam is accelerated at 5 kV and focused towards the
La2O3 source which results in its evaporation. During evaporation process, the base
pressure inside growth chamber is maintained at 10-6 - 10-7 Pa. The physical thickness
of the deposited La2O3 thin film is controlled and monitored by a crystal oscillator. To
ensure a better uniformity of the deposited film layer, the sample holder is rotated
during La2O3 layer deposition.
5) Gate electrode deposition by radio frequency sputtering system
Tungsten (W) and tantalum nitride (TaN) were deposited by RF sputtering system on
top of the La2O3 layer. Figure 2.5 shows the schematic illustration for RF magnetron
Figure 2.4 Schematic illustration of E-beam evaporation system.
…1 2 7 8…
La2O3
E-gun
E-beam
Thickness monitor Sample
holder
Heater
Sources
Deposition chamber
(~10-7Pa)
…1 2 7 8…
La2O3
E-gun
E-beam
Thickness monitor Sample
holder
Heater
Sources
Deposition chamber
(~10-7Pa)
31
sputtering system. This equipment deposits metal film by means of physical sputtering
that occurs in a magnetically-confined RF plasma discharge of an inert argon (Ar) gas
ambient. The base pressure during sputtering process is 10-5 Pa. The thickness of the
sputtered W (or Ta) metal layer was controlled by deposition time, and the thickness of
the La2O3 layer was confirmed by spectroscopic ellipsometer measurements.
6) Reactive ion etching for gate electrode and gate dielectrics
RIE is one of the methods to etch the patterned films [2]. It is similar to RF magnetron
sputtering, but it is used by not only physical but also chemical reaction. The schematic
illustration of RIE system is shown in Figure 2.6.
The etching gases for metal gate, high-k layer (La2O3) and resistor ash are sulfur
hexafluoride (SF6) gas, Ar gas, and O2 gas, respectively. Table 2.2 shows RIE gases for
Figure 2.5 Schematic illustration of RF sputtering system [1].
Substrate Heater Sample
Ta Target
Top electrode
RF Power Source
Plasma
Substrate Heater Sample
Ta Target
Top electrode
RF Power Source
Plasma Ar gas
Or W target
32
etching contaminations in the gate stacks. First, the gas used to etch the film, turns to
plasma. In the plasma status, ionized radicals of cations and anions exist in the process
chamber. Chemical reaction occurs when the ionized radicals are absorbed on the
substrates, and the unprotected part of the sample is removed from the substrates.
Meanwhile, as a physical etching process, collisions of cations with the substrates occur
due to the electric field.
Table 2.2 Etching methods for gate metal and dielectric layers in the gate stacks
Contamination Etching method conditions
SiO2 Wet etching in BHF solution at 23 oC
W RIE by SF6 gas Gas flow 30 sccm, RIE power 30 W at 23 oC
Ta RIE by SF6 gas Gas flow 30 sccm, RIE power 30 W at 23 oC
TaN RIE by SF6 gas Gas flow 30 sccm, RIE power 30 W at 23 oC
La2O3 RIE by Ar gas Gas flow 15 sccm, RIE power 50 W at 23 oC
Resistor ash RIE by O2 gas Gas flow 99 sccm, RIE power 30 W at 23 oC
Al Wet etching in NMD-3 (2.38%) at 23 oC
Figure 2.6 Schematic illustration of RIE system [3].
plasma
Substrate
Radical e-
SF6 or O2
e-
e-
e-
e-
Cation
33
7) Thermal annealing process
Thermal annealing process is used in modern semiconductor fabrication for defects
recovery, lattice recovery or impurity electrical activation of doped or ion implanted
wafers. During the thermal annealing process there is a possibility for ingredients of
each layer in MOS structure to diffuse into other layers. A proper thermal annealing
process must be selected to acquire the desired device performance. In this thesis, we
studied both in-situ annealing and ex-situ annealing approaches. In-situ annealing
process is when wafers are directly loaded into thermal annealing system after metal
gate deposition without exposing the wafers to the air. In contrast, ex-situ annealing
process is when the wafers are taken out from metal gate deposition system and exposed
to air in order to transfer into a thermal annealing unit. In this study, thermal treatment
utilizing infrared lamp typed rapid thermal anneal (RTA) system was applied. For
ex-situ annealing, QHC-P610CP RTA system (ULVAC Co.) is applied for post
metallization annealing (PMA) in forming gas (F.G) (H2:N2 = 3%:97%). Figure 2.7
illustrates the schematic drawing for ULVAC QHC-P610CP [4].
For in-situ annealing, prior to every annealing cycle, residual gas species inside the
anneal chamber and gas lines were pumped out and purged to minimize possibility of
contamination of other existence gases or particles.
34
8) Vacuum pumps
Vacuum components play an important role in semiconductor technology, especially in
MOS device fabrication processes. A schematic of turbo and rotary pump connection
settings are shown in Figure 2.8. Table 2.3 shows vacuum pumps and their usages
applied in this study.
Figure 2.8 Schematic illustration of a vacuum process chamber for fabrication
of MOS devices.
Valve
Rotary pump
Turbo molecular pump
or Diffusion pump
Low vacuum gauge
High vacuum gauge
Process
Chamber
Valve
Rotary pump
Turbo molecular pump
or Diffusion pump
Low vacuum gauge
High vacuum gauge
Process
Chamber
Process
Chamber
Figure 2.7 Schematic illustration for QHC-P610CP RTA system.
Infrared lamp heating chamber
Valve
Turbo-moleculardrag pumpingsystem
Sample load gate
vacuum gauge
Infrared lamp heating furnace
Thermocouple
Infrared lamp heating chamber
Valve
Turbo-moleculardrag pumpingsystem
Sample load gate
vacuum gauge
Infrared lamp heating furnace
Thermocouple
H2/N2
N2
Gas inlets
Infrared lamp heating chamber
Valve
Turbo-moleculardrag pumpingsystem
Sample load gate
vacuum gauge
Infrared lamp heating furnace
Thermocouple
Infrared lamp heating chamber
Valve
Turbo-moleculardrag pumpingsystem
Sample load gate
vacuum gauge
Infrared lamp heating furnace
Thermocouple
H2/N2
N2
Gas inlets
H2/N2
N2
Gas inlets
35
Table 2.3 Vacuum pumps and their classification for MOS device processes
Vacuum levels Type of pumps Vacuum levels Usages
Low level vacuum Rotary pump 103-10-1 Pa Rough pumping
Diffusion pump 10-2-10-5 Pa When contaminations
are not critical High level vacuum
Turbo molecular
pump 10-2-10-8 Pa
When contaminations
are concerned
2.2 Physical Characterization of Gate Dielectrics
The physical characterization of deposited La2O3 films consisted of spectroscopic
ellipsometry measurements for physical thickness determination (of as-deposited
samples or La2O3 without annealing), transmission electron microscopy (TEM) for the
imaging of the structures and X-ray photoelectron microscopy (XPS), and also Fourier
transform infrared (FTIR) spectroscopy measurements for the analyzing of
characteristics of the chemical bondings at the interfaces created between La2O3 and
silicon-substrate. In this paragraph, an introduction for these measurement methods was
briefly described.
1) Ellipsometry measurement
Ellipsometry is a technique for analyzing the properties of a material (include in thin
films and semiconductors) from the characteristics of light reflected from its surface. In
this thesis, the initial physical thickness of the deposited La2O3 thin film was optically
36
extracted by Photal FE-5000 ellipsometer (OTSUKA Electronics) using a Cauchy
model and a single layer approximation [5]. As seen in Figure 2.9, the incident light
angle (θ0) was fixed at 70˚. The wave length of the incident light was varied from 300 to
800 nm.
In the ellipsometry measurement technique, a linearly polarized incident light changes
polarization state when it reflected from the film surface. The name ‘Ellipsometer’ is
related to the fact that the reflected light is elliptically polarized. The polarization can be
described by the σ (light polarized perpendicular to the plane of incidence) and π (light
polarized parallel to the plane of incidence) components of the electric field component
of the propagating light. The polarized light can be measured by a detector and the
complex ratio of the two reflection coefficients of π and σ polarized lights
Figure 2.9 Schematic illustration of ellipsometer [6].
Medium (2)Medium (2)
Medium (1)Medium (1)
Medium (0) (air)Medium (0) (air)
SubstrateSubstrate
FilmFilm dd
Light sourceLight source
PolarizerPolarizer
CompensatorCompensator
DetectorDetector
θθ00
θθ11
EEinin
Incident planeIncident plane
Output planeOutput plane
AnalyzerAnalyzerCompensatorCompensator
EEoutout
EEσσ
EEππ
EEσσ
EEππ
Medium (2)Medium (2)
Medium (1)Medium (1)
Medium (0) (air)Medium (0) (air)
SubstrateSubstrate
FilmFilm dd
Light sourceLight source
PolarizerPolarizer
CompensatorCompensator
DetectorDetector
θθ00
θθ11
EEinin
Incident planeIncident plane
Output planeOutput plane
AnalyzerAnalyzerCompensatorCompensator
EEoutout
EEσσ
EEππ
EEσσ
EEππ
37
je
P
PP )tan(
, (2.1)
is the basic equation in ellipsometry measurement. Where and are two
important parameters as functions of the complex refractive index of the film material.
Film thickness can be determined by three phase optical system consisting of
air/film/substrate structure. The reflection and transmission of the incident wave in the
air/film/substrate optical system is depicted in Figure 2.9. The incident angle for the
wave from the air (medium 0) to film is θ0. The incident wave is partially reflected at
the boundary and partially transmitted through the film (medium 1) at angle of θ1. The
transmitted part of the incident wave propagates through medium 1, again partially
reflected and partially transmitted through substrate (medium 2) at an angle of θ2. By
analyzing the reflection and transmission coefficients of σ and π polarized light, the film
thickness, d, can be expressed as [7]:
)cos(~2
1
11
nd . (2.2)
Where is wave length, 1~n is complex refractive index of the film. β is phase change
38
due to the propagation of the light wave through the medium 1, and can be related to the
reflection of the light from the medium 1 by an expression of [7]
,012
,12,01,12,014
,12,12,01
,012
,12,12,01,014
,12,01,12
)(
)(
jj
jj
ee
ee
P
PP . (2.3)
Where ,01 , ,01 , ,12 , ,12 are complex reflection coefficients related to the
complex refractive indexes, 0~n , 1
~n , 2~n for medium 0, 1, and 2 respectively. If a set of
ellipsometric parameters are measured at a
given angle of incidence θ0 and a give
wavelength , by solving eq. (2.1) and
(2.3) for the phase change β, the film
thickness of a sample can be determined
by eq. (2.2).
2) Transmission electron microscope
Transmission electron microscope (TEM)
uses a high voltage electron beam for creating images instead of using the visible light
(wavelength of 400 -700 nm). Using TEM enables the observation of objects in the
order of a few nanometers.
Figure 2.10 Schematic illustration of
transmission electron microscope [8].
ElectromagneticElectromagneticintermediate lensintermediate lens
Viewing screenViewing screen
SpecimenSpecimen
Electron beamElectron beam
Electron sourceElectron source
ElectromagneticElectromagneticcondense lenscondense lens
ElectromagneticElectromagneticprojector lensprojector lens
Objective Objective aperture lensaperture lens
ElectromagneticElectromagneticintermediate lensintermediate lens
Viewing screenViewing screen
SpecimenSpecimen
Electron beamElectron beam
Electron sourceElectron source
ElectromagneticElectromagneticcondense lenscondense lens
ElectromagneticElectromagneticprojector lensprojector lens
Objective Objective aperture lensaperture lens
39
The imaging process of the TEM is illustrated in a schematic Figure 2.10. Electrons
are emitted by an electron gun, and the electron beam is accelerated by an anode
typically at +100 keV (generally 40 to 400 keV) with respect to the cathode. The
accelerated electrons focused by electrostatic and electromagnetic lenses, and transmitted
through the specimen. The electrons transmitted through the specimen, carries
information about the structure of the specimen that is magnified by the objective lens
system of the microscope. The spatial variation in this information of the specimen may
be viewed by projecting the magnified electron image onto a fluorescent viewing screen
coated with a phosphor or scintillator material such as zinc sulfide. Alternatively, the
image can be photographed by charge-coupled device (CCD) camera. The image detected
by the CCD is displayed on a monitor.
The smallest distance between two points that we can resolve by our eyes is about
0.1-0.2 mm [8]. This distance is the resolution of our eyes. The Rayleigh criterion
defines the resolution of light microscope as [8]:
sin
61.0
n , (2.4)
40
where λ is the wavelength of the radiation, n is the refractive index of the view
medium and β is the semi-angle of collection of the magnifying lens. For the green light
with the wave length 550 nm, the resolution of light microscope gives around 0.3 m.
Based on wave-particle duality, if an electron is accelerated by an electrostatic
potential drop V, the electron wavelength can be described as [9]:
)]2/(1[2 2cmeVeVm
h
mv
h
oo . (2.5)
Where h is Planck constant, m0 is electron rest mass of electron, and c is the speed of
light. If we take the potential as 100 keV, the wavelength is 0.0371 Å. From eq. (2.4)
and (2.5), the higher accelerating rate of the electron beam, the higher resolution can be
obtained [10].
3) X-ray photoelectron spectroscopy
XPS is a well established technique for surface analyses of composition, and nature of
oxygen bonding and also oxidation state of the cations in the thin films.
41
XPS spectra are obtained by irradiating material with a beam of X-ray and
simultaneously measuring the kinetic energy and the number of escaped photoelectrons
from the ionized atoms by the X-ray irradiation. The process of electron emission is
shown schematically in Figure 2.11, where an electron from the K shell is ejected from
the atom (a 1s photoelectron). The relation between the energy of the incident photon
and escaped electrons from the material is expressed as [11]:
workbindkin EE , (2.6)
atomionbind EEE . (2.7)
Where , kinE , bindE , and work are energy of incident photon, kinetic energy of
Figure 2.11 Schematic illustration of X-ray irradiation on materials.
Conduction BandConduction Band
Valence BandValence Band
L1L1
KK
Fermi LevelFermi Level
Vacuum LevelVacuum Level
Incident XIncident X--rayray
1s1s
2s2s
2p2p L2,L3L2,L3
ħ
Ekin
Ebind
0 eV
Ekin
Core LevelCore Level
E
Ground state energyGround state energy
Emitted free electronEmitted free electron
Conduction BandConduction Band
Valence BandValence Band
L1L1
KK
Fermi LevelFermi Level
Vacuum LevelVacuum Level
Incident XIncident X--rayray
1s1s
2s2s
2p2p L2,L3L2,L3
ħ
Ekin
Ebind
0 eV
Ekin
Core LevelCore Level
E
Ground state energyGround state energy
Emitted free electronEmitted free electron
42
escaped electron from material, binding energy of atoms in material, and work function
of the spectrometer. Binding energy is representing the difference in energy between the
ionized and neutral atoms.
XPS spectra are plots of the measured numbers of the detected electrons versus the
kinetic energy of the detected photons. Different elements have different characteristic
set of peaks in their XPS spectra. The characteristics peaks refer to electron
configuration of the electrons within the atoms, for instance, 1s, 2s, 2p, 3s, etc. The peak
area determines the amount of elements within the area irradiated by X-rays. The
electronic state of the atom can affect the value of binding energy. When an atom is
bonded to another atom, the binding energy of the electron may increase or decrease.
The change in the binding energy can be applied to indentify the final electronic state of
Figure 2.12 XPS core-level spectra of O 1s for HfO2 [12].
HfOHfO22(0.5 nm)/SiO(0.5 nm)/SiO22(5 nm)(5 nm)
HfOHfO22(4 nm)/SiO(4 nm)/SiO22(5 nm)(5 nm)
SiOSiO22(5 nm)(5 nm)
SiSi--OO
SiSi--OO
SiSi--OOHfHf--OO--SiSi
HfHf--OO
HfHf--OO--SiSi
O 1sO 1s
HfOHfO22(0.5 nm)/SiO(0.5 nm)/SiO22(5 nm)(5 nm)
HfOHfO22(4 nm)/SiO(4 nm)/SiO22(5 nm)(5 nm)
SiOSiO22(5 nm)(5 nm)
SiSi--OO
SiSi--OO
SiSi--OOHfHf--OO--SiSi
HfHf--OO
HfHf--OO--SiSi
O 1sO 1s
43
the atoms in the sample. Figure 2.12 shows XPS core-level of O 1s spectra for HfO2
layer [12]. The binding energy for O 1s shifts to higher energy side with the increase of
the thickness of the HfO2 layer. Table 2.4 summarized binding energy of gate dielectrics
applied in this study.
Table 2.4 Binding energies for gate dielectric materials studied in this thesis
Bonds Electronic state Binding energy [eV]
Sio Si 2p3/2 99.25 [13]
Si4+ Si 2p3/2 103.15 [13]
O 1s 530.4 [14]
Ce 3d3/2 904.2 [15] CeO2
Ce 3d5/2 898.8, 885.9 [15]
O 1s 530.7 [14]
Ce 3d3/2 901.0, 907.5, 916.8 [15] Ce2O3
Ce 3d5/2 882.2, 888.2, 898.5 [15]
Hf-O O 1s 531.3 [12]
Si-O-Si O 1s 533.45 [15]
O 1s 531.8 [12] Hf-O-Si
Si 2p 103.3 [12]
La-O-Si O 1s 531.70 [15]
O 1s 529.56 [16] La-O-La
La 3d5/2 835.7, 839.2 [17]
4) Fourier-transform infrared spectroscopy measurement
FTIR is a vibrational spectroscopy measurement method based on the absorption of
infrared photons that excite vibrations of molecular bonds. As shown in Figure 2.13,
44
FTIR spectroscopy measurement method first collects an interferogram of a sample
using an interferometer and detector, then performs a Fourier transform (FT) on the
interferogram to obtain the spectrum. The FTIR spectra of La2O3 thin film was obtained
by JASCO FT/IR-4200 spectrometer.
Infrared spectroscopy exploits the fact that molecules absorb specific frequencies that
are characteristic of their structure. These absorptions are resonant frequencies, i.e., the
frequency of the absorbed radiation matches the vibration frequency of the bond or
group in the chemicals. Molecules only absorb infrared light at those frequencies where
the infrared light affects the dipolar moment of the molecule. In a molecule, the
differences of charges in the electronic fields of its atoms produce the dipolar moment
of the molecule. Molecules with a dipolar moment allow infrared photons to interact
with the molecule causing excitation to higher vibrational states. The homo-polar
diatomic molecules do not have a dipolar moment since the electronic fields of its atoms
are equal. Monatomic molecules do not have a dipolar moment since they only have one
Figure 2.13 Schematic illustration of FTIR measurement system.
Infrared SourceInfrared Source
DetectorDetector
ATR setupATR setup
InterferometerInterferometer
Infrared SourceInfrared Source
DetectorDetector
ATR setupATR setup
InterferometerInterferometer
45
atom. Therefore, molecules with homo-polar diatomic or with monatomic do not absorb
infrared light. For instance, the homo-polar diatomic (H2, N2, O2, etc.) molecules and
the monatomic (He, Ne, Ar, etc.) molecules do not absorb infrared light.
When an infrared light interacts with the matter, a chemical functional group tends to
adsorb infrared radiation in a specific wave number range regardless of the structure of
the rest of the molecule. For example, the C = O stretch of a carbonyl group appears at
around 1700 cm-1 in a variety of molecules.
When an interferogram is Fourier transformed, a single beam spectrum is generated. A
single beam spectrum is a plot of raw detector response versus wave number. A single
beam spectrum obtained without a sample is called a background spectrum, which is
induced by the instrument and the environments. Characteristic bands around
3500 cm-1 and 1630 cm-1 are ascribed to atmospheric water vapor and the bands at
2350 cm-1 and 667 cm-1 are attributed to carbon dioxide. The single beam spectrum of
the sample must be normalized against the background spectrum. Consequently, a
transmittance spectrum is obtained as follows:
oIIT / , (2.8)
46
where T is transmittance, I is the intensity measured with a sample in the beam,
and oI is the intensity measured from the back ground spectrum. The absorbance
spectrum can be calculated from the transmittance spectrum using the following
equation.
TA 10log , (2.9)
where A is the absorbance.
2.3 Electrical Characterization of MOS Devices
In this section, electrical characterization methods for MOS capacitors and MOSFETs,
such as estimation of interface trap states by conductance method, effective mobility
extraction by drain current measurement and split C-V method are described.
1) Trap states estimation by conductance technique
In this study, conductance method is used to estimate interface trap state density (Dit).
Conductance method is an approach which we replace the measurement circuit of MOS
capacitor with equivalent circuit models and calculate Dit. Figure 2.14(a) shows an
equivalent circuit model of MOS capacitor [18], where Cox is the oxide capacitance per
47
unit area, Cs is the silicon capacitance per unit area, Rit and Cit are the resistance and
capacitance components per unit area related to interface trap, and Gt is tunnel
conductance per unit area related to leakage current. On the other hand, the
measurement circuit is shown in Figure 2.14(b), where Cm and Gm are the measured
capacitance and conductance per unit area. And the equivalent parallel circuit is shown
in Figure 2.14(c), where Cp and Gp are the equivalent parallel capacitance and
conductance per unit area. The reason why it is changed like that can be expressed that
GP has only interface trap information not including CS when the circuit is converted.
CP and GP are given by
21 it
itSP
qDCC
, (2.10)
21 it
ititP DqG
, (2.11)
where Cit = qDit, and it = CitRit. Dit is interface state density and it is interface trap time
constant here. These two equations are for interface traps with a single energy level in
the band gap.
On the other hand, the capacitance and conductance are measured from the circuit in
48
Figure 2.14(b). By using equivalent circuit in Figure 2.14(c) GP/ can be calculated as:
222
2
mOXtm
OXtmP
CCGG
CGGG
. (2.12)
By considering the fluctuation of surface potential due to the inhomogeneities in oxide
charge and interface charge [19], and by assuming that the surface potential fluctuation
follows normal distribution, thus eq. (2.11) becomes
SSit
it
itP dPDqG
21ln2
, (2.13)
2
2
2 2exp
2
1
SS
SP . (2.14)
Figure 2.14 Equivalent circuits of MOS capacitor: (a) an equivalent circuit model of
MOS capacitor, (b) the measurement circuit, (c) the simplified circuit of (a).
CS
COX
Cit
Rit
GtCm Gm
CP
COX
GP
Gt
(a) (b) (c)
49
2) Threshold voltage and subthreshold slope determination
The threshold voltage (Vth) is one of the most important characteristics of a MOSFET
because it determines the switching characteristic of the device. Vth is defined as the
gate voltage necessary to form an inversion layer in the channel region. A common
measurement technique for determining Vth is the linear extrapolation method with the
drain current (Id) measured as a function of gate voltage (Vg). Drain voltage (Vd) in this
case is typically 50 -100 mV [18]. Due to the deviation of the Id curve from a straight
line at the Vg below Vth, generally the maximum slop of the Id -Vg curve determined by
the maximum point in the trans-conductance curve. As shown in Figure 2.15, Vth can be
determined from the intersection point of the vertical line with the Id -Vg curve and
extrapolating Id -Vg curve linearly to Id = 0.
Figure 2.15 Determination of threshold voltage by the linear extrapolation technique.
I d[A
/cm
2 ]
g m[S
/cm
2 ]
-1.5 1.5-0.5-1.0
25
Gate voltage [V]
L/W = 10/10 m
W/La2O3/Si(PMA@800oC)
1.0
20
15
10
Nsub= 31016 cm-3
EOT = 1.2 nm
5
0
Vth = -0.3V
gm-max
25
20
15
10
5
00 0.5
Id max slop
Vd = 50 mV I d[A
/cm
2 ]
g m[S
/cm
2 ]
-1.5 1.5-0.5-1.0
25
Gate voltage [V]
L/W = 10/10 m
W/La2O3/Si(PMA@800oC)
1.0
20
15
10
Nsub= 31016 cm-3
EOT = 1.2 nm
5
0
Vth = -0.3V
gm-max
25
20
15
10
5
00 0.5
Id max slop
I d[A
/cm
2 ]
g m[S
/cm
2 ]
-1.5 1.5-0.5-1.0
25
Gate voltage [V]
L/W = 10/10 m
W/La2O3/Si(PMA@800oC)
1.0
20
15
10
Nsub= 31016 cm-3
EOT = 1.2 nm
5
0
Vth = -0.3V
gm-max
25
20
15
10
5
00 0.5
Id max slop
Vd = 50 mV
50
The maximum slope of Id -Vg curve is usually expressed as the Subthreshold Slope
(S.S) as shown in Figure 2.16. S.S is a parameter that shows the gate control over
channel. In the experiment, the S.S is defined as the gate voltage required for decreasing
the drain current by one decade, and is given by
ox
dm
g
d
C
C
q
kT
dV
IdSS 13.2
log.
1
10, (2.15)
where k is the Boltzmann’s constant, T is absolute temperature of the system, q is the
electronic charge, Cdm is depletion-layer capacitance. If the density of interface trap
states is high, the subthreshold slope may be degraded due to the interface trap
capacitance which is in parallel with the depletion-layer capacitance [20, 21].
Figure 2.16 Id -Vg characteristics in logarithmic scale for typical MOSFETs.
I d[A
]
-1.0 1.00-0.5
110-4
Gate voltage [V]
W/La2O3/Si(PMA@800oC)
0.5
110-5
110-6
110-7
S.S = 61 mV/dec
L/W = 10/10 m
Nsub= 31016 cm-3
EOT = 1.2 nm
110-8
110-9
Vd = 50 mV
I d[A
]
-1.0 1.00-0.5
110-4
Gate voltage [V]
W/La2O3/Si(PMA@800oC)
0.5
110-5
110-6
110-7
S.S = 61 mV/dec
L/W = 10/10 m
Nsub= 31016 cm-3
EOT = 1.2 nm
110-8
110-9
I d[A
]
-1.0 1.00-0.5
110-4
Gate voltage [V]
W/La2O3/Si(PMA@800oC)
0.5
110-5
110-6
110-7
S.S = 61 mV/dec
L/W = 10/10 m
Nsub= 31016 cm-3
EOT = 1.2 nm
L/W = 10/10 m
Nsub= 31016 cm-3
EOT = 1.2 nm
110-8
110-9
Vd = 50 mV
51
3) Effective mobility measurement by spilt C-V method
The effective mobility (eff) of carriers in the inversion layer of MOSFETs is an
important parameter for device analysis, characteristics and design.
eff is defined by the measured Id, and the inversion layer charge density (Qinv) at a low
Vd in the linear region as [22]:
)(
1)(
)(
1
ginvgd
ginvd
deff VQ
VgW
L
VQV
I
W
L , (2.16)
where dgdgd VVIVg /)()( is the channel conductance. To obtain an accurate value of the
eff, it is necessary to determine accurate values for gd and Qinv in eq. (2.16). Figure 2.17
shows gd -Vg and Id -Vg characteristics of the fabricated La2O3 gate dielectric MOSFETs
Figure 2.17 Id -Vg and gd characteristics for nMOSFET.
Ch
ann
el c
ondu
ctan
ce [
A/V
]
-1.0 1.51.00-0.5
410-4
Gate voltage [V]
0
Vg = 20 mV
L/W = 10/10 m
W/La2O3/Si(PMA@800oC)
0.5
Dra
in c
urre
nt
[A]
310-4
210-4
110-4
210-5
1.510-5
1.010-5
0.510-5
0
Vg = 40 mV
Nsub= 31016 cm-3
EOT = 1.2 nm
Ch
ann
el c
ondu
ctan
ce [
A/V
]
-1.0 1.51.00-0.5
410-4
Gate voltage [V]
0
Vg = 20 mV
L/W = 10/10 m
W/La2O3/Si(PMA@800oC)
0.5
Dra
in c
urre
nt
[A]
310-4
210-4
110-4
210-5
1.510-5
1.010-5
0.510-5
0
Vg = 40 mV
Nsub= 31016 cm-3
EOT = 1.2 nm
52
with PMA at 800 oC in F.G for 30 min.
constVD
Dd
GV
Ig
. (2.17)
The split C-V measurement technique is well known for accurate measurement of the
carrier charge density in the channel. In the split C-V measurement, the capacitance
measured between the gate and the channel and between the gate and the substrate as
illustrated in Figure 2.18 [20]. The characteristics of gate-to-channel capacitance (Cgc)
and gate-to-body capacitance (Cgb) are illustrated in Figure 2.19. In order to avoid the
error from the non-linear dependency of the inversion layer charge density on the gate
voltage above the threshold voltage [23], a direct evaluation of inversion charge density
by integrating Cgc is applied [24]. Therefore, Qinv can be written as:
gV
gggcinv dVVCQ . (2.18)
Similarly, as shown in Figure 2.19 (b), the depletion layer charge Qb is also obtained
by integrating Cgb from VFB towards the inversion condition.
53
g
FB
V
Vgggbb dVVCQ . (2.19)
Then, the effective electric field Eeff can be expressed as [25]:
Figure 2.19 Characteristics for (a) gate-to-channel and (b) gate-to-body capacitances
for nMOSFET.
(a) (b)
Cgc
[F
/cm
2 ]
-1.0 1.00-0.5
2.5
Gate voltage [V]
L/W = 10/10 m
W/La2O3/Si(PMA@800oC)
0.5
2.0
1.5
1.0
Nsub= 31016 cm-3
EOT = 1.2 nm
0.5
0
QinvCgc
[F
/cm
2 ]
-1.0 1.00-0.5
2.5
Gate voltage [V]
L/W = 10/10 m
W/La2O3/Si(PMA@800oC)
0.5
2.0
1.5
1.0
Nsub= 31016 cm-3
EOT = 1.2 nm
0.5
0
Qinv Cgb
[F
/cm
2 ]
-2.0 0-1.0-1.5
2.5
Gate voltage [V]
L/W = 10/10 m
W/La2O3/Si(PMA@800oC)
-0.5
2.0
1.5
1.0
Nsub= 31016 cm-3
EOT = 1.2 nm
0.5
0
VFB
Qb
Cgb
[F
/cm
2 ]
-2.0 0-1.0-1.5
2.5
Gate voltage [V]
L/W = 10/10 m
W/La2O3/Si(PMA@800oC)
-0.5
2.0
1.5
1.0
Nsub= 31016 cm-3
EOT = 1.2 nm
0.5
0
VFB
Qb
Figure 2.18 Schematic configurations for (a) gate-to-channel and (b) gate-to-body
capacitances measurements for nMOSFETs [20].
p-SiDS
G
B
S/D
p-SiDS
G
B
S/D
(a) (b)
54
binvSi
eff QQE 1
, (2.20)
where are 1/2 for electrons and 1/3 for holes.
2.4 Summary
In this chapter, fabrication processes for MOS capacitors and MOSFETs are briefly
illustrated. Measurement techniques of Ellipsometry and FTIR for physical
characterization of gate dielectric layer, and the extraction methods of interface state
density and effective electron mobility for the electrical characterization of fabricated
MOS devices are briefly introduced.
55
References
[1] Kuriyama A, Effect of post metallization annealing for La2O3 thin film, Msc thesis,
Tokyo Institute of Technology, 24(2004).
[2] Nishioka K, Reactive ion etching of Si and SiO2,
http://www-eng.kek.jp/meeting09/proceedings/pdf/h21gp404.pdf.
[3] Kubota T, Estimation of interface and oxide defects in direct contact high-k/Si
structure by conductance method, Bsc thesis, Tokyo Institute of Technology,
11(2011).
[4] http://www.ulvac.com/thermal/qhc.asp.
[5] Kingery W, Bowen H, and Uhlmann D, Introduction to ceramics, 2nd Edition, John
Wiley & Sons, New York, 664(1976).
[6] http://www.australianscience.com.au/physics/ellipsometry-and-polarized-light.
[7] Azzam R M A, and Bashara N M, Ellipsometry and polarized light, Hardbound
edition, North Holland Press, Amsterdam, 283(1977).
[8] Williams D B, and Carter C B, Transmission electron microscopy, Plenum Press,
New York, 6(1996).
[9] Egerton R F, Physical principles of electron microscopy: an introduction to TEM,
SEM, and AEM, Springer-Verlag, New York, 11(2010).
56
[10] Jia C L, and Urban K, Atomic-resolution measurement of oxygen concentration in
oxide materials, Science, 303(5666), 2001(2004).
[11] Briggs D and Seah M P, Practical surface analysis: Auger and X-ray photoelectron
spectroscopy, 2nd Edition, John Wiley & Sons, New York, 124(1990).
[12] Duan T L, Yu H Y, Wu L, Wang Z R, Foo Y L, and Pan J S, Investigation of HfO2
high-k dielectrics electronic structure on SiO2/Si substrate by X-ray photoelectron
spectroscopy, Appl. Phys. Lett., 99(1), 012902(2011).
[13] Hirose K, and Hattori T, X-ray photoelectron spectroscopy study on Si
nanostructures, OYO BUTURI, 80(11), 942(2011).
[14] Mullins D R, Overbury S H, and Huntley D R, Electron spectroscopy of single
crystal and polycrystalline cerium oxide surfaces, Surf. Sci., 409(2), 307(1998).
[15] Shah L R, Ali B, Zhu H, Wang W G, Song Y Q, Zhang H W, Shah S I, and Xiao J Q,
Detailed study on the role of oxygen vacancies in structural, magnetic and transport
behavior of magnetic insulator: Co-CeO2, J. Phys.: Condens. Matter., 21(48),
486004(2009).
[16] Kakushima K, Tachi K, Song J, Sato S, Nohira H, Ikenaga E, Ahmet P, Tsutsui K,
Sugii N, Hattori T, and Iwai H, Comprehensive X-ray photoelectron spectroscopy
study on compositional gradient lanthanum silicate film, J. Appl. Phys., 106(12),
57
124903(2009).
[17] Hohira H, XPS study on chemical bonding states of high-k gate stack for advanced
CMOS, ECS. Trans., 28(2), 129(2010).
[18] Nicollian E H and Brews J R, MOS Physics and Technology, Wiley classic library
edition, John Wiley & Sons, New Jersey, 200(2003).
[19] Nicollian E H and Goetzberger A, The Si-SiO2 interface – electrical properties as
determined by the metal-insulator-silicon conductance technique, Bell System
Journal, 46(6), 1055(1967).
[20] Schroder D K, Semiconductor Material and Device Characterization, 3rd Edition,
John Wiley & Sons, New York, 347(2006).
[21] Kawanago T, A study on high-k/metal gate stack MOSFETs with rare earth oxides,
PhD thesis (Tokyo institute of technology), 32(2011).
[22] Hauser J R, Extraction of Experimental Mobility Data for MOS Devices, IEEE
Trans. Electron Devices., 43(11), 1981(1996).
[23] Sodini C G, Ekstedt T W, and Moll J L, Charge accumulation and mobility in thin
dielectric MOS transistors, Solid-State-Electron., 25(9), 833(1982).
[24] Liang M-S, Choi J Y, Ko P-K, and Hu C, Inversion-layer capacitance and mobility
of very thin gate-oxide MOSFETs, IEEE Trans. Electron Devices., 33(3),
58
409(1986).
[25] Takagi S-i, Toriumi A, Iwase M, and Tango H, On the universality of inversion
layer mobility in Si MOSFET’s: Part I – effects of substrate impurity concentration,
IEEE Trans. Electron Devices, 41(12), 2357(1994).
59
Chapter 3 Interfacial Silicate Layer Formation
One of the advantages of the La2O3 gate dielectrics is that a direct high-k contact with
Si-substrate can be realized by forming a La-silicate Interfacial Layer (IL) at the
La2O3/Si-substrate interface. In this chapter, characterization of the La-silicate IL and
effect of annealing temperature on the La-silicate IL formation are described.
3.1 Introduction
For MOS devices with EOT less than 0.7 nm, a direct high-k dielectrics contact with
Si-substrate is necessary. La2O3 based dielectrics have been widely studied for gate
insulator application [1-7], and recently, Kakushima et al. realized direct
La2O3/Si-substrate contact structure by forming La-silicate IL, which has a relatively
high dielectric constant [8]. Formation of La-silicate IL instead of SiOx at the
La2O3/Si-substrate interface during the thermal annealing process without employing
any complex fabrication process makes this material an attractive choice from the
fabrication point of view. In the following sections, formation mechanism of the silicate
IL and the effect of thermal annealing on the IL formation are analyzed.
60
3.2 Kinetics of Silicate Reaction
In this section, kinetics of the silicate reaction is described. La-silicate IL is formed by
increasing the PMA temperature, and the thickness of the layer is modeled by activation
energy in eq. (3.1) as [8]:
kT
ECt a
osilicate exp , (3.1)
where Co is the concentration of radical oxygen atoms at the La2O3/La-silicate interface.
Figure 3.1 shows the extracted EOTs and the estimated thickness of the interfacial
La-silicate layer versus the annealing temperature. The activation energy of silicate
formation Ea is 0.115 eV and dielectric constants of La2O3 and La-silicate layers are
assumed to be 23 and 7, respectively.
Silicate reaction is promoted by the presence of the radical oxygen atoms at the
surface of Si-substrate. Diffusion of oxygen atoms through gate oxide causes the
reaction of silicate formation [8]. Two factors for limiting the reaction rate can be
considered: (1) preventing the oxygen supply from the metal gate electrode, and (2)
deactivation of oxygen atoms in the silicate layer. Since the PMA time is 30 min for all
the samples, the oxygen atoms contained in W gate seem not to be a limiting factor for
61
EOT increment by the PMA temperature. Therefore, the deactivations of radical oxygen
atoms play important role in the silicate reaction mechanism.
Concentration of radical oxygen atoms in the La2O3 gate stack can be expressed by
mass transfer equation as [9]:
D
zCzC exp)( 0 . (3.2)
Where D and are diffusion constant and the life time of the radical oxygen atoms due
to the effect of deactivation in the silicate layer. 0C is the concentration of radical
oxygen atoms at the W/La2O3 interface as shown in Figure 3.2.
Figure 3.1 EOT increment with annealing temperature.
400As 600200 800
EO
T [
nm
]
1.6
0.8
1.2
0
2
1000
Annealing temperature [oC]
0.4
measurement
model
400As 600200 800
EO
T [
nm
]
1.6
0.8
1.2
0
2
1000
Annealing temperature [oC]
0.4
measurement
model
measurement
model
62
In eq. (3.2) the term D can be considered as a characteristic length of radical
oxygen atoms from La2O3/La-silicate interface, and it is proportional to the ionic
conductivity of the La-silicate layer. can be expressed in terms of the activation
Figure 3.3 Arrhenius plot of the formed silicate layer thickness and annealing
temperature [8].
Figure 3.2 Schematic illustration of concentration of oxygen atoms in the gate oxide [10].
63
energy aE for La-silicate formation and pre-exponential factor )(0 r . The activation
energy can be determined by Arrhenius plot of the formed La-silicate layer. Figure 3.3
shows the thickness of silicate layers in samples annealed at 300 and 500 oC, where the
thicknesses are extracted from TEM [8]. The activation energy for La-silicate formation
is the slope of the )/1/( Ttsili line.
3.3 FTIR Spectroscopy Analyze for La-silicate Formation
Previous researches by XPS [11], Rutherford backscattering [12] and TEM equipped
with electron energy-loss spectroscopy [13] have investigated the atomic distribution of
silicon within the formed La-silicate layer. The results of these works show that there is
a gradual compositional change of La-silicate in the direction normal to the Si-substrate.
XPS study of O 1s core level has revealed the existence of La-O-Si bonding, with a
binding energy (BE) located in between that of La-O-La and Si-O-Si bonding [5, 14 and
15]. Generally, La-silicate takes the form of an amorphous structure within the
temperature range of semiconductor fabrication process ( ~1000 oC ) [16]. However it is
possible for La-silicate layer to have a crystalline structure in the form of La2SiO5 which
has a tetrahedron SiO4 network [17]. The SiO4 network is connected through Si-O
bonds, where the oxygen atoms are called bridging oxygen (BO). When La atom is
64
diffused into the silicate layer, La atom breaks the Si-O bond and forms a La-O bond; in
this case the oxygen atom is called non-bridging oxygen (NBO). Due to the differences
in electro-negativity and binding energy, an increase in the amount of NBO decreases
the amount of BO [18, 19]. It is reported that the decrease in binding energy is the
reason for gradual compositional change of silicate structure [20].
FTIR spectroscopy can provide information about vibration modes of the bonding
states in the dielectric layer. Figure 3.4 shows the absorption intensity of the
photoelectrons in the samples annealed at various temperatures. Two absorption peaks,
one for longitudinal optical (LO) phonon, and the other for transverse optical (TO)
Figure 3.4 FTIR absorption spectroscopy of for samples annealed at temperatures of
200 to 800 oC and also as-deposited for W/La2O3 structure.
Ab
sorb
ance
LO phonon peak for Si —O — Si
0
1400 12001300
Frequency [cm-1]
1100 1000 900 800 700
800oC
750oC
700oC
650oC
600oC
550oC
500oC
450oC
400oC
300oC
200oC
-2
2
4
6
8
10
12
14
LO phonon peak for La-silicate
Ab
sorb
ance
LO phonon peak for Si —O — Si
0
1400 12001300
Frequency [cm-1]
1100 1000 900 800 700
800oC
750oC
700oC
650oC
600oC
550oC
500oC
450oC
400oC
300oC
200oC
-2
2
4
6
8
10
12
14
LO phonon peak for La-silicate
65
phonon, are observed. The absorption peaks gradually shift to the low frequency as the
annealing temperature increases. For annealing temperatures higher than 600 oC , the
vibration frequency of the LO remains constant at around 1248 cm-1. This is a typical
value for Si-O bonds in tetrahedral SiO4 network. Therefore, the LO phonon vibration
mode corresponds to the Si-O asymmetric stretch of SiO4 network.
Figure 3.5 shows the dependency of absorption peak values on the annealing
temperature in FTIR spectra. The peak position is stationary at a value around
1248 cm-1 for annealing temperatures higher than 600 oC. This result indicates that the
stretch of the SiO4 network is relaxed by high temperature annealing (600 oC or higher).
Figure 3.5 Annealing temperature dependency of absorption peaks in FTIR spectra.
1170
1180
1190
1200
1210
1220
1230
1240
1250
1260
200 300 400 500 600 700 800 900Annealing temperature [oC]
Relaxed SiO4(1248cm-1)
LO phonon
Wav
e n
umb
er [
cm-1
]
1170
1180
1190
1200
1210
1220
1230
1240
1250
1260
200 300 400 500 600 700 800 900Annealing temperature [oC]
Relaxed SiO4(1248cm-1)
LO phonon
Wav
e n
umb
er [
cm-1
]
[21]
66
3.4 Characterization of La-silicates
In this section, the results of characterization of La-silicates by XPS spectra are
described.
1) Sample preparation
High-k thin films were deposited by e-beam evaporation in an ultrahigh vacuum
chamber at a base pressure of 10-7 Pa from high-k oxide pressed targets. Substrates used
in this study were n-type Si (1 0 0) wafers with a doping density of 3×1015 cm-3.
Substrates were chemically cleaned and dipped in an HF solution prior to the oxide
deposition. The substrate temperature was 300 oC and the deposition rate was
0.2 nm/min. In order to avoid any moisture absorption from air, SiO2 film was capped
on top of the high-k surface.
XPS analysis is carried out for the samples with the structure of SiO2/La2O3/Si and
annealed in F.G ambient at 300 oC, 500 oC and 700 oC. The XPS measurement was
carried out at SPring-8 with BL46XU using an X-ray light source of 7940 eV at a
take-off angle (TOA) of 85o [22].
Grazing incident X-ray diffraction (GI-XRD) study was carried out by Grazing X-ray
spectrometer for two kinds of samples: a single layer of La2O3(4 nm), HfO2(4 nm); and
a double layers of La2O3(3 nm)/HfO2(1 nm), La2O3(2 nm)/HfO2(2 nm), and
67
HfO2(2 nm)/Sc(2 nm). All these samples were annealed in F.G ambient at 500 oC for
30 min. The wavelength of the incident ray is converted into wavelength of 1.54 Å of
Cu-K.
2) La-silicate characterization by XPS
O 1s spectra obtained from as deposited and annealed samples are shown in Figure 3.6.
La-silicate IL with two different compositions was formed at the interface of La2O3/Si.
The estimated band gaps of these La-silicate ILs are around 5.8 and 6 eV, respectively.
Expression (3.3) shows the possible silicate structures by reaction of oxygen atoms with
La2O3 dielectrics and Si-substrate.
,...OSiLa,OSiLa ,SiOLaOSiOLa 7222669.3352232 (3.3)
Densities of the La2O3 layer and La-silicate IL were extracted from GI-XRD spectra.
Figure 3.7 shows the detected intensities of GI-XRD versus incident angles of incident
X-rays. The measured data were fitted by least squares method, and the extracted values
of densities for each layer are shown in table 3.1. A value of 5.43 g/cm3 was obtained
for density of La-silicate IL.
68
Figure 3.6 O 1s spectra for samples of as deposited and annealed at 300 ~ 900 oC for
SiO2/La2O3/nSi structure.
528532536540544
La2O3
La Silicate1
as depo.
300 oC
500 oC
700 oC
5.84eV
5.79eV
5.75eV
6.05eV
Binding energy (eV)
Inte
nsi
ty (
a.u
.)
O1s profile of as deposited sample
La Silicate2
536540544 532 528528532536540544
La2O3
La Silicate1
as depo.
300 oC
500 oC
700 oC
5.84eV
5.79eV
5.75eV
6.05eV
Binding energy (eV)
Inte
nsi
ty (
a.u
.)
O1s profile of as deposited sample
La Silicate2
528532536540544
La2O3
La Silicate1
as depo.
300 oC
500 oC
700 oC
5.84eV
5.79eV
5.75eV
6.05eV
Binding energy (eV)
Inte
nsi
ty (
a.u
.)
O1s profile of as deposited sample
La Silicate2
528532536540544
La2O3
La Silicate1
as depo.
300 oC
500 oC
700 oC
5.84eV
5.79eV
5.75eV
6.05eV
Binding energy (eV)
Inte
nsi
ty (
a.u
.)
O1s profile of as deposited sample
La Silicate2
536540544 532 528
Figure 3.7 Trend of reflective X-ray intensity versus irradiating angle by GI-XRD
0 10.5 1.5 2
x10-3 w/o Al
w Al
2.5
x10-3 w/o Al
w Al
data
fitting
Θ[deg]
Ref
lect
ivit
y [a
. u]
10 1
10 0
10 -1
10 -2
10 -3
10 -4
10 -5
10 -6
10 -7
10 -8
10 -9
10 1
10 0
10 -1
10 -2
10 -3
10 -4
10 -5
10 -6
10 -7
10 -8
10 -9
Si
La2O3
SiO2
La-silicate
Si
La2O3
SiO2
La-silicate
0 10.5 1.5 2
x10-3 w/o Al
w Al
2.5
x10-3 w/o Al
w Al
data
fitting
data
fitting
Θ[deg]
Ref
lect
ivit
y [a
. u]
10 1
10 0
10 -1
10 -2
10 -3
10 -4
10 -5
10 -6
10 -7
10 -8
10 -9
10 1
10 0
10 -1
10 -2
10 -3
10 -4
10 -5
10 -6
10 -7
10 -8
10 -9
10 1
10 0
10 -1
10 -2
10 -3
10 -4
10 -5
10 -6
10 -7
10 -8
10 -9
10 1
10 0
10 -1
10 -2
10 -3
10 -4
10 -5
10 -6
10 -7
10 -8
10 -9
Si
La2O3
SiO2
La-silicate
Si
La2O3
SiO2
La-silicate
69
Table 3.1 Densities and thickness of each layer in SiO2/La2O3/La-silicate/Si sample by
XRD method
Material Density [g/cm3] Thickness [nm] SiO2 1.92 17.8
La2O3 6.57 3.78 La-silicate 5.43 1.33
Si 2.33 0.00
Figure 3.8 shows GI-XRD spectra for La2O3 and HfO2 gate stacked layers after
thermal annealing at 500 oC in F.G ambient for 30 min. Distinct crystallization peaks
were observed at 8.252 and 6.292 for the single layers of both La2O3(4 nm) and
HfO2(4 nm), respectively. These spectra suggest the presence of hexagonal and
monoclinic crystal phases for La2O3 and HfO2 dielectrics [23]. For
La2O3(3 nm)/HfO2(1 nm), La2O3(2 nm)/HfO2(2 nm), HfO2(2 nm)/Sc(2 nm) structures,
the crystallization peaks are notably suppressed. These results indicate that fabricating
Figure 3.8 Grazed incident XRD spectra for La2O3 and HfO2 gate stacked layers after
thermal annealing at 500 oC in F.G ambient.
2θ [deg.]
Inte
nsi
ty[a
. u]
La2O3(4 nm)HfO2(4 nm)Hf(3 nm)/La(1 nm)
Hf(2 nm)/La(2 nm)
20 25 30 35 40 45 50 55
SiO2/high-k/Si at PMA500oC
20 25 30 35 55504540Hf(2 nm)/Sc(2 nm)
2θ [deg.]
Inte
nsi
ty[a
. u]
La2O3(4 nm)HfO2(4 nm)Hf(3 nm)/La(1 nm)
Hf(2 nm)/La(2 nm)
20 25 30 35 40 45 50 55
SiO2/high-k/Si at PMA500oC
20 25 30 35 55504540Hf(2 nm)/Sc(2 nm)
70
high-k films composed of more than one rare earth element, is an effective method to
prevent crystallization of the high-k dielectrics due to thermal treatment.
3.5 Advantage of La2O3 Gate Dielectrics over CeOx
In this section, interface reactions of a Ce-oxide layer with Si (1 0 0) wafers are studied
by XPS analyses.
1) Sample preparation
Two kinds of samples were fabricated; 1: samples with 2- or 3-nm-thick Ce oxide layers
on Si-substrates, 2: a capacitor structure with a W layer on top of a 3-nm-thick Ce oxide
layer. The former set of samples is used to extract the photoelectron spectra of Ce atoms
from Ce-silicate and also to characterize the band alignment with respect to
Si-substrates. To promote the Ce oxides reaction with Si-substrates, high temperature
annealing at 900 oC for 2 sec was performed. For the MOS structure sample, 8-nm-thick
W layer was deposited by sputtering. The metal layers were deposited on the Ce oxide
layer without breaking the vacuum to avoid any contamination and water absorption
from the air. The capacitors were then annealed at 500 oC for 30 min in F.G ambient.
XPS measurement was carried out at SPring-8 with BL46XU using an X-ray source of
7940 eV at a TOA of 85o [22]. As the inelastic mean free paths (IMFP) of the
71
photoelectrons in the W metal arising from Ce 3d5/2 and Si 1s core levels are 6.9 and
6.4 nm respectively [24], the chemical bonding states can be probed through the
8-nm-thick W layer [25].
2) Band alignment of cerium silicate on Si (1 0 0)
Ce 3d5/2 and Si 1s spectra obtained from 2- and 3-nm-thick Ce oxide samples, which
were annealed at 900 oC are shown in Figure 3.9. Both spectra were normalized by the
intensity of the photoelectrons arising from the un-oxidized Si-substrate component in
the Si 1s spectra. The Ce 3d5/2 spectra showed no change in the shape except for the
intensity with the ratio of 1 to 1.3, which indicates that the Ce atoms are in the same
bonding states for the two samples. On the other hand, the photoelectrons arising from
the oxidized Si atoms in the Si 1s spectra revealed three oxide components with
Figure 3.9 (a) Ce 3d5/2 and (b) Si 1s spectra for 2 and 3-nm thick Ce-oxide/Si after
annealing at 900 oC.
72
different bonding states; a sub-oxide (Si1+) component with a peak intensity at an energy
of 1841.8 eV, a Ce-silicate signal at 1842.7 eV and an SiO2 bonding at 1844.0 eV [26].
As the photoelectron intensity of Si1+ and SiO2 spectra showed no difference between
the two samples, these bondings should locate at the interface between the Ce-silicate
and the Si-substrate with the same amount. The formation of a thin SiO2 layer by a
Ce-oxide layer is in contact with Si-substrate is in a good agreement with previous
report [27]. As the photoelectron intensity ratio of the Ce-silicate components in Si 1s
spectra between the samples was 1 to 1.3, one can conclude that the reactively formed
Ce-contained layers are compositionally uniform Ce-silicates.
The loss spectra in the O 1s core level and the valence band (VB) spectra with respect
to the Si-substrate Fermi level (EF) are shown in Figure 3.10. Two peaks observed in the
Figure 3.10 (a) O 1s and (b) VB spectra of Ce-silicates on Si (1 0 0).
73
O 1s spectra indicate the formation of Ce-silicate and SiO2 interfacial layer. The
difference in the O 1s spectra of the 2- and 3-nm-thick samples by subtraction showed a
single spectrum with peak energy of 530.83 eV, suggesting that the thickness of the
SiO2 layers were the same, which is in good agreement with the Si 1s spectra. The
photoelectrons obtained around 3.5 eV below the EF can be assigned as the Ce 4f 1
initial state, which is fully localized within the bandgap [28, 29]. Moreover, two peaks
observed at energies of 6.7 and 9.0 eV below the EF are the O 2p arising from the
interfacial SiO2 layer. Therefore, further subtracting the VB spectrum of SiO2, a VB
offset of 4.35 eV at Si-substrate and Ce-silicate layer can be determined [30]. Finally,
the conduction band (CB) offset of Ce-silicate and Si-substrate can be calculated as
2.20 eV.
3) Valence number transition in W/CeOx MOS capacitors by annealing
To observe the valence number transition of the Ce atoms in the Ce oxides before and
after the PMA, Ce 3d5/2 and Si 1s spectra were measured from Ce oxide capacitors with
W gate electrodes. Figure 3.11 shows the Ce 3d5/2 spectra of as-deposited state and after
annealing at 500 oC for 30 min. Compound spectra indicate the presence of Ce3+ and
Ce4+ as well as Ce-silicate components in the oxide film [31].
Using the first set of samples as a reference spectrum of Ce-silicate component, each
74
component of Ce3+ and Ce4+ can be extracted from the two Ce 3d5/2 spectra by
constructing linear equations. By comparing the photoelectron intensities in each
spectrum, 47 and 19 % of the Ce atoms were in Ce3+ and Ce4+ states, respectively, and
34 % of the Ce atoms were in the silicate state at as-deposited sample. Upon annealing,
the portion of Ce4+ and silicate increased up to 26 and 48 %, respectively, and the Ce3+
was found to decrease down to 26 %. CeO2 is known to promote oxidation of
Si-substrates by reducing the state from Ce4+ to Ce3+, producing Ce2O3 in the oxide and
SiO2 layer at the Si-substrate interface [32]. By further supplying of oxygen atoms from
environment to react with the SiO2 layer, the reaction advances to oxidize the Ce3+ to
Ce4+ and leaving Ce-silicates at the Ce-oxide/SiO2 interface. The source of oxygen,
which triggers the reaction, is originated from the sputter-deposited W gate electrode,
which is a metal known to contain oxygen atoms [8].
The growth of Ce-silicate layer is also confirmed from Si 1s spectra, as shown in
Figure 3.12 (a), where the photoelectron intensity of the silicate component increased by
2.4 times. The discrepancy in the increased ratio of silicates observed in Ce 3d5/2 and Si
1s spectra can be understood from the formation of Si-rich phase, which including
Ce2Si2O7 phase, after annealing. By subtracting the two Si 1s spectra, formation of SiO2
layer is observed during PMA annealing. Assuming a density of 5.78 g/cm3 (PDF
75
48-1588) [33] and IMFP of 10.1 nm for Si-rich Ce-silicate, the thickness of the silicate
can be calculated as 1.3 nm after annealing, which fairly matches with a thickness of 1.4
nm observed from TEM image, as shown in Figure 3.12 (b). In the same way, the
thickness of SiO2 layers can be calculated to increase from 0.44 to 0.96 nm after
annealing, which is also observed in the TEM image.
Promotion of Si oxidation under the presence of Ce and O atoms is known to take place
owing to two reactions; oxidation of Ce3+ to Ce4+ and reduction of Ce4+ to Ce3+ states
[32]. The valence number transitions of oxidation of Ce atoms can be expressed as:
4341
3 Ce)1(CeCeOSiCe xxnm silicate , (3.4)
Figure 3.11 Measured and deconvoluted Ce 3d5/2 spectra obtained from capacitor
structure: (a) before and (b) after annealing.
76
where m and n1 is the number of Si and O atoms required for reaction and x is the ratio
of Ce3+ atoms that is converted into silicate (0< x <1), so that the ratio of Ce atoms in
Ce4+ state is (1-x). At the same time, a part of the Ce atoms in Ce4+ states are reduced to
Ce3+ states by oxidizing Si atoms to form SiO2 as:
243
24 SiOCe)1(CeOSiCe yyyny , (3.5)
where y is the ratio of Ce3+ atoms that is reduced back from Ce4+ state and to form SiO2
at interface, and n2 is number of oxygen atoms required to proceed the reaction. The
created Ce atoms in Ce3+ state again follow the first reaction until the thermal
equilibrium is reached. By combining the two reactions, we can obtain the following
Figure 3.12 (a) Si 1s spectra obtained from W/Ce-oxide/Si structure before and after
annealing. The subtracted spectrum is also shown. (b) TEM
cross-sectional images before and after annealing.
77
reaction as:
43213 Ce11
)1(1Ce
11O
11
1Si
11
1Ce
yx
yx
yx
x
yx
nxn
yx
yxmsilicate
2SiO11
1
yx
yx
. (3.6)
The Ce 3d5/2 spectra indicated that the reacted Ce atoms in Ce3+ states were converted
into Ce- silicates and Ce4+ states with a ratio of 2 to 1, so that the following equation
can be derived.
yx
yx
yx
x
11
112
11 . (3.7)
On the other hand, assuming that newly created SiO2 layer after annealing is grown only
by the reduction of Ce atoms, another equation can be derived from the ratio of
increased photoelectrons in Si 1s spectra, shown in Figure 3.12 (a), as:
yx
yx
yx
x
11
1
114.1 . (3.8)
Solving the two equations, we can obtain x = 0.34 and y = 0.74.
78
4) Advantage of La2O3 over CeOx
XPS analyses show that Ce-silicate and SiO2 layers are formed at Si (1 0 0) interface
with CeOx gate dielectric during PMA. Valance number transition analysis in CeOx
show that oxidation of Si atoms is stronger than the formation of silicate. La2O3 gate
oxide on the other hand, promotes silicate formation rather than SiO2 at the interface.
3.6 Summary
In this chapter, the effect of the PMA on La-silicate IL is described. The EOT increment
with annealing temperature is caused by La-silicate IL formation due to the chemical
reaction of La, Si and O atoms at the La2O3/Si-substrate interface. Fourier Transform
Infrared Spectroscopy results indicate that high temperature annealing is required to
relax the stretch of SiO4 network of the La-silicate layer and thus preventing
crystallization of the high-k film. Wide band gap value of ~6 eV and physical density
value of 5.43 g/cm3 was obtained for La-silicate layer based on GI-XRD analysis. XPS
spectra results for CeOx show SiO2 interfacial layer formation at Ce-oxide/Si-substrate
interface due to valance number transition.
79
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84
Chapter 4 Evaluation of Interface and Oxide Trap States in
La2O3/La-Silicate Capacitors
In this chapter, origin of the trap states in La2O3 gate stacks is studied. A novel
interpretation of observed two peaks in the conductance spectra of La2O3/La-silicate
capacitors has been proposed.
4.1 Introduction
Formation of the La-silicate IL with higher dielectric constants (8~14) instead of SiO2
IL is one of the advantages of using La2O3 as a gate dielectrics for further downscaled
MOS devices [1, 2]. However, previous works show that Dit at the interface of
La-silicate/Si-substrate is still in the order of 1012 cm-2/eV and sensitive to the annealing
temperature [3]. This is due to high number of defects in La2O3 dielectric and also the
chemical reaction between La2O3 and Si-substrate. Therefore, it is necessary to reduce
the interface trap state densities in the La2O3/Si MOS devices. Another typical feature of
La2O3 gate stacked MOS capacitors is that their C-V spectra show frequency-dependent
humps near the flat-band condition as shown in Figure 4.1. It is also important to
85
identify the physical origin of the traps responsible for this behavior. This would help
with improving the La2O3 /Si-substrate interfacial properties.
4.2 Conductance Spectra of La2O3 Gated MOS Capacitors
Figure 4.2 shows the measured conductance spectrum as a function of the voltage
frequency for both La2O3 and SiO2 MOS capacitors. The measured conductance
spectrum in depletion condition for SiO2-based capacitor shows only a single peak in
the high frequency region. However, two distinct peaks are observed in the conductance
spectrum of La2O3-based capacitor at the frequency region of 100 Hz ~ 2 MHz. The
conductance-frequency peaks in the low frequency region are nearly an order of
-0.5-1-1.5 0 0.5 1
Gate voltage [V]
3.0
2
1
0.5
0
Cap
acit
ance
[u
F/c
m2 ]
1.5
2.5
1.5
1 MHz
100 kHz
10 kHz
1 kHz
Ideal
PMA@600oC in F.G 30min
-0.5-1-1.5 0 0.5 1
Gate voltage [V]
3.0
2
1
0.5
0
Cap
acit
ance
[u
F/c
m2 ]
1.5
2.5
1.5
1 MHz
100 kHz
10 kHz
1 kHz
Ideal
-0.5-1-1.5 0 0.5 1
Gate voltage [V]
3.0
2
1
0.5
0
Cap
acit
ance
[u
F/c
m2 ]
1.5
2.5
1.5
1 MHz1 MHz
100 kHz100 kHz
10 kHz10 kHz
1 kHz1 kHz
IdealIdeal
PMA@600oC in F.G 30min
Figure 4.1 Capacitance versus gate bias for a sample annealed at 600 oC. The dots
correspond to the measured capacitances for the frequency range from 1 kHz to 1 MHz,
and the solid line corresponds to the ideal curve of SiO2.
86
magnitude higher than the conductance-frequency peaks in the high frequency region.
Moreover, the conductance peaks at the low frequency region are less dependent on the
electron energy, whereas the conductance peaks at high frequency region change with
the electron energy.
Figure 4.3 shows the trap time constants estimated from these conductance peaks. The
conductance-frequency peaks in the high frequency region (100 kHz ~ 2 MHz), show a
shorter trap time constant for the capture and emission process, and their value vary
Figure 4.2 Gp/ω as a function of frequency. The left y-axis is for La2O3 gate stack
capacitor, which is annealed at 600 oC. The solid lines correspond to the fitting curves
by our modified model with the fitting parameters of sot510~ , sit
710~ , 410~ .
The right y-axis is for SiO2 capacitor. The conductance data for both La2O3 and SiO2
sample correspond to the eV 11.0s . All data are taken by the measured voltage
amplitude of 100 mV.
10110-1 102100 103 104
Frequency [kHz]
2
1
0.5
0
Gp
/[u
F/c
m2 ]
1.5
2.5E-Ei=0.31 eV
0.005
0.003
0.002
0.001
Gp
/[u
F/c
m2 ]
0.004
0
SiO2
La2O3
E-Ei=0.26 eV
E-Ei=0.21 eV
E-Ei=0.16 eV
E-Ei=0.21 eV
10110-1 102100 103 104
Frequency [kHz]
2
1
0.5
0
Gp
/[u
F/c
m2 ]
1.5
2.5E-Ei=0.31 eV
0.005
0.003
0.002
0.001
Gp
/[u
F/c
m2 ]
0.004
0
SiO2
La2O3
E-Ei=0.26 eV
E-Ei=0.21 eV
E-Ei=0.16 eV
E-Ei=0.21 eV
87
significantly with the surface potential. On the other hand, the conductance-frequency
peaks in the low frequency region (100 Hz ~ 10 kHz), show a longer trap time constant
for the capture and emission process, and vary marginally in their values with the
surface potential. Conductance-frequency peaks in the high frequency region can be
considered to be caused by interface trap states. This means that the trap centers are
located at/or near the oxide/Si interface. The conductance-frequency peaks in the low
frequency region are assumed to be caused by trap states other than interface traps. We
have assigned the low frequency conductance peaks to slow traps, meaning the electron
capturing time is slower than the electron capturing time for the typical interface trap
Figure 4.3 Interface trap time constant ( it ) and slow trap time constant ( slow )
versus electron energy; the closed dots represent it and the closed triangles
represent slow .
0.20 0.30.1 0.4
E-Ei [eV]
1
10-2
Tra
p t
ime
con
stan
t [
10-4
s]
10
10-1
10-3
EcEi
it
slow
0.20 0.30.1 0.4
E-Ei [eV]
1
10-2
Tra
p t
ime
con
stan
t [
10-4
s]
10
10-1
10-3
EcEi
it
slow
88
states. In the following sections, we attempt to clarify the origins of these slow traps in
the La2O3 gate dielectric MOS capacitors.
4.3 A Proposed Method for La2O3/Si Trap States Characterization
Generally, Gp,it for interface traps with continuum energy level in the band gap can be
expressed by Dit and time constant (it) by a statistical Gaussian model based on surface
potential fluctuation as eq.(4.1) and (4.2).
sssit
sit
sititp dPDqG
1ln
22,
,
(4.1)
2
2
2 2exp
2
1
ss
sP , (4.2)
where q, , s and are the electronic charge, angular frequency, the normalized
mean surface potential and standard deviation, respectively [4]. By setting proper values
for Dit, it and , the conductance spectrum shown in Figure 4.2 for SiO2 and the fast
traps with La2O3 capacitors can be reproduced as shown with solid line. Since it and
showed little difference between two gate oxide materials, the basic mechanism for the
89
carrier trappings can be assumed identical. Therefore, we can conclude that the fast
traps which peak at a frequency of 800 kHz can be related to Dit located at the
La-silicate/Si-substrate interface. The decreasing trend of Dit towards Si mid-gap as
shown in Figure 4.3, is a typical feature of interface trap states in Si (1 0 0)-orientated
substrate.
On the other hand, the slow traps in the conductance spectrum (Gp,slow) have a single
time constant (slow) and a single trapping energy level, expressed in eq. (4.3)
2,
1 slow
slowslowslowp DqG
. (4.3)
Figure 4.4 Energy distribution of the Dit and Dslow within the band gap of Si.
0.20 0.30.1 0.4
E-Ei [eV]
Dsl
ow, D
it[c
m-2
/eV
]
11014
EcEi
Dit
Dslow
11013
11011
11010
0.20 0.30.1 0.4
E-Ei [eV]
Dsl
ow, D
it[c
m-2
/eV
]
11014
EcEi
Dit
Dslow
11013
11011
11010
90
Since slow is larger than it, the physical origin of these slow traps can be considered
either at deep energy levels within the bandgap of silicon or inside oxide layer. The
former possibility can be eliminated since the capacitors are biased in depletion
condition. Surface potential fluctuation in depletion condition should broaden the
spectrum by convolution of Gaussian distribution expressed in eq. (4.2). Traps in oxide
are known to behave like slow-states to generate low frequency (1/f) noise in SiO2 case.
M. J. Uren et al. reported that the traps in the oxide with a time constant of ox and trap
state density (Dox) can be expressed as eq. (4.4)
)(tan22
1,ox
oxoxp qDG
, (4.4)
A plateau in the conductance spectra can be observed at low frequency region, typically
below 100 kHz [5]. In a real device, traps are distributed both spatially and energetically
in the oxide. This results in the broadening of the spectrum. Therefore, the observed
slow traps here should be located at the same distance or distributed with a certain
distance from Si-substrate. Indeed, the fact that the capture cross-section of the slow
traps (slow) show a strong dependency on the distance from the substrate, which can be
explained by the tunneling probability for trapping, also supports our model. This will
91
be discussed in more detail in the next section.
The slow-state traps should be energetically distributed at a fixed level, since the
amount of these traps is almost constant even considering the surface potential
fluctuation. Here we propose that the physical origin of the traps can be considered to be
at the interface of La2O3 and La-silicate layer. La2O3 is known to react with Si-substrate
to form a La-silicate interfacial layer. The thickness of the La-silicate layer is dependent
on the annealing process; oxygen partial pressure and temperature. The atomic bonding
in La2O3 is known to be of ionic nature and in La-silicate layer more of a covalent
nature. It is reported that at the boundary of two materials with ionic and covalent bonds,
a large amount of oxygen vacancies are presented [6]. These vacancies can be
Figure 4.5 Band diagram representing the proposed interpretation of the location
of trap sites for La2O3 gated MOS capacitors.
Fast-state Dit
La-silicate
tsilicate
La2O3
Si-substrateMetal
Ef
Ec
Ev
Oxide trap state
Slow-state Dslow
Fast-state Dit
La-silicate
tsilicate
La2O3
Si-substrateMetal
Ef
Ec
Ev
Oxide trap state
Slow-stateDslow
Fast-state Dit
La-silicate
tsilicate
La2O3
Si-substrateMetal
Ef
Ec
Ev
Oxide trap state
Slow-state Dslow
Fast-state Dit
La-silicate
tsilicate
La2O3
Si-substrateMetal
Ef
Ec
Ev
Oxide trap state
Slow-stateDslow
92
eliminated by low-temperature oxidation. However, they can also be easily created by
annealing in reducing ambient [7]. The localized traps at ionic-HfO2 and covalent SiO2
have been reported to be probed by charge-pumping measurement [8]. Therefore, it is
plausible to consider the slow traps to be located at La2O3 and La-silicate interface. The
proposed interpretation of the interface and slow traps is schematically illustrated in
Figure 4.5.
4.4 Effect of Annealing Temperature on Trap States in La2O3 Gate Stacks
In this section, the dependency of Dit and Dslow on PMA temperature is investigated.
In Figure 4.6 (a), (b), and (c) show PMA temperature dependencies of the trap states,
capture cross sections and the flat band voltage shifts due to the slow trap states,
respectively. Both Dit and Dslow decrease with higher annealing temperature, in which a
large decrease by two orders of magnitude is achieved with Dit, as shown in Figure 4.6
(a). On the other hand, only a slight decrease by half in Dslow indicates that the traps
located at La2O3 and La-silicate layer is hardly improved by annealing process. The
capture cross-section of interface trap states (it) and slow trap states slow dependencies
on the annealing temperature are shown in Figure 4.6 (b). The decrease in it with
annealing temperature up to 500 oC can be considered as the effect of hydrogen atom
93
passivation of dangling bonds at the Si substrate. it stays almost constant at annealing
temperature over 600 oC. On the other hand, slow is showed continuous decrements
with the annealing temperature. Based on our assignment that Dslow is located at the
interface between La2O3 and La-silicate layers, the slow should follow
silicate
slow
texp0 , (4.5)
where 0 and are the capture cross-section pre-factor and attenuation wave function
coefficient related to tunnel probability extracted from WKB approximation [9].
Therefore, the slow values on the annealing temperature can be obtained from eq. (3.1)
and (4.5) as
kT
Easlow exp
1
10ln
1log 010
. (4.6)
The calculated slow in Figure 4.6 (b) with 0 and of 7×10-14 cm-2 and 0.8 nm,
respectively, shows fairly nice agreement with the obtained data. This also supports our
interpretation of the slow traps to be the traps located at La2O3 and La-silicate interface.
94
When the gate voltage is biased over VFB to accumulation region, conductance spectra
cannot be obtained due to excess majority carriers [5]. However, the electron trapping
into slow traps, still occurs while increasing the gate voltage. When the C-V curves are
fitted with ideal curves at the accumulation region, we see a discrepancy near VFB, a
stretch-out behavior. As most of the interface trap states are occupied by the electrons,
the shift can be mainly considered as the contribution of the slow traps. Indeed, suppose
400As 600200 800 1000
Annealing temperature [oC]
400As 600200 800 1000
Annealing temperature [oC]
400As 600200 800 1000
Annealing temperature [oC]
Dit
,Dsl
ow[c
m-2
/eV
] 1014
1013
1012
1011
Dslow
Dit
10-11
it, s
low
[cm
2 ]
10-12
10-13
10-14
10-15
fitting
it
slow
VF
B[V
]
-0.05
-0.15
-0.10
0
-0.20
measurementestimation
-0.25
-0.30400As 600200 800 1000
Annealing temperature [oC]
400As 600200 800 1000
Annealing temperature [oC]
400As 600200 800 1000
Annealing temperature [oC]
400As 600200 800 1000
Annealing temperature [oC]
Dit
,Dsl
ow[c
m-2
/eV
] 1014
1013
1012
1011
Dslow
Dit
Dslow
Dit
10-11
it, s
low
[cm
2 ]
10-12
10-13
10-14
10-15
fitting
it
slow
VF
B[V
]
-0.05
-0.15
-0.10
0
-0.20
measurementestimationmeasurementestimation
-0.25
-0.30
Figure 4.6 Dependencies of (a) Dit and Dslow, (b) capture cross-sections, and (c)
VFB on annealing temperature.
(a)
(b)
(c)
95
all the trappings beyond VFB to the accumulation region are to be due to slow traps with
a constant Dslow, one can estimate the shift in the VFB from the ideal value by tsilicate. The
shifts in the VFB (VFB) at each annealing temperature with Dslow of 2.8×1013 cm-2/eV
are shown in Figure 4.6 (c). We can see that the VFB can be well reproduced with our
model, which also supports our interpretation of slow traps. Also, it is worth to note that
the energy distribution of Dslow is still constant even at the energy range out of the
bandgap of Si-substrate.
4.5 Summary
Conductance spectra of La2O3 dielectrics MOS capacitors were analyzed. Based on
observed experimental results, a novel interpretation of the two peaks in the
conductance spectra of La2O3/La-silicate gate dielectric capacitors has been proposed.
The fast-state response is assigned to the interface trap state as is commonly observed
with SiO2 gate oxide. The slow-state response is assigned to trapping at the
La2O3/La-silicate interface for the following reasons: (1) The spectra have shown a
single-level trapping without statistical surface potential fluctuation; (2) Capture
cross-sections of the traps can be modeled by tunneling probability with the thickness of
silicate IL; (3) The trapped charges are in good agreement with the shift in the VFB.
96
References
[1] Kakushima K, Koyanagi T, Tachi K, Song J, Ahmet P, Tsutsui K, Sugii N, Hattori T,
and Iwai H, Characterization of flatband voltage roll-off and roll-up behavior in
La2O3/Si gate dielectrics, Solid-State Electron., 54(7), 720(2010).
[2] Kakushima K, Tachi K, Song J, Sato S, Nohira H, Ikenaga E, Ahmet P, Tsutsui K,
Sugii N, Hattori T, and Iwai H, Comprehensive x-ray photoelectron spectroscopy
study on compositional gradient lanthanum silicate film, J. Appl. Phys., 106(12),
124903(2009).
[3] Masson P, Autran J -L, Houssa M, Garros X, and Leroux C, Frequency
characterization and modeling of interface traps in HfSixOy/HfO2 gate dielectric
stack from a capacitance point-of-view, Appl. Phys. Lett., 81(18), 3392(2002).
[4] Nicollian E H and Brews J R, MOS Physics and technology, John Wiley & Sons,
New York, 199(2003).
[5] Uren M J, Collins S, and Kirton M, Observation of slow states in conductance
measurements on silicon metal-oxide-semiconductor capacitors, Appl. Phys. Lett.,
54(15), 1448(1989).
[6] Shiraishi K, Theoretical model for work function control, Microelectron Eng.,
86(7-9), 1733(2009).
97
[7] Nabatame T, Ohi A, and Chikyow T, Role of oxygen transfer for high-k/SiO2/Si
stack structure on flatband voltage shift, ECS Trans., 35(4), 403(2011).
[8] Ghobar O, Bauza D, and Guillaumot B, On the depth profiling of the traps in
MOSFET’s with high-k gate dielectrics, ECS Trans., 6(1), 219(2007).
[9] Heiman F P, and Warfield G, The effect of oxide traps on the MOS capacitance,
IEEE Tran. Electron Devices., 12(4), 167(1965).
98
Chapter 5 Interfacial Properties and Effect of Annealing
In this chapter, the effect of Post Metallization Annealing (PMA) on the interfacial
properties of La2O3 MOS capacitor is described. First, the effect of thermal treatment
timing on the La-silicate IL formation is discussed. The difference between in-situ and
ex-situ annealing approaches are compared by device characteristics. Finally, the effect
of the annealing temperature on the La-silicate formation is discussed.
5.1 Introduction
Radical oxygen within La2O3 gate dielectric insulator, promotes La-silicate formation at
the substrate interface. An excess amount of oxygen atoms results in the excess
formation of the La-silicate IL. On the other hand, an insufficient oxygen supply can
lead to formation of oxygen vacancies in La2O3 layer. These oxygen vacancies, which
being as Coulomb scattering centers, lead to mobility degradation of carriers in the
channel of MOSFETs [1]. Therefore, a careful annealing approach to maintain precise
control over the oxygen supply without degrading the electrical characteristics of
MOSFETs is required.
99
There are a number of works done to prevent EOT increment during the PMA process.
Kawanago et al. proposed a method of capping a Si layer on the metal gate to prevent
absorption of the oxygen atoms into the metal gate [2]. Meanwhile, Kitayama et al.
proposed a thin Si layer insertion between metal gate and La2O3 dielectric layer [3]. In
the latter case, by thermal annealing, an interfacial amorphous La-silicate layer is
formed between metal gate W and La2O3 layer. This amorphous interfacial layer inhibits
the diffusion of oxygen atoms through the dielectric grain boundaries and suppresses the
formation of the La-silicate IL at the La2O3/Si-substrate interface. In the approach of
Kawanago et al., extra steps are needed for patterning the gate electrode and
source/drain area. In the approach of Kitayama et al., the inserted Si layer turns to
La-silicate at the metal/La2O3 interface thus increasing the EOT of the gate stack. As
shown in Figure 5.1, in our method, an in-situ annealing approach is used in order to
Figure 5.1 Schematic diagram of preventing oxygen atoms diffusing into La2O3
gate dielectrics.
Si-substrate
La-silicate
La2O3
W
La-silicate/Si interface
La2O3/La-silicate interface
O2
Annealing temperature dependency
Si-substrate
La-silicate
La2O3
W
Si-substrate
La-silicate
La2O3
W
La-silicate/Si interface
La2O3/La-silicate interface
O2
Annealing temperature dependency
100
avoid exposing devices to the air.
5.2 The Effect of Air Exposure
In this section, effect of delaying the PMA time on the EOT of the gate oxide insulator
is discussed. Due to the absorption of oxygen atoms into the metal gate W [4], these
atoms can diffuse into the gate oxide insulator during thermal treating process. The
amount of the oxygen atoms in the metal gate affects the formation of the La-silicate IL
and interfacial properties of the gate stack.
In order to observe the effect of oxygen on the formation of the La-silicate IL,
samples were deliberately left in room temperature and pressure for a certain amount of
time before carrying out PMA process. The delay time for PMA is defined as the time
interval between deposition of gate metal and carrying out PMA. A delay time of few
hours, one day, two days, one week, and three weeks was investigated. The rest of the
fabrication flow was the same for all samples.
Figure 5.2 (a) and (b) show the dependence of measured capacitance and EOT on the
delay time for PMA, respectively. The results show that both the capacitance and EOT
decrease for longer delay times. The increment in EOT can be explained by contribution
of the oxygen atoms absorbed in W metal gate layer [4, 5]. The solid line in the Figure
101
5.2 (b) is fitting curve. The linear trend of increment in EOT can be attributed to a linear
dependency of the silicate thickness on the amount of oxygen concentration at the
W/La2O3 interface [6].
These results indicate that it is preferable to avoid exposing devices to oxygen
containing environments after gate metal deposition. By in-situ annealing approach, the
thermal annealing process is applied without exposing the wafers to the air. Hence,
in-situ annealing approach can effectively avoid EOT increment.
5.3 In-situ Post Metallization Annealing
In the previous section, it was shown that delaying the PMA timing contributes to the
EOT increment. In this section, in-situ annealing approach for minimizing oxygen
diffusion into W gate metal is discribed.
Cap
acit
ance
[F
/cm
2 ]
-1.0 1.00.50-0.5
1.2
0.8
Gate voltage [V]
0.4
0
0 day1 day
2 days1 week3 weeks
100 kHz
Cap
acit
ance
[F
/cm
2 ]
-1.0 1.00.50-0.5
1.2
0.8
Gate voltage [V]
0.4
0
0 day1 day
2 days1 week3 weeks
0 day1 day
2 days1 week3 weeks
100 kHz
105101 104103102
3.2
3.0
2.8
2.6
2.4
Annealing delay time [min]
EO
T [
nm
]
3.4
3.6
PMA@800oC
for 30 min in F.G
105101 104103102
3.2
3.0
2.8
2.6
2.4
Annealing delay time [min]
EO
T [
nm
]
3.4
3.6
105101 104103102
3.2
3.0
2.8
2.6
2.4
Annealing delay time [min]
EO
T [
nm
]
3.4
3.6
101 104103102
3.2
3.0
2.8
2.6
2.4
Annealing delay time [min]
EO
T [
nm
]
3.4
3.6
PMA@800oC
for 30 min in F.G
Figure 5.2 (a) measured capacitance variance with PMA delay time; (b) EOT
variance with PMA delay time.
(a) (b)
102
Figures 5.3 (a) and (b) show measured capacitance and EOT for the samples with in-situ
and ex-situ PMA, respectively. For the MOS capacitors with similar La2O3 gate
dielectric insulator and gate metal thickness, a smaller EOT value was obtained with
in-situ annealing approach compared to ex-situ annealing approach. In Figure 5.3 (b),
solid lines show the theoretical fitting lines. For samples with in-situ PMA, EOT
increment is saturated when the initial deposition thickness is larger than 4.5 nm. This
result indicates that La2O3 layer with a certain thicknesses remains in the gate stack and
does not turn to La-silicate. This is due to lack of sufficient oxygen supply.
5.4 Annealing Temperature Effects on Interfacial Property
In the previous sections, it was shown that in-situ PMA is an effective method for
suppressing EOT increase due to thermal treatment. In this section, we will discuss the
Figure 5.3 (a) measured capacitance and (b) extracted EOT for samples annealed
by in-situ and ex-situ approaches respectively.
0
0.5
1
1.5
2
2.5
3
-2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5
Vg (V)
Cg
(uF
/cm
2 )
800oC-ex situ
800oC-in situ
1MHz
EOT=1.06nm
EOT=0.99nm
TPhys~2nm
0
0.5
1
1.5
2
2.5
3
-2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5
Vg (V)
Cg
(uF
/cm
2 )
800oC-ex situ
800oC-in situ
1MHz
EOT=1.06nm
EOT=0.99nm
TPhys~2nm
(a) (b)
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
1.5 2.5 3.5 4.5 5.5
Thickness of La2O3 (nm)
EO
T (
nm
)
800oC-ex situ
800oC-in situ
EOTEOT comparisoncomparison
La2O3 remains
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
1.5 2.5 3.5 4.5 5.5
Thickness of La2O3 (nm)
EO
T (
nm
)
800oC-ex situ
800oC-in situ
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
1.5 2.5 3.5 4.5 5.5
Thickness of La2O3 (nm)
EO
T (
nm
)
800oC-ex situ
800oC-in situ
EOTEOT comparisoncomparison
La2O3 remains
103
effect of PMA temperature on the interfacial properties of the MOS capacitors with
W/La2O3/Si-subtrate structure.
Figures 5.4 (a), (b), and (c) compare the C-V characteristics of three MOS capacitors
with in-situ PMA treatment in various temperatures. For PMA temperature of 700 oC or
lower, device C-V curves have frequency-dependent humps in flatband condition. These
humps disappear by increasing the PMA temperature and the measured C-V approach
ideal curve. These results indicate that high temperature PMA improves the interfacial
properties of MOS capacitors with La2O3 gate dielectric insulator.
5.5 Summary
In this chapter, effects of PMA temperature on the electrical characteristics of MOS
capacitors were described. It was found that in-situ PMA is an effective method in order
0.5
1 MHz
100 kHz
10 kHz
Ideal
2.0
1.5
1.0
0.5
0-1.0 -0.5 0
800oC2.5
Gate voltage [V]0.5
1 MHz
100 kHz
10 kHz
Ideal
2.0
1.5
1.0
0.5
0-1.0 -0.5 0
800oC2.5
1 MHz
100 kHz
10 kHz
Ideal
2.0
1.5
1.0
0.5
0-1.0 -0.5 0
800oC2.5
Gate voltage [V]-0.5 0 0.5
1 MHz
100 kHz
10 kHz
Ideal
2.5
2.0
1.5
1.0
0.5
0-1.0
700oC
Gate voltage [V]
Cap
acita
nce
[F
/cm
2 ]
-0.5 0 0.5
1 MHz
100 kHz
10 kHz
Ideal
2.5
2.0
1.5
1.0
0.5
0-1.0
700oC1 MHz
100 kHz
10 kHz
Ideal
2.5
2.0
1.5
1.0
0.5
0-1.0
700oC
Gate voltage [V]
Cap
acita
nce
[F
/cm
2 ]
Figure 5.4 Measured capacitances for samples with in-situ PMA at (a) 700 oC, (b)
800 oC, and (c) 900 oC, respectively.
(a) (b) (c)
1 MHz
100 kHz
10 kHz
Ideal
0.5
2.5
2.0
1.5
1.0
0.5
0-1.0 -0.5 0
900oC1 MHz
100 kHz
10 kHz
Ideal
0.5
2.5
2.0
1.5
1.0
0.5
0-1.0 -0.5 0
900oC
104
to suppress EOT increase due to thermal treatment. Suppressing the promotion of
silicate reaction at La2O3/Si-subtrate interface by preventing the absorption of oxygen
atoms in the metal gate is considered to be the reason for this result. High temperature
PMA of 800 oC or more was found to be important for improving the interfacial
properties of La2O3 gate stacked MOS capacitors.
105
References
[1] Kim H, Mclntyre P C, Chui C O, Saraswat K C, and Stemmer S, Engineering
chemically abrupt high-k metal oxide/silicon interface using an oxygen-gettering
metal overlayer, J. Appl. Phys., 96(6), 3467(2004).
[2] Kawanago T, Lee Y, Kakushima K, Ahmet P, Tsutsui K, Nishiyama A, Sugii N,
Natori K, Hattori T, and Iwai H, Optimized oxygen annealing process for Vth tuning
of p-MOSFET with high-k/metal gate stacks, IEEE ESSDERC., 301(2010).
[3] Kitayama D, Koyanagi T, Kakushima K, Ahmet P, Tsutsui K, Nishiyama A, Sugii N,
Natori K, Hattori T, and Iwai H, Effect of thin Si insertion at metal gate/high-k
interface on electrical characteristics of MOS device with La2O3, Microelectron.
Eng., 88(7), 1330(2011).
[4] Kitayama D, Kubota T, Koyanagi T, Kakushima K, Ahmet P, Tsutsui K,
Nishiyama A, Sugii N, Natori K, Hattori T, and Iwai H, Silicate reaction control at
Lanthanum oxide and silicon interface for equivalent oxide thickness of 0.5 nm:
adjustment of amount of residual oxygen atoms in metal layer, Jpn. J. Appl. Phys.,
50(10), 10PA05-1(2011).
[5] Mamatrishat M, Kubota T, Seki T, Kakushima K, Ahmet P, Tsutsui K, Kataoka Y,
Nishiyama A, Sugii N, Natori K, Hattori T, and Iwai H, Oxide and interface trap
106
densities estimation in ultrathin W/La2O3/Si MOS capacitors, Microelecton.
Reliab., (2012). doi: 10.1016/j.microrel.2011.12.025;
[6] Itoh H, Nagamine M, Satake H, and Toriumi A, A study of atomically-flat SiO2/Si
interface formation mechanism, based on the radical oxidation kinetics,
Microelectron. Eng., 48(1-4), 71(1999).
107
Chapter 6 Impact of Metal Gate on Interfacial Properties
In this chapter, the impact of metal gate on the interfacial properties of La2O3 gate
stacked MOS capacitors is described. Effects of the physical thickness and material
nature of the metal gate on the formation of La-silicate interfacial layer are discussed.
6.1 Introduction
For the high-k gate dielectric gate stacked MOS devices, performance improvement can
not be solved solely from the improvement of the properties of the high-k dielectric
layer [1]. Impact of metal gate on the over all properties of the MOS device is also an
important factor for improving the performance of MOS devices with metal gate/high-k
structure. Several metal gate electrodes such as W/TiN, Mo, Ta, TaN, TiN and TaSixNy
have been studied as a replacement for poly-Si gate. Metal gates must have a suitable
work function, thermal and chemical stability with underlying gate dielectric insulator
[2]. Tungsten (W) has been explored extensively as a gate metal for CMOS technology
because of its low resistivity and near mid-gap work function [3-4]. However, for W
metal gates with HfO2 and ZrO2 gate insulator, the increase in the EOT of gate dielectric
108
layer was observed due to the formation of interfacial SiO2 layer during thermal
annealing process [5-7]. For La2O3 gate dielectric insulators with W metal gate, the
increment of EOT also observed due to the silicate IL formation at the interface of
La2O3/Si-substrate [8]. In these works, the formation of the IL at the high-k/Si-substrate
interface is believed due to the oxygen involvement in the oxidation of the interface of
high-k/Si-substrate, and the W metal gate layer is considered the source of the oxygen.
Observed results showed that oxygen atoms were absorbed in W metal layer during
sputtering deposition process. The source of this oxygen was considered to be the
impurities contained in Ar gas lines which were used during the deposition process. As
discussed in chapter 5, in our experiments, exposing the devices to room temperature
and pressure after gate deposition, was the main cause of oxygen absorption into W
metal film. These oxygen atoms promote silicate reaction at the interface of
La2O3/Si-substrate when PMA is conducted. The formation of the La-silicate IL at the
La2O3/Si-substrate interface, effects the interfacial properties of the gate stack and also
increases EOT of gate dielectric layer in MOS devices.
In the following sections, the effects of the physical thickness and material nature of
metal gate are explored as a mean to control the amount of oxygen atoms within the
gate stack. Figure 6.1 shows the schematic illustration of our approach.
109
6.2 Effect of Metal Gate Material on Interfacial Properties
In this section, the effect of metal gates with the medium work function, such as
tungsten (W) and tantalum nitride (TaN), on the interfacial property of La2O3 MOS
capacitors is described.
Figure 6.2 shows C-V characteristics for TaN(45 nm), W(60 nm), and
TaN(45 nm)/W(5 nm) metal gated La2O3 MOS capacitors with similar fabrication
process. Sample with TaN metal gate shows a distinct hump in the C-V characteristics,
whereas no humps are observed in the C-V characteristics of other samples. TaN gate
electrodes contain less oxygen atoms compared to the W gate electrode. Low oxygen
concentration of TaN gate electrode results in only a partial La-silicate transformation at
Figure 6.1 Schematic illustration of controlling of the supplement of oxygen
atoms in the metal gate.
Changing metal gate thickness
Controlling La-silicate formation
Si-substrate
La-silicate
La2O3
WO
O OO
O
OO
O
Si-substrate
La-silicate
La2O3
WO
OO
O
OO
O
Changing metal gate thickness
Controlling La-silicate formation
Si-substrate
La-silicate
La2O3
WO
O OO
O
OO
O
Si-substrate
La-silicate
La2O3
WO
OO
O
OO
O
Changing metal gate thickness
Controlling La-silicate formation
Si-substrate
La-silicate
La2O3
W
Si-substrate
La-silicate
La2O3
WOO
OO OOOO
OO
OOOO
OO
Si-substrate
La-silicate
La2O3
WO
OO
O
O
Si-substrate
La-silicate
La2O3
WOO
OOOO
O
OOOO
OO
110
the La2O3/Si-sub interface while the regions close to the metal gate remain in the form
of La2O3.
As shown in Figure 6.2 (c), the TaN capped sample shows less VFB shift compared to
the TaN, and W metal gate capacitors. When EOT value is less than 0.8 nm, no humps
can be observed, and the C-V curve is closer to the ideal curve. This implies that the
Figure 6.2 C-V characteristics of (a) TaN/La2O3/Si, (b) W/La2O3/Si, and (c)
TaN/W/La2O3/Si MOS capacitors.
(a) (b)
(c)
Cap
acit
ance
[F
/cm
2 ]
-1.0 0-0.5
Gate voltage [V]
TaN(45 nm)/W(5 nm)/La2O3(2~5 nm)/Si
0.5
@100kHz
1.0-1.5
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
EOT = 1.
0 nm
EOT = 0.6 nm
In-situ
PMA@800oC
EOT=0.6 nm
EOT=0.8 nm
EOT=1.0 nm
Ideal
Vfb= -370 mVCap
acit
ance
[F
/cm
2 ]
-1.0 0-0.5
Gate voltage [V]
TaN(45 nm)/W(5 nm)/La2O3(2~5 nm)/Si
0.5
@100kHz
1.0-1.5
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
EOT = 1.
0 nm
EOT = 0.6 nm
In-situ
PMA@800oC
EOT=0.6 nm
EOT=0.8 nm
EOT=1.0 nm
Ideal
EOT=0.6 nm
EOT=0.8 nm
EOT=1.0 nm
Ideal
Vfb= -370 mV
Cap
acit
ance
[F
/cm
2 ]
-1.0 0-0.5
Gate voltage [V]
TaN(45 nm)/La2O3(2~5 nm)/Si
0.5
@100kHz
1.0-1.5
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
EOT = 1.2 nm
EOT = 0.9 nm
In-situ
PMA@800oC
EOT=0.9 nm
EOT=1.1 nm
EOT=1.2 nm
Ideal
Big hump
Cap
acit
ance
[F
/cm
2 ]
-1.0 0-0.5
Gate voltage [V]
TaN(45 nm)/La2O3(2~5 nm)/Si
0.5
@100kHz
1.0-1.5
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
EOT = 1.2 nm
EOT = 0.9 nm
In-situ
PMA@800oC
EOT=0.9 nm
EOT=1.1 nm
EOT=1.2 nm
Ideal
EOT=0.9 nm
EOT=1.1 nm
EOT=1.2 nm
Ideal
Big humpC
apac
itan
ce [F
/cm
2 ]
W(60 nm)/La2O3(2~5 nm)/Si
@100kHz
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
EOT = 1.1 nm
EOT = 0.8 nm
In-situ
PMA@800oC
-1.0 0-0.5
Gate voltage [V]
0.5 1.0-1.5
EOT=0.8 nm
EOT=1.0 nm
EOT=1.1 nm
Ideal
Small humpC
apac
itan
ce [F
/cm
2 ]
W(60 nm)/La2O3(2~5 nm)/Si
@100kHz
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
EOT = 1.1 nm
EOT = 0.8 nm
In-situ
PMA@800oC
-1.0 0-0.5
Gate voltage [V]
0.5 1.0-1.5
EOT=0.8 nm
EOT=1.0 nm
EOT=1.1 nm
Ideal
EOT=0.8 nm
EOT=1.0 nm
EOT=1.1 nm
Ideal
Small hump
111
interfacial (La-silicate/Si-substrate) property of the gate stack has improved by capping
TaN on W metal gate. However, a relatively large negative VFB shift is observed when
EOT value is around 1.0 nm. The negative shift in VFB implies that the net positive
charges at the interfaces of La2O3/La-silicate and La-silicate/Si-substrate increase with
the La2O3 layer thickness.
(a) (b)
(c)
Figure 6.3 EOT dependence of flat band voltage for (a) TaN, (b) W, and (c) TaN/W
metal gated La2O3 MOS capacitors with PMA in F.G for 30 min at 800 oC.
Fla
t ba
nd v
olta
ge [
V]
Equivalent oxide thickness [nm]
TaN(45 nm)/La2O3(2~5 nm)/Si
1.0
EOT = 1.3 nmExperiment
Slope
-0.4
-0.5
-0.6
1.51.25
-0.45
-0.55
Fla
t ba
nd v
olta
ge [
V]
Equivalent oxide thickness [nm]
TaN(45 nm)/La2O3(2~5 nm)/Si
1.0
EOT = 1.3 nmExperiment
Slope
Experiment
SlopeSlope
-0.4
-0.5
-0.6
1.51.25
-0.45
-0.55
Fla
t ba
nd v
olta
ge [
V]
0.75
Equivalent oxide thickness [nm]
W(60 nm)/La2O3(2~5 nm)/Si
1.00.5-0.1
-0.2EOT = 0.9 nm
Experiment
Slope
-0.3
-0.4
-0.5
-0.6
1.51.25F
lat
band
vol
tage
[V
]0.75
Equivalent oxide thickness [nm]
W(60 nm)/La2O3(2~5 nm)/Si
1.00.5-0.1
-0.2EOT = 0.9 nm
Experiment
Slope
Experiment
SlopeSlope
-0.3
-0.4
-0.5
-0.6
1.51.25
Fla
t ba
nd v
olta
ge [
V]
0.75
Equivalent oxide thickness [nm]
TaN(45 nm)/W(5 nm)/La2O3(2~5 nm)/Si
1.00.5-0.1
-0.2
Experiment
Slope
-0.3
-0.4
-0.5
-0.6
1.51.25
Fla
t ba
nd v
olta
ge [
V]
0.75
Equivalent oxide thickness [nm]
TaN(45 nm)/W(5 nm)/La2O3(2~5 nm)/Si
1.00.5-0.1
-0.2
Experiment
SlopeSlope
-0.3
-0.4
-0.5
-0.6
1.51.25
112
Figure 6.3 shows EOT dependence of VFB for TaN, W, and TaN/W metal gated La2O3
MOS capacitors. VFB of the sample with the TaN metal gate (Figure 6.3 (a)) shows a
relatively large value compared to the sample with the W metal gate (Figure 6.3 (b)). On
the other hand, VFB of the sample with the TaN/W metal gate (Figure 6.3 (c)) shows the
smallest value. Both W and TaN/W metal gates show VFB roll-off behavior at EOT
around 0.8 nm and 0.9 nm, respectively. In the case of TaN metal gate, VFB roll-up is
observed at EOT around 1.3 nm. VFB shifts with EOT can be explained by fixed charges
located inside the gate oxide [9]. Therefore, from the slope of VFB the net charge
concentrations at the La2O3/La-silicate and La-silicate/Si-substrate interfaces can be
qualitatively estimated.
Table 6.1 Estimated net charge concentrations at the interfaces of La2O3 gate stacks
Sample EOT [nm] netQ [cm-2]
EOT<0.9 -3.191012 W(60 nm)/La2O3(2~5 nm)/Si
EOT>0.9 1.241013
EOT<1.3 8.651012 TaN(45 nm)/La2O3(2~5 nm)/Si
EOT>1.3 -8.201012 EOT<0.8 -1.711012
Ta(45 nm)/W(5 nm)/La2O3(2~5 nm)/SiEOT>0.8 2.421013
Table 6.1 shows the estimated net charge concentrations at the interfaces of La2O3 gate
stack. The net charge is the sum of all charges located at the La2O3/La-silicate and
113
La-silicate/Si-substrate interface. Judging by VFB, both W and TaN/W metal gate
samples show a large decrease in the net positive charges for 0.9 nm < EOT <1.3 nm.
Whereas a small increase in the net positive charges for the sample with TaN metal gate
is observed.
The negative shift of the VFB for EOT over 1.3 nm (as shown in Figure 6.3 (a)) can be
explained by the negative polarity of the net charges. The charges at the
silicate/Si-substrate interface are considered as positive because of the silicate formation
reaction includes oxidation of the Si atoms [10]. Therefore, the charges at the
La2O3/La-silicate should be negative since the bonding nature of oxygen atoms in the
La2O3 layer is different from the bonding of oxygen atoms in the La-silicate layer.
Oxygen atoms are negatively charged (O2-) in the La2O3 layer, and neutral (O0) in the
La-silicate layer. This bonding state of oxygen atoms in the La2O3 and La-silicate layers
leads to negatively charged electrons trapped at the La2O3/La-silicate interface [11].
When EOT is between 0.9 and 1.3 nm, the net positive charges increase due to the metal
diffusion or oxygen vacancies induced by metal atoms [12]. When EOT is less than
0.9 nm, the roll-off behavior can be explained by the net positive charge increase due to
the phase changes of La-silicate layer [13].
114
6.3 Effect of the Metal Gate Thickness on Interfacial Properties
In the previous section, MOS capacitor with W metal gate had a better interfacial
property compared to MOS capacitor with TaN metal gate electrode. In this section, the
effect of metal gate thickness on the interfacial property of MOS capacitors with W and
TaN/W metal gate electrodes will be discussed.
Figures 6.4 (a) and (b) show C-V characteristics for W(60 nm)/La2O3(4 nm)/Si and
W(8 nm)/La2O3(4 nm)/Si MOS capacitors, respectively. The capacitor with W(60 nm)
metal gate electrode shows a smaller hump in C-V curves compared to the capacitor
with thinner W metal gate, indicating that higher concentration of oxygen atoms are
contained in the thicker W gate electrode. This result implies that an appropriate
thickness for the W metal gate in respect with La2O3 thickness should be selected.
Figure 6.4 C-V characteristics for samples with (a) W(60 nm), and (b) W(8 nm) metal
gate electrodes.
(a) (b)
Cap
acit
ance
[F
/cm
2 ]
Experiment
Ideal
W(8 nm)/La2O3(4 nm)/Si
@100kHz
2.0
1.5
1.0
0.5
0
EOT = 1.54 nm
In-situ
PMA@800oC
-1.0 0-0.5
Gate voltage [V]
0.5 1.0
hump
Cap
acit
ance
[F
/cm
2 ]
Experiment
Ideal
ExperimentExperiment
IdealIdeal
W(8 nm)/La2O3(4 nm)/Si
@100kHz
2.0
1.5
1.0
0.5
0
EOT = 1.54 nm
In-situ
PMA@800oC
-1.0 0-0.5
Gate voltage [V]
0.5 1.0
hump
Cap
acit
ance
[F
/cm
2 ]
-1.0 0-0.5
Gate voltage [V]
W(60 nm)/La2O3(4 nm)/Si
0.5
@100kHz
1.0
2.0
1.5
1.0
0.5
0
EOT = 1.52 nm
In-situ
PMA@800oC
Experiment
Ideal
Cap
acit
ance
[F
/cm
2 ]
-1.0 0-0.5
Gate voltage [V]
W(60 nm)/La2O3(4 nm)/Si
0.5
@100kHz
1.0
2.0
1.5
1.0
0.5
0
EOT = 1.52 nm
In-situ
PMA@800oC
Experiment
Ideal
ExperimentExperiment
IdealIdeal
115
It is reported that oxygen atoms in the W gate electrode diffuse into the oxide layer,
and participate in silicate formation reaction at the La2O3 and Si-substrate interface [9].
XPS results for La2O3 gate dielectric layer with different physical thickness of W metal
gate show that the interfacial silicate formation is strongly affected by the thickness of
the metal gate [15].
Figure 6.5 shows C-V characteristics for La2O3 MOS capacitors with TaN/W
(2 ~ 20 nm) metal gate. Due to TaN capping of the W film, the amount of oxygen atoms
in the W metal layer is mainly determined by the thickness of the W metal layer. The
oxygen atoms initially absorbed into the W metal layer, start to diffuse into the gate
oxide layer during in the PMA process [3]. These oxygen atoms compensate oxygen
defects in the La2O3 layer and also promote the silicate reaction at the
Figure 6.5 W thickness dependence of C-V characteristics for TaN/W/La2O3/Si MOS
capacitors with in-situ PMA in F.G for 30 min at 800 oC.
Cap
acit
ance
[F
/cm
2 ]
-1.0 1.50-0.5
4.0
Gate voltage [V]
TaN(45 nm)/W/La2O3(2.5 nm)/Si
0.5
EOT = 1.1 nm@100kHz
1.0-1.5
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
W(2 nm)
W(3 nm)W(5 nm)W(20 nm)
EOT = 0.7 nm
EOT = 0.6 nm
EOT = 0.6 nm
In-situ
PMA@800oCCap
acit
ance
[F
/cm
2 ]
-1.0 1.50-0.5
4.0
Gate voltage [V]
TaN(45 nm)/W/La2O3(2.5 nm)/Si
0.5
EOT = 1.1 nm@100kHz
1.0-1.5
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
W(2 nm)
W(3 nm)W(5 nm)W(20 nm)
EOT = 0.7 nm
EOT = 0.6 nm
EOT = 0.6 nm
In-situ
PMA@800oC
116
La2O3/Si-substrate interface. For W metal gate thickness of less than 5 nm, the
capacitance decreases at a constant VFB. This means that all the diffused oxygen atoms
participate in silicate formation. Above a certain value of the thickness of W metal layer
(thicker than 5 nm), the capacitance is largely decreased while the VFB shifts to the
negative direction due to some amounts of the oxygen atoms contribute to the fixed
charges located at the interface and inside of the gate oxide layer. These results are
consistent with reports that a 10 nm thick W metal gate is sufficient to compensate
oxygen deficiency in the La2O3 layer [16].
Figure 6.6 shows the experimental and fitting results for VFB as a function of the
thickness of the W metal layer in TaN/W/La2O3/Si gate stacked MOS capacitors. The
experimentally observed VFB values largely shift to a negative direction with the
Figure 6.6 Flat band voltage as a function of the thickness of W metal gate in La2O3/Si
MOS capacitors with in-situ PMA in F.G for 30 min at 800 oC.
Thickness of W metal gate [nm]
20 704030 50 601050
Fla
t ba
nd v
olta
ge [
V]
-0.1
-0.15
-0.20
-0.25
-0.30
TaN(45 nm)/W/La2O3(2.5 nm)/Si
W(60 nm)/La2O3(2.5 nm)/Si
Experiment
Fitting
Thickness of W metal gate [nm]
20 704030 50 601050
Fla
t ba
nd v
olta
ge [
V]
-0.1
-0.15
-0.20
-0.25
-0.30
TaN(45 nm)/W/La2O3(2.5 nm)/Si
W(60 nm)/La2O3(2.5 nm)/Si
Thickness of W metal gate [nm]
20 704030 50 601050
Fla
t ba
nd v
olta
ge [
V]
-0.1
-0.15
-0.20
-0.25
-0.30
TaN(45 nm)/W/La2O3(2.5 nm)/Si
W(60 nm)/La2O3(2.5 nm)/Si
Experiment
Fitting
Experiment
Fitting
117
increasing of the W metal layer thickness. The experimental results are well fitted to the
exponential decay curve of the VFB dependence on the W layer thickness. This indicates
that the concentration of the oxygen atoms inside the gate oxide layer is exponentially
decayed [17].
6.4 Summary
The impacts of metal gate material and the physical thickness of the metal gate on the
interfacial properties of La2O3 gate stacked MOS capacitors were discussed. It was
shown that by a combination of TaN (as oxygen free metal) and W (as metal containing
oxygen) silicate reaction at the substrate interface can be controlled. Balancing the
thickness of each metal is a key factor for preventing excess or deficiency of oxygen
atoms within the gate stack which would lead to degradation in device characteristics.
118
References
[1] Robertson J, High dielectric constant gate oxides for metal oxide Si transistors, Rep.
Prog. Phys., 69(2), 327(2006).
[2] Kim Y H, Lee C H, Jeon T S, Bai W P, Choi C H, Lee S J, Xinjian L, Clarks R,
Roberts D, and Kwong D L, High quality CVD TaN gate electrode for Sub-100 nm
MOS devices, IEEE IEDM Tech. Dig., 667(2001).
[3] Buchanan D A, McFeely F R, and Yurkas J J, Fabrication of midgap metal gates
compatible with ultrathin dielectrics, Appl. Phys. Lett., 73(12), 1676(1998).
[4] Shang H, White M H, Guarini K W, Cartier E, and Solomon P, Characterization of
midgap tungsten gate MOSFETs, DRC Conf. Dig., 73(2001).
[5] Iwata S, Yamamoto N, Kobayashi N, Terada T, and Mizutani T, A new tungsten gate
process for VLSI applications, IEEE Trans. Electron Devices., 31(9), 1174(1984).
[6] Shimuzu H, Kita K, Kyuno K, and Toriumi A, Kinetic model of Si oxidation at
HfO2/Si interface with post deposition annealing, Jpn. J. Appl. Phys., 44(8),
6135(2005).
[7] Preisler E J, Guha S, Copel M, Bojarczuk N A, Reuter M C, and Gusev E,
Interfacial oxide formation from intrinsic oxygen in W-HfO2 gated silicon
field-effect transistors, Appl. Phys. Lett., 85(25), 6230(2004).
119
[8] Kakushima K, Tachi K, Adachi M, Okamoto K, Sato S, Song J, Kawanago T,
Ahmet P, Tsutsui K, Sugii N, Hattori T, and Iwai H, Interface and electrical
properties of La-silicate for direct contact of high-k with silicon, Solid-State
Electron., 54(7), 715(2010).
[9] Kaushik V S, O’sullivan B J, Pourtois G, Hoornick N V, Delabie A, Elshocht S V,
Deweerd W, Schram T, Pantisano L, Rohr E, Ragnarsson L A, De Gendt S D, and
Heyns M, Estimation of fixed charge densities in hafnium-silicate gate dielectrics,
IEEE Tran. Electron Devices., 53(10), 2627(2006).
[10] Deal B E, Sklar M, Grove A S, and Snow E H, Characteristics of the surface-state
charge (Qss) of thermally oxidized silicon, J. Electrochem. Soc., 114(3), 266(1967).
[11] Shiraishi K, Yamada K, Torii K, Akasaka Y, Nakajima K, Konno M, Chikyow T,
Kitajima H, and Arikado T, Oxygen vacancy induced substantial threshold voltage
shifts in the Hf-based high-k MISFET with p+ poly-Si gates-A theoretical
approach, Jpn. J. Appl. Phys., 43(11A), L1413(2004).
[12] Kouda M, Kawanago T, Ahmet P, Natori K, Hattori T, Iwai H, Kakushima K,
Nishiyama A, Sugii N, and Tsutsui K, Interface and electrical properties of Tm2O3
gate dielectrics for gate oxide scaling in MOS devices, J. Vac. Sci. Technol. B.,
29(6), 062202-1(2011).
120
[13] Kakushima K, Koyanagi T, Tachi K, Song J, Ahmet P, Tsutsui K, Sugii N, Hattori T,
and Iwai H, Characterization of flatband voltage roll-off and roll-up behavior in
La2O3/silicate gate dielectrics, Solid-State Electron., 54(7), 720(2010).
[14] Kakushima K, Tachi K, Song J, Sato S, Nohira H, Ikenaga E, Ahmet P, Tsutsui K,
Sugii N, Hattori T, and Iwai H, Comprehensive X-ray photoelectron spectroscopy
study on compositional gradient lanthanum silicate film, J. Appl. Phys., 106(12),
124903(2009).
[15] Kitayama D, Kubota T, Koyanagi T, Kakushima K, Ahmet P, Tsutsui K,
Nishiyama A, Sugii N, Natori K, Hattori T, and Iwai H, Silicate reaction control at
Lanthanum oxide and silicon interface for equivalent oxide thickness of 0.5 nm:
adjustment of amount of residual oxygen atoms in metal layer, Jpn. J. Appl. Phys.,
50(10), 10PA05-1(2011).
[16] Kawanago T, Lee Y, Kakushima K, Ahmet P, Tsutsui K, Nishiyama A, Sugii N,
Natori K, Hattori T, and Iwai H, Optimized oxygen annealing process for Vth
tuning of p-MOSFET with high-k/metal gate stacks, IEEE ESSDERC, 301(2010).
[17] Itoh H, Nagamine M, Satake H, and Toriumi A, A study of atomically-flat SiO2/Si
interface formation mechanism, based on the radical oxidation kinetics,
Microelectron. Eng., 48(1-4), 71(1999).
121
Chapter 7 Effective Mobility Analyses Based on Remote
Coulomb Scattering Model
In this chapter, the analysis of effective mobility for thin La2O3 gate MOSFETs is
described.
7.1 Introduction
Mobility degradation is one of the main concerns in MOSFETs with high-k gate stacks
[1-6]. A number of models were proposed for clarify the mechanism of mobility
degradation in the ultrathin gate oxide MOSFETs [7-15], and these models suggested
that remote scattering mechanisms such as RCS [8-11], RSR [12-15], and RPS [16]
contribute to the mobility degradation in ultrathin gate oxide MOSFETs. At the room
temperature, effect of RPS on the electron mobility can not be reduced due to the
intrinsic characteristics of the high-k gate dielectrics. Hence, RCS and RSR scattering
are considered can be reduced by optimizing device fabrication process. Effects of RCS
and RSR on the electron mobility in the channel of MOSFETs can be separated by their
122
low and high electric field dependency, respectively [17-18]. In this study, the effect of
RCS on the electron mobility in La2O3 gate stacked MOSFETs was studied.
For ultrathin MOSFETs that La2O3 direct contacting on Si-substrate, Kakushima et al.
have reported that for EOT thicker than 1.3 nm, reduction of electron mobility value can
be considered relatively small and the mobility reduction becomes more significant
when EOT is smaller than 1.3 nm. This degradation can be explained by an additional
scattering from RCC due to the diffusion of metal atoms from gate electrode into the
La2O3 dielectric layer [19]. In the following paragraphs, the effect of charges located
near W/La2O3 interface on the electron mobility in the channel of MOSFETs was
discussed. Remote scattering from the Coulomb charges was evaluated on La2O3-based
MOSFETs with EOT scaled from 1.2 to 0.8 nm.
7.2 Remote Charge Scattering Model
In this paragraph, RCS Model is briefly described.
The electron transport in an n-type inversion layer formed at a Si (100) surface of a
MOSFET with structure of W/La2O3/Si (as shown in Figure 7.1) was considered. Based
on the previous work [19], a silicate IL formation between La2O3 layer and Si-substrate
was suggested. RCC were assumed mainly located at near the interfaces of the W/La2O3
123
Figure 7.1 Schematic cross-section of La2O3 gate stacked MOSFET.
W
La2O3
La-silicate
Si-substrate
silicate= 8
= 23.4La2O3
W
La2O3
Si-substrate
60 nm
1.5 ~ 4 nm
Before annealing
After annealing
W
La2O3
La-silicate
Si-substrate
silicate= 8
= 23.4La2O3
W
La2O3
La-silicate
Si-substrate
silicate= 8
= 23.4La2O3 = 23.4La2O3
W
La2O3
Si-substrate
60 nm
1.5 ~ 4 nm
W
La2O3
Si-substrate
60 nm
1.5 ~ 4 nm
Before annealing
After annealing
(a) (b)
and La2O3/silicate layers, and the charge distribution follows a delta function. The
electrons in the Si inversion layer were considered as a two-dimensional electron gas.
RCS can be calculated from the relaxation time approximation, as follows:
tRCS /RCS
me , (7.1)
where tm is the transverse effective mass of the electron and RCS is the averaged
relaxation time over the kinetic energy of the electron. The relaxation time can be
solved from a perturbation potential by a method proposed by Saito et al [10]. Using
Fermi’s golden rule, RCS can be obtained by the following expression:
124
k
k
kEfkE
kEfkE
)](/)[(
)](/[)(
RCS
RCS
, (7.2)
where ),,( F TEEff is the Fermi-Dirac distribution function, and FE is Fermi
energy of the electron. The relaxation time is simplified as follows:
2
0
2
00RCS03
t
RCS
)cos1()()(2
)(
1zAzNdzd
mq
, (7.3)
where is a scattering potential averaged over the inversion charge distribution.
)( 0zAq is the Fourier-Bessel transformation of the scattering potential );,( 0zzr . In
the calculation of the perturbation potential, the screening effect was included using
Thomas-Fermi approximation with considering the quantum fluctuation as derived
by Pirovano et al. [20-21].
In the numerical calculation, the transverse and longitudinal effective mass of the
electrons were take as 916.0/ 0t mm , and 2.0/ 0l mm , respectively. The dielectric
constants of the La2O3 layer, the interfacial silicate layer, and Si-substrate were take as
4.2332OLa , 8Silicate and 7.11Si , respectively. The EOT value was considered as
ranges of 0.7 ~ 1.5 nm.
125
Figure 7.2 shows that the numerically (Appendix) calculated RCS in the channel of
La2O3 gate stacked MOSFETs decreases with EOT. This result implies that the RCS
potential increases as the location of RCC approaching closer to the inversion layer.
7.3 RCS Induced Mobility Degradation Mechanism
In this paragraph, mobility degradation in the La2O3 gate stacked MOSFETs was
discussed.
1) Experimental details
nMOS capacitors and nMOSFETs with W/La2O3/Si structure were fabricated on the
(1 0 0)-oriented Si-substrates with doping densities of 3 1015 cm-3 and 3 1016 cm-3,
respectively. The wafers were cleaned by sulfuric acid hydrogen peroxide mixture
(SPM) and HF (1%) solution. After deposition of the La2O3 film by E-beam deposition,
Figure 7.2 Calculated RCS-limited electron mobility versus inversion charge density.
Ns [1013cm-2]
100
10
1
0
RC
S m
obil
ity[
cm2 /
Vs]
10000
1000
0.60.50.1 0.40.30.2
EOT=0.7 nm
EOT=0.9 nm
EOT=1.2 nm
EOT=1.5 nm
NRCC =2.31013 cm-2
Ns [1013cm-2]
100
10
1
0
RC
S m
obil
ity[
cm2 /
Vs]
10000
1000
0.60.50.1 0.40.30.2
Ns [1013cm-2]
100
10
1
0
RC
S m
obil
ity[
cm2 /
Vs]
10000
1000
0.60.50.1 0.40.30.2
EOT=0.7 nm
EOT=0.9 nm
EOT=1.2 nm
EOT=1.5 nm
EOT=0.7 nm
EOT=0.9 nm
EOT=1.2 nm
EOT=1.5 nm
NRCC =2.31013 cm-2
126
the samples were transferred in-situ into a high vacuum chamber and a 60 nm thick W
film was deposited by RF-sputtering method. Then, the samples were transferred into a
thermal processing chamber and PMA at a temperature of 800 oC for 30 min was
carried out in F.G ambient. In order to avoid absorptions of oxygen and moisture from
the air, all the fabrication and annealing processes described above were performed in a
multi-chamber system, without exposing the samples to the air. After patterning the gate
electrodes by RIE, Al thin film was thermally evaporated to form source/drain and
backside electrode contacts. In Figure 7.1, a Schematic structure of the samples is
shown.
Capacitance-voltage (C-V) and current-voltage (I-V) measurements have been
performed by Agilent E4980A precision LCR meter and Agilent 4156C semiconductor
parameter analyzer, respectively. The capacitance was measured in the frequency range
from 1 kHz to 1 MHz, and the area of the capacitors was 10 × 10 μm2. EOT was
extracted from the C-V data using the NCSU CVC modeling program [22].
Conductance measurements were done in frequency range from 100 Hz to 2 MHz, and
the area of the capacitors was 50 × 50 μm2. Effective electron mobility was extracted
from the data of Id -Vd and split C-V measurements. Both the gate length and gate width
127
of the measured MOSFETs were 10 μm. Additional scattering mobility was evaluated
using Matthiessen’s rule.
2) Observation of mobility degradation
Figure 7.3(a) shows typical 100 kHz C-V curves measured for the fabricated MOS
capacitors with EOT down to 0.8 nm. Small humps are observed (Figure 7. 3(b)) near
the VFB at frequencies of 1 kHz and 10 kHz. These humps indicate the existence of
interfacial state density at La-silicate/Si-substrate interface [23].
Figure 7.4 shows EOT dependence of MOS capacitors on the physical thickness of
deposited La2O3 gate dielectrics. Considering the formation of La-silicate at the
Figure 7.3 Measured C-V characteristics for the fabricated MOS capacitors after PMA
800 oC in F.G for 30 min; (a) EOT dependence of capacitance value; (b) Capacitance
dependence on measurement frequency; in both figures, the solid lines refer to the ideal
curve and the symbols refer to measurement data.
100 kHz
-1.0
PMA@800oC in F.G 30min
EOT= 0.8 nm
Ideal
EOT= 1.1 nm
EOT= 1.0 nm
EOT= 1.2 nm
1.00.50-0.5Gate voltage [V]
0.5
1.0
1.5
2.0
2.5
3.0
0
3.5
4.0
Cap
acit
ance
[F
/cm
2 ]
100 kHz
-1.0
PMA@800oC in F.G 30min
EOT= 0.8 nm
Ideal
EOT= 1.1 nm
EOT= 1.0 nm
EOT= 1.2 nm
EOT= 0.8 nm
Ideal
EOT= 1.1 nm
EOT= 1.0 nm
EOT= 1.2 nm
1.00.50-0.5Gate voltage [V]
0.5
1.0
1.5
2.0
2.5
3.0
0
3.5
4.0
Cap
acit
ance
[F
/cm
2 ]
-0.5-1.0 0 0.5Gate voltage [V]
2
1
0.5
0
Cap
acit
ance
[u
F/c
m2 ]
1.5
2.5
Ideal
10 kHz
1 kHz
1 MHz
100 kHz
EOT=1.0nm
PMA@800oC in F.G 30min
-0.5-1.0 0 0.5Gate voltage [V]
2
1
0.5
0
Cap
acit
ance
[u
F/c
m2 ]
1.5
2.5
Ideal
10 kHz
1 kHz
1 MHz
100 kHz
IdealIdeal
10 kHz10 kHz
1 kHz1 kHz
1 MHz1 MHz
100 kHz100 kHz
EOT=1.0nm
PMA@800oC in F.G 30min
a) b)
128
oxide/Si-substrate interface [24], the total EOT of the capacitor is determined by the
sum of the thicknesses of the La-silicate and La2O3 layers.
silicate-Laoxide-La EOTEOTEOT . (7.4)
Where EOTLa-oxide, and EOTLa-silicate are equivalent oxide thicknesses for La2O3 and
La-silicate layers. The thickness of La-silicate layer formed at La2O3/Si-substrate
interface can be extracted from the relation between the estimated EOT and the
deposited physical thickness of La2O3 dielectric layer. A best fit (with standard
deviation of 0.02 nm) leads to the value of 1.55 nm for silicate IL. The formation of
silicate IL at the interface of La2O3/Si-substrate during the thermal annealing process
was confirmed by XPS analyses [24]. The fitting also gives the values of dielectric
constants La-silicate = 8.1 for silicate IL, and La-oxide = 22.3 for the La2O3 layer. These
obtained values are well agreed with the reported k values that are calculated from the
oxide thickness determined by TEM images [19, 25]. Assuming the silictae IL thickness
at the interface depends only on the annealing temperature, the increment of the
measured EOT can be explained simply by the increment in the thickness of La2O3
layer.
129
Figure 7.5(a) shows the Id -Vd characteristics of the fabricated
W/La2O3/Si gate stacked MOSFETs. The gate-to-channel capacitance has no
Figure 7.5 The measured electrical characterizations of W/La2O3 gate stacked MOSFETs
annealed at 800 oC in F.G for 30 minutes; (a) Id -Vd characteristics, and (b) Gate-to-channel
(Cgc), and gate-to-body (Cgb) capacitance characteristics.
a) b)
-0.5-2.0 0 1.0Gate voltage [V]
2
1
0.5
0
Cap
acit
ance
[u
F/c
m2 ]
1.5
2.5
EOT=1.1nm
PMA@800oC in F.G 30min
Cgc
Cgb
L/W = 10/10 m
@100 kHz
0.5-1.5 -1.0 -0.5-2.0 0 1.0Gate voltage [V]
2
1
0.5
0
Cap
acit
ance
[u
F/c
m2 ]
1.5
2.5
EOT=1.1nm
PMA@800oC in F.G 30min
Cgc
Cgb
L/W = 10/10 m
@100 kHz
0.5-1.5 -1.0Drain voltage [V]
Vg = 0.8 VVg = 1.0 V
Vg = 0.4 V
Vg = 0.6 V
Vg = 0.2 VVg = 0.0 V
0.60.0 1.0
Dra
in c
urr
ent
[A]
3.0E-4L/W = 10/10 m
0.2 0.4 0.8
2.5E-4
2.0E-4
1.5E-4
1.0E-4
0.5E-4
0.0E0
Drain voltage [V]
Vg = 0.8 VVg = 1.0 V
Vg = 0.4 V
Vg = 0.6 V
Vg = 0.2 VVg = 0.0 V
Vg = 0.8 VVg = 1.0 V
Vg = 0.4 V
Vg = 0.6 V
Vg = 0.2 VVg = 0.0 V
0.60.0 1.0
Dra
in c
urr
ent
[A]
3.0E-4L/W = 10/10 m
0.2 0.4 0.8
2.5E-4
2.0E-4
1.5E-4
1.0E-4
0.5E-4
0.0E0
Figure 7.4 EOT versus the thickness of the deposited La2O3 film. The closed symbols
correspond to the total EOT extracted from the C-V measurement; the solid line refers to
the fitting curve, considering the formation of interfacial silicate layer (TLa-silicate) within
La2O3 layer (TLa-oxide).
3.51.5 2.0 4.0Deposited physical thickness [nm]
1.40
1.20
1.00
0.80
EO
T [
nm
]
1.00.60
2.5 3.0
measurement
fitting
3.51.5 2.0 4.0Deposited physical thickness [nm]
1.40
1.20
1.00
0.80
EO
T [
nm
]
1.00.60
2.5 3.0
measurement
fitting
measurementmeasurement
fitting
130
hysteresis, while the gate-to-body capacitance shows a small hysteresis, as shown in
Figure 7.5(b). These results suggest that a fairly nice La-silicate/Si-substrate interface is
achieved with a negligible amount of local trap states existing near the valance band of
the silicon.
Figure 7.6(a) shows EOT dependency of the measured eff for the fabricated
MOSFETs. The eff decreases with the decrement of EOT. By using Matthiessens’s rule,
an additional scattering-limited mobility (add) factor was extracted from eff of
MOSFETs with EOT of 1.2 and 0.8 nm. As shown in Figure 7.6(b), a relation of
add Ns+0.60 was observed in the low electric field region (Ns < 5.5 1013 cm-2). The
a) b)
0 0.4 0.8 1.2 1.6Ns [ 1013cm-2]
1.2 nm
0.8 nm
1.1 nm1.0 nm
200
150
50
0
Eff
ecti
ve m
obil
ity
[cm
2 /V
s]
100
PMA@800oC
L/W = 10/10 m
T = 300 K
Nsub = 31016 cm-3
0 0.4 0.8 1.2 1.6Ns [ 1013cm-2]
1.2 nm
0.8 nm
1.1 nm1.0 nm
1.2 nm1.2 nm
0.8 nm0.8 nm
1.1 nm1.1 nm1.0 nm1.0 nm
200
150
50
0
Eff
ecti
ve m
obil
ity
[cm
2 /V
s]
100
PMA@800oC
L/W = 10/10 m
T = 300 K
Nsub = 31016 cm-3
0.1 1.0Ns [ 1013cm-2]
EOT = 1.2 nm
add
1000
200
100
Eff
ecti
ve m
obil
ity
[cm
2 /V
s]400
PMA@800oC
L/W = 10/10 m
T = 300 K
Nsub = 31016 cm-3
EOT = 0.8 nm
Ns0.6
10
600
800
0.1 1.0Ns [ 1013cm-2]
EOT = 1.2 nm
add
1000
200
100
Eff
ecti
ve m
obil
ity
[cm
2 /V
s]400
PMA@800oC
L/W = 10/10 m
T = 300 K
Nsub = 31016 cm-3
EOT = 0.8 nm
Ns0.6
10
600
800
Figure 7.6 Mobility versus inversion layer charge density; (a) measured effective electron
mobility, and (b) extracted additional scattering-limited electron mobility for samples with
PMA 800 oC in F.G for 30 min; the measured device size is L/W 10/10 m and measurement
frequency is 100 kHz.
131
power dependency of add on Ns, add Ns+0.60, suggests that the RCS is the main cause
for the mobility degradation [18].
3) Proposed model for explaining mobility degradation by RCS
The obtained eff values at the effective electric field of 0.3 MV/cm for MOSFETs with
EOT from 1.2 to 0.8 nm are plotted against the thickness of La2O3 layer in Figure 7.7.
The decrease in eff value with the thickness of La2O3 layer can be attributed to at least
two kinds of RCC: one originating from La2O3/La-silicate interface and the other from
W/La2O3 interface.
Eeff = 0.3MV/cm
Thickness of the La2O3 layer [nm]
120
800
Eff
ecti
ve m
obil
ity[
cm2 /
Vs]
200
160
3.22.41.60.8
Equivalent oxide thickness [nm]0.6 1.41.21.00.8
experiment
model
7.91012 cm-2
Intensity of RCS
Tsilicate
TLa O2 3
Si
5.41012 cm-2
z
0
Eeff = 0.3MV/cm
Thickness of the La2O3 layer [nm]
120
800
Eff
ecti
ve m
obil
ity[
cm2 /
Vs]
200
160
3.22.41.60.8
Equivalent oxide thickness [nm]0.6 1.41.21.00.8
experiment
model
experiment
model
7.91012 cm-2
Intensity of RCS
Tsilicate
TLa O2 3
Si
5.41012 cm-2
z
0 7.91012 cm-2
Intensity of RCS
Tsilicate
TLa O2 3
Si
5.41012 cm-2
z
0
Tsilicate
TLa O2 3TLa O2 3
Si
5.41012 cm-2
z
0
Figure 7.7 Mobility versus the thickness of La2O3 layer. TLa-oxide is extracted from the total
EOT by considering the formation of La-silicate layer. The closed symbols correspond to
the measurement data of eff at Eeff = 0.3 MV/cm. The solid line refers to theoretical
modeling.
132
Figure 7.8 shows the experimentally observed conductance spectra for the fabricated
MOS capacitors. The conductance peaks are roughly constant regardless of both EOT
and the electron energy. These conductance peaks can be assigned to RCC centers due
to slow traps located at the La2O3/La-silicate interface [26]. This implies that an
approximately same amount of RCC is distributed at the La2O3/La-silicate interface
despite the changes in the total EOT. Therefore, the observed mobility degradation at
smaller EOT can be considered as the result of scattering from the RCC located near the
W/La2O3 interface. The small negative shift of VFB with the increment of EOT in Figure
7.3(a) indicates a small reduction of the negative charges. This can be understood due to
the increase of the total positive charges as a result of a thicker La2O3 layer. These
positive charges are generally attributed to the metal induced [18, 27] and oxygen
defects [28] in the gate oxide layer. Given the facts above, it is reasonable to assume
that, approximately same amount of RCC is distributed near to the W/La2O3 interface.
Therefore, the relation between eff and the thickness of the La2O3 layer can be modeled
using RCS potential intensity at MOSFET channel with different EOT [16]. RCS
potential decreases by the )2exp( oxFTk factor, with increasing oxide thickness.
Where kF is the Fermi wave number of the channel carriers and Tox is the thickness of
the oxide layer. The measured electron mobility, can be expressed as [16]:
133
other
oxFR
Tk
1)2exp(
11 , (7.5)
where R is the pre-factor mobility representing the scattering from a high-k dielectric,
and other is the mobility in the gate-oxide from other contributions. The inset in
Figure 7.7 shows an exponential decay trend of RCS potential intensity for RCC located
at the La2O3/silicate interface and near W/La2O3 interface. The RCC distributed at the
La2O3/silicate interface with the density of 5.4 1012 cm-2 and near W/La2O3 interface
with the density of 7.9 1012 cm-2 results the best calculated fit of eff to the
experimental value, as shown in Figure 7.7 (solid line). It should be noted that the
103 104 105 106
Angular frequency [rad/s]107
1.2
0.8
Gp/
[F
/cm
2 ]
0.4
1.6
2
0
-0.8eV
-0.5eV -0.7eV-0.6eV EOT=0.8 nm
EOT=1.2 nm
103 104 105 106
Angular frequency [rad/s]107
1.2
0.8
Gp/
[F
/cm
2 ]
0.4
1.6
2
0
-0.8eV
-0.5eV -0.7eV-0.6eV EOT=0.8 nm
EOT=1.2 nm
Figure 7.8 Conductance spectra for W/La2O3/Si MOS capacitors with PMA 800 oC in F.G
for 30 min. The dark and light symbols correspond to samples with EOT = 0.8 nm and
EOT = 1.2 nm, respectively. The conductance spectra were measured with E-Ei range from
-0.5 to -0.8 eV.
134
assumed value of charge density located at the La2O3/La-silicate interface is consistent
with the experimental value of slow trap density extracted by conductance method [26].
The agreement between the calculated and experimentally obtained mobility suggests
that the RCC located near to the W/La2O3 interface plays an important role in causing
the mobility degradation in MOSFETs with thin La2O3 dielectrics. Our result suggest
that in order to improve the mobility in MOSFETs with thin La2O3 gate dielectrics, it is
necessary to reduce the RCS potential by reducing the amount of RCC located near
W/La2O3 interface. This result is consistent with the result reported by Kitayama et al.
[29], where a thin Si layer was inserted at the interface between the W and La2O3 to
reduce the positive fixed charges which induced by the metal electrode, and
consequently an improvement in the electron mobility was observed.
7.4 Suggestion to Improve Mobility
Mobility degradation in W/La2O3/Si MOSFETs with EOT from 1.2 to 0.8 nm was
studied. The obtained results show that RCC located near W/La2O3 interface has a
dominant role in the mobility degradation as EOT scaled smaller than 1 nm. Our results
suggest that in order to achieve a higher mobility in the MOSFETs with thin La2O3 gate
dielectrics, it is necessary to reduce the RCC located near W/La2O3 interface.
135
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141
Chapter 8 Summary
In this chapter, summaries of all chapters and future prospects of this thesis are
described.
8.1 Summaries of This Thesis
In this thesis, interfacial properties of La2O3 gate dielectrics, and effect of RCS on
electron mobility in the La2O3 gate stacked MOSFETs are experimentally investigated.
In the first chapter, high-k dielectrics are introduced and current status of high-k
dielectrics in particular La2O3, are summarized. In the second chapter, fabrication
process for MOS capacitors and MOSFETs with La2O3 gate stacks and electrical
characterization methods are described. Below are the summaries of the remaining
chapters:
a) La-silicate interfacial layer formation (Chapter 3)
In chapter 3, realization of direct high-k contact with Si is described. Effect of PMA on
the silicate formation mechanism is also investigated. The main findings and
contributions of this work are summarized as below:
142
La2O3 is a suitable candidate to achieve direct high-k contact with Si because of its
material nature to form a La-silicate IL at La2O3/Si-substrate interface. Both TEM
image and XPS spectra confirm La-silicate IL formation. Measurement and calculation
results show that by increasing of the annealing temperature EOT becomes larger due to
the formation of La-silicate IL. It was also observed from FTIR spectra that at PMA
temperatures of 600 oC and higher, stretch of La-Si-O bonds within the silicate structure
start to saturate. This indicates a complete transformation of La2O3 to La-silicate.
b) Interface and oxide trap states estimation (Chapter 4)
In chapter 4, the electrical characteristics of MOS devices with La2O3 as gate dielectrics
are investigated. Based on the observed two distinct peaks in the conductance spectra
for the La2O3 gate dielectrics, a novel interpretation for conductance method to evaluate
interface and oxide trap state density has been proposed. The observed result assigned
that the amount of the slow trap centers located at the La2O3/La-silicate interface can
not be reduced by PMA in the F.G ambient. The estimated value of the order of
1013 cm-2/eV for the slow traps at the La2O3/La-silicate interface indicates that a
W/La-silicate/Si structure is preferable for fabrication of devices with low interfacial
traps.
c) Interfacial properties and effect of annealing (Chapter 5)
143
In chapter 5, process-based approach for interfacial properties is described. Effect of
PMA temperature on the electrical characteristics of La2O3 gate stack capacitors was
investigated. The result shows that in-situ PMA is an effective method in order to
suppress EOT increase due to thermal treatment. High temperature PMA of 800 oC or
more was found to be important for improving the interfacial properties of La2O3 gate
stacked MOS capacitors.
d) Impact of metal gate on interfacial properties (Chapter 6)
In chapter 6, the impact of the metal gate material and physical thickness of the metal
gate on the interfacial properties of La2O3 MOS capacitors by reducing the amount of
oxygen atoms in the metal gate were discussed. The result shows that the silicate
reaction at the substrate interface can be controlled by a combination of TaN (as oxygen
free metal) and W (as metal containing oxygen). Balancing the thickness of each metal
is a key factor for preventing excess or deficiency of oxygen within the gate stack which
would lead to degraded device characteristics.
e) Effective mobility analyses based on RCS model (Chapter 7)
In chapter 7, mobility degradation in W/La2O3/Si MOSFETs with EOT from 1.2 to
0.8 nm was studied. The obtained results show that RCS from Coulomb charges located
near the metal gate/high-k interface has a dominant role in the mobility degradation as
144
EOT scaled down less than 1 nm. Our result suggests that in order to achieve a higher
mobility in the MOSFETs with thin La2O3 gate dielectrics, it is necessary to prevent or
reduce the amount of RCC located near W/La2O3 interface by reducing the RCS
potential.
8.2 Recommendations for Further Study
Based on this study, further study of high-k/metal gate stacks with La-silicate is
described. Interfacial properties improvement and mobility degradation are two of the
main concerns in performance improvement of the downscaled devices. In this work,
La-silicate IL formation and its effects on interfacial properties of La2O3 gate dielectrics
were studied. The silicate reaction is basically triggered by the presence of oxygen
atoms. The controlling of the amount of oxygen atoms corresponds to the controlling of
silicate reaction. Further EOT scaling may be achieved by systematic study including
spectral analysis for the chemical bonds at the interface and in the gate oxide. The
amount of oxygen atoms in the gate stacks should be investigated by spectral analyses.
The MOSFET performance can be improved by preventing metal diffusion and
reducing oxygen defects. As previously mentioned in this study, RCS from Coulomb
charges within high-k layer near to the metal gate/high-k interface become an important
145
factor in mobility degradation for ultrathin MOSFETs with high-k dielectrics. Further
studying of RSR scattering is also necessary to improve device performance. Especially,
effects of these two remote scattering mechanisms are expected to reduce by optimizing
device fabrication process.
In conclusion, this thesis provides useful information and further understanding for
high-k/metal gate system. These studies are also expected to contribute to the future
progress of LSIs.
146
Publications and Presentations
a) Publications (3 papers accepted for publication)
1) M. Mamatrishat, T. Kubota, T. Seki, K. Kakushima, P. Ahmet, K. Tsutsui, Y. Kataoka,
A. Nishiyama, N. Sugii, K. Natori, T. Hattori, and H. Iwai, Oxide and interface trap
state densities estimation in ultrathin W/La2O3/Si MOS capacitors (accepted for
publication in Microelectronic reliability, reference number is MR10323 with DOI:
10.1016/j.microrel.2011.12.025)
2) M. Mamatrishat, M. Kouda, T. Kawanago, K. Kakushima, P. Ahmet, K. Tsutsui, Y.
Kataoka, A. Nishiyama, N. Sugii, K. Natori, T. Hattori, and H. Iwai, Effect of remote
Coulomb scattering on electron mobility in La2O3 gate stacked MOSFETs,
Semiconductor Science and Technology, 27(4), 045014(2012).
3) M. Mamatrishat, M. Kouda, K. Kakushima, H. Nohira, P. Ahmet, Y. Kataoka, A.
Nishiyama, K. Tsutsui, N. Sugii, K. Natori, T. Hattori, and H. Iwai, Valance number
transition and silicate formation of cerium oxide on Si (100), Vacuum, 86(10),
1513(2012).
b) International Presentations (2 oral presentations)
1) M. Mamatrishat, M. Kouda, T. Kawanago, K. Kakushima, P. Ahmet, A. Aierken, K.
147
Tsutsui, A. Nishiyama, N. Sugii, K. Natori, and H. Iwai, Effect of
remote-surface-roughness scattering on electron mobility in MOSFETs with high-k
dielectrics, ECS transaction, 33(3), 249-255(2010).
2) M. Mamatrishat, M. Kouda, K. Kakushima, P. Ahmet, K. Tsutsui, N. Sugii, K.
Natori, T. Hattori, and H. Iwai, Analysis of remote Coulomb scattering limited
mobility in MOSFETs with CeO2/ La2O3, ECS transaction, 25(7), 253-257(2009).
c) Domestic Presentations (3 oral presentations)
1) M. Mamatrishat, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii,
K. Natori, and H. Iwai, Electron mobility degradation in ultrathin high-k gate
stacked MOSFETs, 58th Japan Society of Applied Physics (JSAP), Japan, March,
2011.
2) M. Mamatrishat, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii,
K. Natori, T. Hattori, and H. Iwai, Dependence of electron mobility of high-k gate
stacked MOSFETs on remote interface roughness scattering, 71th Japan Society of
Applied Physics (JSAP), Japan, Sept. 2010.
3) M. Mamatrishat, M. Kouda, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama,
N. Sugii, K. Natori, T. Hattori, and H. Iwai, Remote Coulomb scattering limited
mobility in MOSFET with CeO2/La2O3 gate stacks, 70th Japan Society of Applied
148
Physics (JSAP), Japan, Sept. 2009.
d) Domestic Presentations (5 posters)
1) M. Mamatrishat, T. Seki, K. Kakushima, P. Ahmet, Y. Kataoka, A. Nishiyama, N.
Sugii, K. Tsutsui, K. Natori, T. Hattori, and H. Iwai, Evaluation of interfacial
properties of direct contacted La2O3 gate dielectrics, Symposium on Innovative
platform for education and research, TIT, Japan, 2012/02/28.
2) M. Mamatrishat, T. Seki, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N.
Sugii, K. Natori, T. Hattori, and H. Iwai, Evaluation of oxide traps in La based
oxides for direct high-k/Si capacitor, G-COE PICE International Symposium and
IEEE EDS mini-colloquium on Advanced Hybrid Nano Devices: Prospects by
Worlds Leading Scientists, TIT, Japan, 2011/10/04-10/05.
3) M. Mamatrishat, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K.
Natori, and H. Iwai, Remote-surface-roughness scattering limited electron mobility
in ultrathin high-k gate stacked MOSFETs, Taiwan-Japan workshop on Nano
Devices, TIT, Japan, 2011/03/03.
4) M. Mamatrishat, K. Kakushima, P. Ahmet, K. Tsutsui, N. Sugii, K. Natori, T.
Hattori, and H. Iwai, Remote Coulomb and roughness scatterings in gate oxide
scaling, Symposium on Innovative platform for education and research, TIT, Japan,
149
2010/12/14.
5) M. Mamatrishat, M. Kouda, K. Kakushima, P. Ahmet, K. Tsutsui, N. Sugii, K.
Natori, T. Hattori, and H. Iwai, Study on remote Coulomb scattering limited
mobility in MOSFETs with CeO2/La2O3 gate stacks, G-COE PICE International
Symposium on Silicon Nano Devices in 2030-Prospects by Worlds Leading
Scientists, TIT, 2009/10/13~10/14.
e) Other contributions (3 international and 4 domestic conferences)
1) Ahmet P, Kitayama D, Kaneda T, Suzuki T, Koyanagi T, Kouda M, Mamatrishat M,
Kawanago T, Kakushima K, Tsutsui K, Nishiyama A, Sugii N, Natori K, Hattori T,
and Iwai H, TiN/Metal/La2O3/Si High-k gate stack for EOT below 0.5 nm, ECS
trans. 34(1), 99(2011).
2) Kakushima K, Koyanagi T, Kitayama D, Kouda M, Song J, Kawanago T,
Mamatrishat M, Tachi K, Bera M K, Ahmet P, Nohira H, Tsutsui K, Nishiyama A,
Sugii N, Natori K, Hattori T, Yamada K, and Iwai H, Direct contact of high-k/Si
gate stack for EOT below 0.7 nm using LaCe-silicate layer with VFB controllability,
Dig. Tech. Pap.-Symp. VLSI Technol., 69(2010).
3) Ahmet P, Kitayama D, Kaneda T, Suzuki T, Koyanagi T, Kouda M, Mamatrishat M,
Kawanago T, Kakushima K, and Iwai H, Scaling of EOT beyond 0.5 nm, IEEE
150
ICSICT, 994(2010).
4) Kouda M, Mamatrishat M, Kakushima K, Nohira H, Ahmet P, Tsutsui K,
Nishiyama A, Sugii N, Natori K, Hattori T, and Iwai H, Valence number transition
and silicate formation of cerium oxide films on Si (100), 59th Japan Society of
Applied Physics (JSAP), Japan, March, (2012).
5) Zhao Y, Mamatrishat M, Kakushima, Ahmet P, Kataoka Y, Tsutsui K, Nishiyama A,
Sugii N, Natori K, Hattori T, and Iwai H, Interface trap density estimation of
reactivity formed La-silicate and La2O3, 59th Japan Society of Applied Physics
(JSAP), Japan, March, (2012).
6) K. Tuokedaerhan, T. Kaneda, M. Mamatrishat, K. Kakushima, P. Ahmet, K. Tsutsui,
A. Nishiyama, N. Sugii, K. Natori, T. Hattori, and H. Iwai, Effects of post
deposition annealing on electrical characteristics of MOS device with La2O3/n-Si
structure, 72th Japan Society of Applied Physics (JSAP), Japan, Aug.,(2011).
7) C. Dou, M. Mamatrishat, D. Zade, T. Sato, K. Kakushima, P. Ahmet, K. Tsutsui, A.
Nishiyama, N. Sugii, K. Natori, T. Hattori, and H. Iwai, Resistance switching
behaviors in rare earth (Ce, Eu) oxide based MIM structures, 71th Japan Society of
Applied Physics (JSAP), Japan, Sept., (2010).
151
Acknowledgements
It would not have been possible to write this doctoral thesis without the help and
support of the kind people around me, especially those who supports me by moral,
financial, instrumental, and presentational, and also interactive communicational way.
First of all, I am sincerely and heartily grateful to my supervisor Prof. Hiroshi Iwai of
Tokyo Institute of Technology (TIT) and associate Prof. Parhat Ahmet (TIT) for their
offerings of various opportunities, helpful guides, continuous encouragement, and
fruitful discussions, and also friendly advice. Without their supports my study could not
have success. Their tremendous supports I received have been invaluable on both an
academic and a personal level, for which I am extremely grateful. The opportunities and
experience I get from them bring me great benefits to my future life.
I am deeply grateful to professors Takeo Hattori (TIT), Kenji Natori (TIT), Nobuyuki
Sugii (TIT), Akira Nishiyama (TIT), Yoshinori Kataoka (TIT), Kazuo Tsutsui (TIT) for
their useful discussions, wise guides, detailed corrections and instantaneous email
exchanges. I am especially deeply acknowledging associate Prof. Kuniyuki Kakushima
(TIT) for his enthusiastic encouragement, experimental and theoretical guide for
research works, and fruitful discussions throughout my doctoral study. I am sure it
would have not been possible to complete this doctoral thesis without his guide and
support. His endless support promotes and stimulates my professional knowledge.
I am also grateful to professors Masahiro Watanabe (TIT), Shun-ichiro Ohmi (TIT),
Ming Liu (Institute of Microelectronics Chinese academy of Sciences), Hei wong (City
152
University of Hong Kong), Zhenan Tang (Dalian University of Technology), Zhenchao
Dong (University of Science and Technology of China), Junyong Kang (Xiamen
University), Weijie Song (Ningbo Institute of Material Technology Engineering),
Chandan Sarkar (Jadavpur University), Wang yang (Lanzhou Jiaotong University) and
Kenji Shirai (University of Tsukuba), and also associate Prof. Baishan Shadeke
(Xinjiang University) for their reviewing manuscript and giving valuable comments at
the final examination of thesis dissertation.
I would also like to thank Prof. Hiroshi Nohira (Tokyo City University) for XPS
measurements and valuable advice on XPS results.
I would like to thank department of electronics and applied physics (DEAP),
interdisciplinary graduate school of science and engineering (IGSSE), frontier research
center (RFC), G-COE program of Photonics integration-Core Electronics (PICE),
Innovative Platform for Education and Research (IPER) of TIT, and the Japan Student
Services Organization (JASSO), and also NEC C&C cooperation for their financial
supports during my doctoral studies. I appreciate continuous supports from program
leader of G-COE PICE Prof. Fumio Koyama, Prof. Iwamoto Yogaku of IPER, and Dr.
Daniel Berrar of IGSSE.
I would like to appreciate the consistent supports from Prof. Iwai’s laboratory
secretaries, Ms. Akiko Matsumoto, Ms. Mikoto Karakawa, and Ms. Masako Nishizawa.
I would also appreciate supports from Secretary Ms. Chikako Yoshida (G-COE PICE),
and secretaries of DEAP, IGSSE, FRC, G-COE, and IPER and also staffs of Student
Support Division and Library of TIT.
I am obliged to colleagues of Prof. Iwai’s Laboratory, Dr. Milan Kumar Bera, Dr.
Jaeyeol Song, Dr. Takamasu Kawanago, Dr. Kiichi Tachi, Dr. Soshi Satoh, doctoral
153
students Miss. Miyuki Kouda, Lee-Yeong-hun, Abudureheman Abudukelimu, Kamale
Tuokedaerhan and MSc students Daisuke Kitayama, Tasuku Kaneda, and also BSc
students Tohru Kubota, Takuya Seki for their friendly discussions, and lab assistances. I
especially acknowledge doctoral student Dariush Hassan Zadeh for his enthusiastic and
friendly discussions and also careful proof reading of the manuscript. His proof reading
improves quality of this thesis. Besides, I would like to thank all other members of
Iwai’s Laboratory for their kind hospitality and friendships.
Finally, I would also like to thank all of my family, especially my parents, brother and
sisters, and also my wife Nuriman and also my son Anser for their great patience, moral
supports and the understanding during my doctoral studies.
Lastly, but by no means least, I offer my regards and blessings to all of those who
supported me in any respect during the completion of the doctoral studies.
Mamatrishat Mamat
Suzukakedai Campuse
Tokyo Institute of Technology
Yokohama, Japan,
2012/04/16
154
Appendix
A. MATLAB code for RCS-limited electron mobility calculation
The RCS-limited electron mobility was calculated based on the work of S. Saito (J.
Appl. Phys., 98, 113706(2005)).
The MATLAB code was written by the author Mamat Mamatrishat.
Iwai Laboratory
Department of Electronics and Applied Physics
Interdisciplinary Graduate School
Tokyo Institute of Technology
------------------------------------------Physical constants-----------------------------------------
Clear
fid=fopen('77K-La2O3-La-sil.txt','w+'); % open a data file
double E;
double Z_o;
h=6.63*10^(-34); % Planck’s constant [JS]
h_p=h/(2*pi); % Reduced Planck’s constant [JS]
e=1.6*10^(-19); % Electron charge [C]
m_o=9.1*10^(-31); % Electron mass [kg]
m_p=0.19*m_o; % Effective mass in interface direction
m_z=0.916*m_o; % Effective mass motion in z direction
V=1; % Voltage unit
g_v=2; % Degeneracy factor for spin
k=1.38*10^(-23); % Boltzmann constant [J/K]
E_o=3.1*e*V; % Lowest subband energy 3.1eV
E_f=4.56*e*V; % Fermi energy (refer to vacuum level)
k_f=sqrt(2*m_p*E_f)/h_p; % Wave vector corresponding to Ef
T_1=300; % Room temperature 300 K
% Densities in gate stack
N_depl=3*10^20; % Depletion charge density
N_inv=2.5*10^12; % Inversion charge density
155
% Permittivities in gate stack
E_Si=11.7; % Dielectric constant of silicon (or 11.5)
E_SiO2=3.9; % Dielectric constant of SiO2
E_La-sili=10; % Dielectric constant of La-silicate
E_Al2O3=11.5; % Dielectric constant of Al2O3 (or 9.3)
E_La2O3=23; % Dielectric constant of La2O3
% Thickness of layers in the gate stack
t_SiO2_1=0.7*10^(-9); % 0.7nm, 0.9nm, 1.5nm, 2.7nm
t_Al2O3=2.0*10^(-9); % Physical thickness of Al2O3
t_phys_1=2.7*10^(-9); % Total physical thickness
%-------------------------------------Parameter P_0 and P_av-------------------------------------
b_alpha=48*pi*m_z*e^2; % Pre-factor of the b
step=E_meas;
Low_E= Low_E;
Up_E=Up_meas;
E_eff= Low_E:step:Upper_E; % Effect field (unit in V/m)
b=(b_alpha*(E_Si*E_eff/e-5*N_inv/32)/(h_p^2)).^(1/3); % Variation factor
syms E
P_o = @(E) ((b./(b+2*sqrt(2*m_p*E/h_p^2)/45)).^3);
P_av = @(E)((8*b.^3+9*b.^2*2*sqrt(2*m_p*E/h_p^2)+...
3*b.*2*sqrt(2*m_p*E/h_p^2).^2)./(2*(b+2*sqrt(2*m_p*E/h_p^2))).^3);
%-------------------------Screening parameter determination -----------------------------------
eta=(E_f-E_o)/(k*T_1);
mahraj=(1+exp(-eta))*log(1+exp(eta));
q_so=(N_inv*e^2)/(2*E_Si*k*T_1*mahraj);
Fermi = @(E) 1/(1+exp((E-E_f)/(k*T_1))); % Fermi distribution function
q_s = @(E) q_so/(2*Fermi(E_o))/(sqrt(E/4));
%--------------------------------- Parameter beta ---------------------------------------------------
beta1=(E_Si-E_La-sili)/(E_Si+E_La-sili);
beta2=(E_La-sili-E_Al2O3)/(E_La-sili+E_Al2O3);
beta3=(E_Al2O3-E_gate)/(E_Al2O3+E_gate);
%--------------------------------- Parameter gamma------------------------------------------------
Yegin_1=[]
gam_40_1=[]
gam_4_1=[]
gam_1_1=[]
156
gam_2_1=[]
gam_3_1=[]
gam_4_1=[]
gam_5_1=[]
Yegin_1 = @(E)(beta2*exp(-2*2*sqrt(2*m_p*E/h_p^2)*t_SiO2_1)+beta3*...
exp(-2*2*sqrt(2*m_p*E/h_p^2)*t_phys_1));
gam_40_1 = @(E)((beta2)*(beta3)*exp(-2*2*sqrt(2*m_p*E/h_p^2)*t_phys_1)+...
exp(-2*2*sqrt(2*m_p*E/h_p^2)*t_SiO2_1).*(1+beta1*Yegin_1(E)));
gam_4_1 = @(E) (1./gam_40_1(E));
beta=beta1*beta2*beta3;
gam_1_1 = @(E) ((gam_4_1(E)).*(beta*exp(-2*2*sqrt(2*m_p*E/h_p^2)*t_phys_1)+...
exp(-2*2*sqrt(2*m_p*E/h_p^2)*t_SiO2_1).*(beta1+Yegin_1(E))));
gam_2_1 = @(E) (gam_4_1(E).*(exp(-2*2*sqrt(2*m_p*E/h_p^2)*t_SiO2_1)+...
beta2*beta3*exp(-2*2*sqrt(2*m_p*E/h_p^2)*t_phys_1)));
gam_3_1 = @(E) (gam_4_1(E).*(exp(-2*2*sqrt(2*m_p*E/h_p^2)*...
t_SiO2_1).*Yegin_1(E)));
gam_5_1 = @(E) (gam_4_1(E)*beta3.*exp(-2*2*sqrt(2*m_p*E/h_p^2)...
*t_phys_1));
%--------------------------------------Average scattering potential-------------------------------
Z_o_1=-0.7*10^(-9); % Position of test charge (0.7~2 nm)
Ze=e*A_N; % Atomic number of fixed charge in gate
mm1=(1-beta1)*Ze;
denominator1_1 = @(E) (2*sqrt(2*m_p*E/h_p^2)+...
q_s(E).*(P_av(E)+gam_1_1(E).*P_o(E).*P_o(E)));
surat1_1 = @(E)
(mm1*P_o(E)*(1-beta2).*exp(-4*sqrt(2*m_p*E/h_p^2)*t_SiO2_4).*(gam_4_1(E).*...
exp(2*sqrt(2*m_p*E/h_p^2)*Z_o_1)+...
gam_5_1(E).*exp(-2*sqrt(2*m_p*E/h_p^2)*Z_o_1)));
A_av1 = @(E) ((surat1_1(E))./((4*pi*E_Si)*denominator1_1(E)));
%--------------------------------------Demonstrating result---------------------------------------
subplot(2,2,1)
plot(E_eff,A_av1,'--rs')
%-------------------------------------- Scattering rate ---------------------------------------------
Z_o=[];
Pref=(2*pi*m_z)*(2*pi)/(h_p^3); % Integral constants
N_ofix=N_depl; % Fixed charge (FC) to cause the RCS
157
N_rcs_1 = @(Z_o) (N_ofix*exp(-2*sqrt(2*m_p*E/h_p^2)*Z_o));
% Exponentional distribution of FC
F1 = @(Z_o) ((N_rcs_1(Z_o)).*((A_av1(E)).*(A_av1(E))));
integ1=quadv(F1,-d_limit,u_limit); % Double integral part
f_rcs1=Pref*integ1;
subplot(2,2,2)
plot(E_eff,f_rcs1,'--rs')
%--------------------------------- Average scattering time ----------------------------------------
E=[];
D_f = @(E) -1/(k*T_1)*(1-Fermi(E)).*Fermi(E); % Derivative of the Fermi function
D_s=g_v*m_p/(pi*(h_p)^2); % Density of states(E>Ec_min=3.1eV)
S11 = @(E) (-D_s*E*(D_f(E))./f_rcs1);
Surat_integ1=quadv(S11,d_limit1,u_limit1); % Integral of S11
M1 = @(E) (D_s*E.*Fermi(E));
Mahraj_integ1=quadv(M1, d_limit1, u_limit1);
tao_rcs1=Surat_integ1./Mahraj_integ1; % Average RCS time
subplot(2,2,3)
plot(E_eff,tao_rcs1,'--rs');
%------------------------ Remote charge scattering limited mobility --------------------------
u_rcs1=e*tao_rcs1/m_p;
subplot(2,2,4)
plot(E_eff,u_rcs1,'--rs');
E_eff1=E_eff;
fprintf(fid,'%10.4e¥t%10.4e¥t%10.4e¥n',E_eff1,A_av11, u_rcs1);
end