a study of substrate noise in mixed-signal integrated ... · a study of substrate noise in...

A Study of Substrate Noise in Mixed-Signal Integrated Circuits

by

Mohammad Hekmat

B . S c , Sharif University of Technology, 2003

A THESIS S U B M I T T E D IN P A R T I A L F U L F I L M E N T O F T H E R E Q U I R E M E N T S F O R T H E D E G R E E O F

M A S T E R O F A P P L I E D S C I E N C E

in

The Faculty of Graduate Studies

^ (Electrical and Computer Engineering)

T H E U N I V E R S I T Y O F B R I T I S H C O L U M B I A

July, 2005

© Mohammad Hekmat, 2005

11

Abstract

Integrating analog and radio-frequency (RF) circuits with digital blocks on a C M O S

system-on-a-chip (SoC) has drawn a lot of attention, recently. One major obstacle at

this high level of integration is the substrate noise, which results in undesired interaction

between these circuits through the common substrate. Analog circuits are the main vic

tims of such interactions; consequently, understanding the behaviour of substrate noise

and performance degradations it causes, is indispensable for analog designers.

This work addresses three aspects of substrate noise. First, substrate noise is char

acterized in the time and frequency domains to identify major parameters that control

substrate noise generation, propagation, and reception. Effects of many parameters on

the amount of noise generation and coupling are also studied.

Second, this thesis investigates the noise impact on analog circuits from a circuit-level

point of view by introducing a new small-signal model of the M O S device, which accounts

for the substrate noise effects. While most works have focused on system-level or signal-

level analysis, study of the noise from a circuit-level point of view is more beneficial for

analog designers because it gives them more insight on how to improve the substrate noise

rejection capability of their designs.

Finally, noise reduction techniques are revisited in this work. The use of passive guard-

rings is reviewed in detail and the effects of many design parameters on the amount of

noise attenuation provided by these structures are studied. The behaviour of guard-rings

in different substrates are also discussed.

i i i

Table of Contents

Abstract i i

Table of Contents i i i

List of Tables v

List of Figures v i

List of Abbreviations v i i i

Acknowledgements ix

1 Motivation 1 1.1 Challenges of Analog C M O S Circuits in SoCs 1 1.2 Research Goals 3 1.3 Thesis Organization 4

2 Background 6 2.1 Substrate Noise Characterization 8

2.1.1 Noise Injection into the Substrate 9

2.1.2 Noise Propagation through the Substrate 10

2.1.3 Noise Reception Mechanisms 11

2.2 Substrate Noise in Frequency Domain 12

2.3 Effects of Substrate Noise 13

2.4 Substrate Noise Simulation 15

2.5 Substrate Noise Reduction Techniques 17

3 Substrate Noise Characterization 19 3.1 Supply/Ground Noise due to Switching 21

3.1.1 M O S Device Modelling 21

3.1.2 Supply/Ground Noise in a Single Gate 23

3.1.3 Simultaneous Switching of Multiple Gates 26 3.1.4 Supply/Ground Noise Simulation Results 28

Table of Contents iv

3.2 Internal versus External Noise Sources 31

3.3 Substrate Noise in Frequency Domain 35

3.4 Noise versus Switching Time 35

3.5 Effect of Substrate Type on Noise 39

3.5.1 Different Substrate Types 39

3.5.2 Noise Behaviour in Different Substrates 42

3.6 P M O S versus N M O S 46

3.7 Summary 47

4 Model l ing the Effect of Substrate Noise 49 4.1 Noise Modelling in M O S Devices 50

4.2 M O S F E T Small-Signal Model Including Substrate Noise Effects 52

4.3 Noise Figure Calculation 55 4.4 Summary 62

5 Evaluation of Reduction Methods 63 5.1 Noise Injection Reduction 64

5.1.1 Switching Activi ty Spreading 65 5.2 Noise Propagation Reduction 66

5.2.1 Passive Guard-Rings 67 5.3 Noise Reception Reduction 76 5.4 Summary 77

6 Conclusion and Future Work 79

6.1 Conclusion 79

6.2 Future Work 80

Bibliography 82

A M O S F E T Small-Signal M o d e l 88

V

List of Tables

1.1 Some of the recently reported SoCs 3

5.1 Noise attenuation using GRs with different shapes 74

vi

List of Figures

1.1 The block diagram of a multi-standard SoC 2

2.1 Partitioning substrate noise coupling mechanism into three steps 9

3.1 Illustration of internal and external noise sources 19

3.2 I-V characteristic of an N M O S device in 0.18/zra technology and its linear

approximation 22

3.3 A typical C M O S inverter along with the package model 24

3.4 Switching noise voltage on ground line with L = InH, R = 2Q, tr — 200ps,

and N = 100 28

3.5 Maximum noise on ground as a function of the number of switching gates

(R = 0, tr = 200ps, L = InH, C = 0) 29

3.6 Maximum noise on ground as a function of the number of switching gates

(R = 2tt, tr = 200ps, L = InH, C = 100 /F) 30

3.7 Maximum noise on ground lines as a function of the inductance in supply

lines (R = 2Q, tr = 200ps, C = 100 /F , N = 200) 31

3.8 Comparison of the internal and external noise sources 32

3.9 Layout of substrate noise analysis testbench 34

3.10 Attenuation factor as a function of frequency 36

3.11 Substrate noise waveforms for various clock rise-times 37

3.12 Peak-to-peak value of substrate noise as a function of the rise-time of the

last stage 38

3.13 Two most commonly used silicon substrates 40

3.14 Resistive modelling of the substrate 41

3.15 Attenuation factor as a function of the distance between analog and digital

nodes in two types of substrate (Note that the scales are different.) . . . . 43

3.16 The dependence of the attenuation factor on the resistivity of the bulk in

lightly-doped wafers 44

3.17 Illustration of geometric mean distance (dgm(i) 45

3.18 The dependence of the attenuation factor on the thickness of the epitaxial

layer 46

List of Figures v i i

3.19 Frequency dependence of the additional attenuation provided by P M O S . . 47

4.1 M O S F E T small-signal model, including device internal noise sources (no

substrate noise modelling or body effect) 50

4.2 Small-signal model of a M O S F E T , including device internal noise sources,

substrate noise and body effect 52

4.3 Simplified version of Figure 4.2 53

4.4 A typical inductively-degenerated L N A 55

4.5 Small-signal model of an inductively-degenerated L N A 56

4.6 Normalized device noise factor as a function of Q for different values of c. 58

4.7 Normalized substrate noise factor as a function of Q 59

4.8 Noise figure as a function of Q. The spectral density of substrate noise is

given in V2/Hz 60

4.9 Comparison of noise figure for different Qs. (The spectral density of sub

strate noise is given in V2/Hz.) 61

5.1 Switching activity spreading 65

5.2 Effect of SAS in time and frequency domains 66

5.3 Lumped model of GRs in lightly-doped substrates 68

5.4 Attenuation as a function of frequency for different G R arrangements. . . 70

5.5 Additional attenuation provided by GRs as a function of frequency 71

5.6 G R attenuation as a function of width 72

5.7 Effect of G R placement 72

5.8 Different G R shapes 73

5.9 Lumped model of GRs in epitaxial substrates 75

5.10 Effect of substrate type 76

A . l Detailed small-signal model of the M O S device, including device internal

noise sources, parasitic capacitances, and body effect 88

A.2 Simplified M O S F E T small-signal model (parasitic capacitances, gate dis

tributed resistance, and body effect are ignored) 89

A.3 M O S F E T small-signal model with a single noise source representing the

effects of both channel thermal and gate-induced noise 90

A.4 M O S F E T model for the calculation of the effect of gate-induced noise . . . 90

A.5 Equivalent circuit to find Zgs 91

A.6 M O S F E T model for the calculation of the effect of channel thermal noise. . 92

List of Abbreviations

A D C Analog-to-Digital Converter

B E M Boundary Element Method

C B L Current Balanced Logic

C C B L Complementary Current Balanced Lo

D A C Digital-to-Analog Converter

D N C Device Noise Coefficient

D N F Device Noise Factor

F D M Finite Difference Method

F S C L Folded Source Coupled Logic

G P S Global Positioning System

L N A Low-Noise Amplifier

P L L Phase-Locked Loop

SAS Switching Act ivi ty Spreading

S C L Source Coupled Logic

S N C Substrate Noise Coefficient

S N F Substrate Noise Factor

S N R Signal-to-Noise Ratio

SoC System-on-a-Chip

SOI Silicon-on-Insulator

SSN Simultaneous Switching Noise

V C O Voltage-Controlled Oscillator

Acknowledgements

' This thesis would not have been completed without the appreciable help of many great

people who made my life in U B C an enjoyable and enlightening experience.

First of all I would like to express my gratitude to my supervisor, Dr. Shahriar Mirab-

basi for giving me the opportunity to work in his group. I am greatly indebted to him for

his continuous support, patience, and enthusiasm. He has been a great friend and advisor

for me. I would also like to thank Professors Andre Ivanov and Resve Saleh for reviewing

my thesis. I also wish to thank Dr. Maj id Hashemi for his valuable technical comments.

This research was supported in part by S i R F Technology Inc., C M C , and N S E R C .

I gratefully acknowledge the support of my colleagues in System-on-a-Chip group in

U B C . I'm especially thankful to Shahrzad Jalali, Pedram Sameni, Zahra Ebadi, Marwa

Hamour, Samad Sheikhaei, Dipanjan Sengupta, Y in -T ing Chang, Behnoosh Rahmatian,

Neda Nouri, Edmund Lee, Rod Foist, Peter Hallschmid, and Howard Yang. I would also

like to extend my thanks to my friends in U B C for all the memories I share with them,

especially Mehran Motamed, Ehsan Dehghan, Hani Eskandari, Reza Zahiri, Sara Khosravi

and also all my colleagues in E C E G S A .

M y sincere thanks goes to Roberto Rosales for all his support and willingness to help.

I also wish to thank Roozbeh Mehrabadi for C A D support and Sandy Scott for her ad-

i ministrative assistance in our lab.

A n d the last but the most, I express my deepest appreciation to my wonderful parents

and sisters for all their love and endless support. If it were not for their sincere help and

encouragement, I would not have made it as far as I did.

1

Chapter 1

Motivation

1.1 Challenges of Analog CMOS Circuits in SoCs

Continuous scaling in C M O S technology has provided improved device performance and

lower cost in digital circuits over the past three decades. The proliferation of C M O S

digital circuits has augmented the demand for C M O S analog and RF circuits, which

were previously implemented in Bipolar or B i C M O S technologies. However, since C M O S

processes have traditionally been optimized for digital applications, they are not ideal

candidates for analog purposes owing to several shortcomings such as the inherent low

drive capability of active devices, the relatively poor quality of on-chip passive elements,

and the low power supply requirement imposed by digital applications. Despite these

difficulties, analog designers have managed to develop successful C M O S analog and R F

blocks with novel architectures and design techniques [1].

The feasibility of using C M O S in analog circuits has motivated people toward higher

levels of integration and, ultimately, a system-on-a-chip (SoC) that will be a combination

of digital, analog, and R F circuits. Figure 1.1 shows a simplified block diagram of an SoC

with multi-standard R F front-end, analog-to-digital converter ( A D C ) , digital-to-analog

converter (DAC) , and baseband signal processing blocks as well as other logic and digital

Chapter 1. Motivation 2

GPS

GSM

IEEE802.11

A D C

Baseband Processing

Unit

CPU DSP

Logic and Control Unit

Bluetooth DAC Memory

I/O

I I I

RF Front-end Mixed-Signal Interface

Digital Unit

Figure 1.1: The block diagram of a multi-standard SoC.

units. Such SoCs wil l result in considerable reduction in cost, in power consumption, and

in form factor, each of which are of crucial importance in handheld devices.

Recently, mixed-signal SoCs have drawn a lot of attention, as shown in Table 1.1 [2-13],

especially for wireless applications; however, designing an SoC is not as trivial as putting a

few blocks on the same chip. A n immediate problem in abutting analog and digital blocks

, is the signal integrity issue and, more specifically, substrate noise effect, which is defined

as the problem of performance degradation (mostly in analog blocks) due to the activity

of neighbouring digital circuits.

The substrate noise issue is even more noticeable, when one realizes that many of

the works in Table 1.1 have denoted substrate noise as their major challenge for single-

' chip integration. Those results are in addition to the published results on performance

degradations of individual analog blocks such as A D C s , phase-locked loops (PLLs) , and

low-noise amplifiers (LNAs) . Furthermore, one can anticipate that the problem wil l be

further aggravated in future SoCs because of the increasing complexity of digital functions

http://IEEE802.11


Company Application Technology Date Alcatel [2] Bluetooth 0.25pm ISSCC01 Atheros [3] IEEE802.11a 0.25pm ISSCC02 Toshiba [4] IEEE802.11a 0.18jLOTl ISSCC03 A M D [5] IEEE802.11b 0.25^um ISSCC03 Toshiba [6] Bluetooth 0.18pm ISSCC03 Sony [7] G P S 0.18pm V L S I Symp.03 STmicroelectronics [8] G P S 0.18pm CICC04 Texas Instruments [9] Bluetooth 0.13pm ISSCC04 Broadcom [10] IEEE802.11b 0.18pm ISSCC05 Atheros [11] IEEE802.11g 0.18pm ISSCC05 Texas Instruments [12] G P S 90nm ISSCC05

Table 1.1: Some of the recently reported SoCs.

and faster clock switchings. A l l these issues, coupled with the overall challenges in analog

C M O S design, present a picture of the problem where understanding substrate noise would

obviously be indispensable.

1.2 Research Goals

This research is intended to provide an intuition into the issue of substrate noise and how

it can affect the performance of critical blocks in a mixed-signal SoC, especially in R F and

analog parts. It targets three research areas: the first is the study of substrate noise in both

the time and frequency domains and the analysis of the effect of several parameters such

as clocking frequency and package parasitics on the behaviour of the noise. Additionally,

some technological aspects, such as the effect of the substrate type on noise propagation

and generation, wil l be explored; therefore, characterization is one of the primary concerns

of this part of the work.

In the second part, the impact of substrate noise on the performance of L N A s , as a


representative sensitive analog block, will be studied. This is achieved through a new

approach using a proposed M O S device model that accounts for substrate noise effects.

Previous work on the same topic has merely considered the problem from a signal analysis

aspect; however, our goal is to approach it from a circuit design point of view, which allows

for an intuitive perspective on how design parameters can be changed to reduce the effect

of substrate noise.

Efficient techniques to mitigate the performance degradation caused by substrate noise

wil l be required more and more in future SoCs; thus in the last part of the work, we evaluate

the efficiency of existing noise reduction methods and trade-offs in using them. After all,

the goal of this research is to show that substrate noise has added new complexity to

analog circuit design in mixed-signal SoCs; therefore, to achieve successful designs, it is

necessary to take substrate noise into account during the design stage.

1.3 Thesis Organization

This thesis is organized as follows: first, Chapter 2 gives an overview of the substrate noise

problem and briefly, discusses the previous research on this topic. Next, Chapter 3 dis

cusses the characterization of substrate noise both theoretically and through simulations.

Supply noise as a main contributor to external substrate noise sources wil l be studied in

detail. This chapter also analyzes the impact of the substrate type on noise propagation

behaviour, as well as the effect of various parameters on the amount of noise both in the

time and frequency domains.

Modelling the effect of substrate noise on the performance of analog C M O S circuits


is of crucial importance; therefore, a separate chapter focuses on this topic. As such,

Chapter 4 wil l review a general model for noise analysis in M O S circuits, which wil l be

• modified for substrate noise analysis purposes. Based on the new model, the effect of

substrate noise on a typical L N A in an R F system will be studied.

Chapter 5 explores substrate noise reduction techniques. The relationship between the

efficiency of these methods and several parameters such as frequency, digital activity, and

physical separation wil l be investigated. Finally, Chapter 6 presents concluding remarks

and suggestions for future work.

6

Chapter 2

Background

Most modern communication systems use complicated digital signal processing blocks, the

activity of which affects the performance of sensitive analog circuits through interactions

' via the on-chip parasitics and the common substrate. Such interactions are mostly classi

fied as noise because, by definition, any unwanted fluctuation in analog or digital signals

wil l be considered as noise. In this thesis, substrate noise is meant to be the undesired

effects of neighbouring blocks on each other in an SoC, which is propagated through the

common substrate. It should be noted that, in contrast to white noise, this type of noise

is not totally random but depends on the activity in different parts (mainly digital of the

chip); therefore, one can consider it as pseudo-random noise.

In general, the maximum tolerable amount of noise is determined by the application

and the standard. In some applications such as G P S a very stringent noise requirement

is imposed, whereas others, such as Bluetooth, have a more relaxed noise margin. This

has been the main obstacle in achieving single-chip solutions in certain applications. For

example, as was shown in Table 1.1, the single-chip G P S was introduced much later than

other wireless standards despite its relative simplicity.

The problem of performance degradation due to the activity of digital circuits was

first observed in the 1980s [14], even before the introduction of mixed-signal SoCs. Most

Chapter 2. Background 7

early researchers studied this phenomenon under the name of switching noise. However,

this type of noise applies mostly to digital circuits and refers to the variations of supply

and ground voltage due to the switchings in digital circuits. Analog circuits are affected

by switching in digital parts not only by supply and ground variations but also by other

mechanisms such as body effect that are not addressed in switching noise analysis; there

fore, analog circuits do not fit exactly into the context of switching noise, but as wil l be

seen, substrate noise is closely related to switching noise; therefore, understanding the

behaviour of switching noise is helpful in substrate noise analysis.

Early researchers in the field of switching noise mostly focused on the calculation of

the maximum amount of noise without taking into account its time or frequency domain

behaviour [15, 16]. It was not until the early 1990s that the first report on the substrate

noise problem was published in [17]. Later, a seminal work in the study of substrate noise

was reported in [18], where substrate noise was studied in the time-domain, and mostly

< the capacitive coupling of the noise was taken into account; therefore, packaging issues and

the relationship between supply noise and substrate noise were neglected. Furthermore,

a simple digital circuit had been used in their analysis; therefore, in later studies more

complicated digital blocks were used as noise generators to explore the effect of various

switching patterns on the behaviour of noise [19, 20].

In addition to the behaviour of noise in time domain, the frequency content of the

noise is important in R F applications because mainly the in-band portion of the noise

or those components that may create in-band intermodulation terms are of significance;

therefore, subsequent researchers included the analysis of noise in the frequency-domain

in their studies [19-21].


In general, the research on substrate noise falls into one of four major categories:

• Those focusing on substrate noise character izat ion either i n the t ime or frequency

d o m a i n [18-20, 22].

• Those s tudy ing the effect of substrate noise on the performance of cer ta in analog

blocks [21, 23-25].

• Those concerned about the mode l l ing of the noise and C A D too l development [26-

29].

• Those concentra t ing on noise reduct ion techniques [30-32].

In the fol lowing sections, we w i l l exp la in the basic aspects of substrate noise p rob lem

and comment on issues i n its character izat ion and model l ing . W e w i l l also review the pr ior

work on this topic and discuss their merits and shortcomings.

2.1 Substrate Noise Characterization

T h e substrate noise coupl ing mechanism can be model led i n three steps, as conceptual ly

i l lus t ra ted i n F igure 2.1 [21]. F i r s t , the noise is generated and injected by d ig i t a l c i r cu i t ry

into the substrate. Nex t , i t travels th rough the substrate and f inal ly couples back to

sensitive analog nodes. A s shown i n this figure, there exists another way for the noise to

' transfer to analog nodes, wh ich is by means of supp ly lines. It should be noted that the

substrate is wel l connected to the supply lines th rough substrate contacts; therefore, any

voltage var ia t ion on the supply lines w i l l couple to the substrate and reach analog bu lk

nodes. W e w i l l address this issue later, because even though i n this case the noise does


Supply network

Noise coupling through supply lines incs \ Noise coupling

back to analog nodes

Digital circuits Analog circuits

l-Noise injection^ by digital switching

f3-No ise reception by analog bulk node

2-Noisc propagation through substrate

Common Substrate

Figure 2.1: P a r t i t i o n i n g substrate noise coupl ing mechanism into three steps.

not d i rec t ly go through the substrate, it couples back to the analog nodes using substrate

contacts. A s a result, this noise manifests i tself th rough substrate contacts and changes

' the substrate voltage, hence it can be considered as substrate noise.

2.1.1 Noise Injection into the Substrate

A l l currents injected into the substrate w i l l cause variat ions of substrate voltage that can

couple back to the analog nodes. These currents can originate from various sources, such as

the charging and discharging o f l o a d or parasi t ic capacitances, device leakage currents, etc.

In d ig i t a l C M O S circui ts , substrate noise is generated by two major mechanisms, namely

the capaci t ive coup l ing from the swi tch ing nodes (main ly transistor terminals) and the

noise from supply or ground lines due to the parasi t ic impedances of these lines [33].

W h i l e the former comes from the direct coupl ing of d ig i t a l switchings th rough parasi t ic

capacitances to the substrate, the lat ter m a i n l y results from the voltage drop across par-

asitics of bondwires and package pins. It should be noted that the capaci t ive coupl ing


is inevitable because the parasitic capacitances of diffusion areas are due to the physical

layout of the circuit and cannot be eliminated; however, the noise due to supply can be

reduced using better packaging (with lower parasitic inductance) or on-chip decoupling

capacitances.

2.1.2 Noise Propagation through the Substrate

, Once the noise is generated in the digital blocks, it wil l propagate all over the chip through

the common substrate. Up to several G H z , the silicon substrate can be considered a

resistive medium [26]; therefore, any perturbation at any node of such a network wil l

potentially cause voltage fluctuations at all other points. While the amount of noise

injection and reception depends on the impedance of the injection and reception points

' and supply contacts, the key parameter in noise propagation is the impedance of the

substrate path.

Since the electrical properties of the substrate are the main factors in the noise prop

agation behaviour, various studies have focused on investigating the effect of substrate

type on the noise [18, 21, 22, 33-35]. Typically, the higher the resistance of the substrate

the better the noise rejection performance; therefore, more advanced processes, such as

SOI, are anticipated to be better in terms of substrate noise rejection. Interestingly, it has

been found that even though these processes are more favourable from a noise propagation

perspective at low frequencies, their advantage is compromised with increasing frequency

mostly because of the capacitive nature of the substrate impedance [34]. Additionally, it

has been shown that the effectiveness of many isolation schemes depends on the properties

of the substrate; consequently, understanding the propagation behaviour of the noise in


various types of substrate is important in both noise characterization and reduction.

2.1.3 Noise Reception Mechanisms

Substrate noise can impact analog circuits through two different mechanisms: directly, by

affecting the signal at the output or input nodes and, indirectly, by changing the design

parameters of the circuit.

One of the direct mechanisms is capacitive reception in which the voltage fluctuations

* of the substrate directly couple to the drain and source terminals of a M O S F E T through

the parasitic capacitances of these diffusion areas [36]. Another direct method is the noise

coupling to the channel through depletion capacitances; however, this method can be seen

as an extra contribution to the noise injected into the source and drain [36]. In many cases,

this noise can be treated as common-mode noise, which can ideally be suppressed using

' differential structures; however, in practice, owing to nonlinearities and asymmetries, it

cannot be removed completely. In addition to the terminals of active devices, passive

on-chip devices such as capacitors, spiral inductors, and resistors can also act as receptors

for substrate noise [37].

One of the major indirect noise reception mechanisms is body effect. This phenomenon

changes the large and small-signal behaviour of the M O S device, which influences analog

performance. It should be noted that, while capacitive coupling can happen in any active

device ( M O S F E T , B J T , or diode), body effect is specific to M O S devices.

Other indirect mechanisms, such as the variation of the capacitance of varactors or

changes in the biasing conditions of the circuit, are also important in certain applications,

e.g., in V C O s and P L L s [23, 38]. However, for the purpose of this work, i.e., the effect of


substrate noise on L N A s , we will focus only on body effect.

2.2 Substrate Noise in Frequency Domain

Most analog circuits work in a specific frequency band. As such, studying the frequency

content of the substrate noise is of interest, since out-of-band noise can be easily removed

by filtering. Most previously reported work has focused on substrate noise in time domain,

and only a few have investigated high-frequency content of the noise and its relationship

to other parameters, such as the clocking scheme of digital blocks [19-21, 39].

A n extension of the time-domain work in [18] for G P S applications was demonstrated

in [21], which covered substrate noise in frequency domain. A theoretical treatment of

the noise was also given; however, it is difficult to get a clear view of the noise frequency

content from the formulation. The experimental results were based on a more complicated

(yet with a well-defined switching pattern) digital circuit; therefore, the noise peaks in

frequency were observed at multiples of clock frequency. Also predicted by this work was

that the spectrum of the noise depends not only on the clock frequency but also on the

switching patterns of the digital circuits, and as the switching in the digital blocks becomes

more random, the noise wil l eventually be distributed equally over the frequency.

Another work presented in [19] used direct measurements to find the frequency content

of substrate noise. One shortcoming of their technique was the limited bandwidth of

the measurement system used, which limited their results to a few 100MHz. The same

result as [21] was obtained, i.e., noise peaks occurred at multiples of the clock frequency.

Additionally, their results supported the dependence on the switching pattern of the digital


circuit; as an example in [19] the digital circuit had a divide-by-2 nature; consequently, in

addition to the main harmonics of the clock frequency, noise peaks were observed at half

of the clock frequency, as well.

One of few measurement results based on an actual SoC was reported in [20], where

it was shown that different cores on an SoC can generate peaks at different frequencies,

which is a more realistic approach compared to the totally random activity of digital

circuits in [21].

2.3 Effects of Substrate Noise

Substrate noise can affect both digital and analog circuits in an SoC; however, its effect on

analog circuits is more pronounced for two reasons: first, analog circuits in general have

a more limited noise budget due to the small amplitude of their input signal. Second,

the mechanisms through which the noise affects their performance are more diverse in

these circuits because, as discussed before, other than direct coupling of the supply noise

to the input and output nodes of the circuit, and capacitive couplings through junction

and device capacitances, a significant noise reception mechanism is body effect, which is

not important in digital applications. The study of noise in analog circuits is also more

complicated, owing to the importance of the analysis of the noise in frequency domain.

In digital circuits, substrate noise can result in false switching, erroneous storage into

flip-flops [40], double clocking, and missing clocked pulses [41]. Another observed phe

nomenon is the change in the delay of the datapath due to substrate noise that can

potentially exceed the predefined clock period.


The effect of substrate noise on analog systems can be analyzed from a signal degrada

tion point of view. Three mechanisms can be distinguished through which substrate noise

degrades analog signals [36]:

1. Direct coupling

2. Intermodulation

3. Sampling

Substrate noise contains high frequency components that can fall into signal band through

the direct coupling of the substrate to the output nodes of the analog circuit. This process

can degrade the signal-to-noise ratio (SNR) directly. In addition to direct coupling, in-

' band noise can be generated through the intermodulation of the noise signals due to

nonlinearities in analog circuits [21]. Another consequence of modulation is variations in

the bias conditions in bandgap references. A n example of such effects is introduced in [38],

where substrate noise in the bandgap reference circuit has resulted in a D C shift of the

output voltage. The last mechanism is sampling, which is a common process in A D C s .

The noise coupled to the analog circuit preceding the A D C , at an out-of-band frequency,

can fold back into signal band through this process [36].

L N A s , P L L s , voltage-controlled oscillators (VCOs) , operational amplifiers (op amps),

and A D C s are common analog and R F blocks in mixed-signal SoCs; therefore, extensive

research has been done on the study of the effects of substrate noise on the operation of

these blocks.

The impact of noise on operational amplifiers was considered in [42]. In [21] the effect

of noise on the performance of a G P S L N A was reviewed from a signal point of view. A


s tudy of the effect of noise on oscillators was given i n [23]. In oscillators, substrate noise

can change the value of the varactors, wh ich i n t u r n causes the output frequency to vary,

thus generating ex t ra j i t t e r or phase noise. In [43], the effect of substrate noise on t i m i n g

j i t t e r of a P L L was explored using a stochastic approach to substrate noise.

Compara to r s are another type of analog c i rcui t wide ly used i n A D C s . A c o m m o n

architecture of comparators is composed of an ampl i f ica t ion stage followed by a la tch.

T h e speed of such comparators is a funct ion of the t ransconductance of transistors i n the

la tch. Since the t ransconductance is affected by the substrate noise th rough b o d y effect,

the speed of the comparator would also change due to the substrate noise. T h i s effect can

be considered as the output s ignal j i t te r that w i l l decrease the S N R of the A D C [44]. It

was shown i n [25] that the output of an A D C can be h igh ly dis tor ted due to substrate

noise. Fur thermore , substrate noise can signif icantly l i m i t the m i n i m u m detectable level

of the s ignal that can degrade A D C ' s resolut ion and decrease its effective number of bi ts .

A l t h o u g h i n most cases substrate noise only degrades the performance of the c i rcui t ,

examples of mal func t ion ing are also reported i n the l i terature. A n example of failure was

reported i n [45] where an 8-bit, semi-flash p ipe l ined video A D C cont inued to fail several

specifications after three design fabr icat ion i terations.

2.4 Substrate Noise Simulation

T h e accurate mode l l ing of substrate noise requires the precise mode l l ing of the whole

layout and substrate, meaning that in format ion about the geometry of a l l wells, wel l

contacts, diffusion areas, trenches, etc. are needed as well as a three-dimensional (3D)


model of the substrate. Even in a small circuit, this comprehensive modelling entails a

huge network of elements whose governing equations will not be tractable. Furthermore,

since the modelling depends on the final layout of the chip, it would be difficult for designers

to get an insight into the effects of substrate noise at the early stages of the design.

Accurate modelling techniques use various methods, such as the finite difference method

( F D M ) or the boundary element method ( B E M ) , and Green's function 1 to accurately

solve physical equations of the substrate and model it with a large and accurate R C

.network [27, 28, 45, 46].

Conventional tools available for substrate noise analysis, such as S P A C E [47] and

S N A [48], use 3D modelling of the substrate and create macromodels of the digital noise

and substrate and solve the resulting network using several simplification algorithms. 2

Some works have suggested small models consisting of a few lumped elements to be added

' to each transistor [18, 19, 34]. One major drawback of these models is that they are

applicable only to epitaxial substrates owing to some special properties of these substrates 3

that renders them impractical for lightly-doped ones; nonetheless, since they can be applied

to simulations at the schematic level, they can be used even before the final layout is drawn.

In addition to substrate modelling, calculation of the switching digital noise is another

part of substrate noise simulation that should be addressed in C A D tools. Due to the

large number of elements on current chips, the accurate simulation of switchings results

in a prohibitively large computation cost; therefore, various methods are proposed in the

1 The Green's function is the potential at any point in a medium with suitable boundary conditions due to a unit current injected at a point within the medium.

2 In this thesis, we use SeismIC noise analysis tool for the study of substrate noise, which is a part of Substrate Noise Analyst (SNA) by Cadence™.

3 We will discuss the difference between epitaxial and lightly-doped substrates in detail in Chapter 3.


literature for macromodelling digital noise [49-51]. A simple approach is to use a properly-

sized chain of inverters instead of a large digital block to reduce the calculation cost.

2.5 Substrate Noise Reduction Techniques

Several existing substrate noise reduction techniques can be found in the literature. The

use of passive guard-rings was studied in [34]. A simple substrate contact was used as a

noise sensor, which is resistively connected to the substrate, whereas in a more realistic

approach analog nodes are connected to the substrate both resistively and capacitively.

Active noise suppression is another method, which was explored in [30, 31]. The basic

idea is to measure the amount of noise and inject an inverted version of the noise into the

substrate to cancel out the original noise. This approach suffers from two shortcomings:

first, this technique wil l cancel the noise locally and cannot be applied to a large area unless

, multiple measuring points and circuitry are used. Additionally, in contrast to passive

methods that do not impose power overhead, this method involves power consumption for

noise reduction circuits, which is not desirable in low-power or handheld applications.

In addition to passive and active guard-rings, digital activity can be modified to gener

ate less noise. This reduction is usually achieved either by reducing the amount of activity

' or distributing it over time. 4 Many low-noise digital families are proposed, including cur

rent steering logic (CSL), current balanced logic ( C B L ) , complementary current balanced

logic ( C - C B L ) , source-coupled logic (SCL) and folded source-coupled logic (FSCL) [52-54].

Output drivers are typically one of the major contributors to substrate noise due to the

4Note that most of these techniques are similar to those used in low-power digital design because both try to reduce instantaneous current or simultaneous switching.


large instantaneous current they draw from the supplies. T h e design of low-noise output

drivers was also addressed i n [41, 55]. A n example of ac t iv i ty d i s t r ibu t ing techniques is

switching activity spreading, wh ich was presented i n [21, 56]. A l t h o u g h this technique

reduces the rms value of the noise, this reduct ion does not necessarily mean that the noise

content i n the frequency band of interest is also decreased; therefore, these approaches

should be used w i t h caut ion in R F appl icat ions [21].

19

Chapter 3

Substrate Noise Characterization

Voltage variations in the substrate are caused by various sources. These sources can be

classified into two major types: internal and external noises. These terms refer to the way

that the generated noise couples to the substrate of analog circuits and not the propagation

properties of the noise through the substrate. Figure 3.1 illustrates this concept.

V Off-chip supply network A /

Digital

~r . - r v_ Analog

Internal Noise External Noise

Figure 3.1: Illustration of internal and external noise sources.

Internal noise refers to the case where the switching of on-chip digital gates is internally

coupled to the substrate through the parasitic capacitances of active devices, wells and

interconnects; therefore, it directly couples to the substrate and transmits to sensitive

nodes, i.e., everything happens internally, within the silicon substrate. On the other

hand, external noise applies to the situation in which a part of the noise path from digital

to analog nodes falls outside of the chip substrate (e.g., on supply lines). A n example of

Chapter 3. Substrate Noise Characterization 20

such noise is when swi tching d ig i t a l gates induce noise on s u p p l y / g r o u n d l ines 1 and then

the resul t ing noise is coupled back to the substrate through substrate and supp ly contacts

i n the v i c in i t y of analog circui ts . Note that bo th the internal and external sources are

consequences of swi tch ing i n d ig i ta l parts, but they use different paths to reach analog

nodes.

In add i t ion to the noises due to swi tch ing act ivi ty , other noises exist that are inde

pendent of swi tch ing i n d ig i t a l gates and are mos t ly due to leakage currents. Examples

of such sources are impact ionization current and photon induced current. However, it

has been shown that these types of noise have less of an impact on the overal l substrate

noise [19, 33], and thus they are ignored i n our study.

In the fol lowing sections, a review of s u p p l y / g r o u n d noise as a major cont r ibutor to

external noises is given first. Nex t , the effects of several parameters on the in ternal and

external sources are analyzed. T h i s section is followed by a discussion on the relative

impor tance of in ternal and external sources to identi ty the dominant noise mechanism.

F i n a l l y , the effect of substrate type on noise propagat ion behaviour is s tudied using s imu

la t ion results from Se i smIC substrate noise analysis too l . It should be noted that Se i smIC

is one of the few substrate noise analysis tools commerc ia l ly available, the accuracy of

wh ich is verified by exper imental results [57, 58].

This noise is sometimes referred to as ground/supply bounce, switching, or ^ noise.


3.1 Supply/Ground Noise due to Switching

, The inductance of package pins and bondwires, along with the transient currents, are the

main causes of supply or ground noise in digital circuits. The transient current during

digital transition in a C M O S logic circuit comes from two sources: the main source of this

current is the charging or discharging of the load capacitance of each gate through the

positive supply (VDD) o r negative supply (V$s), respectively, and the second source is the

• short circuit current between VDD and Vss during the switchings. To explore the behaviour

of this current, in the following section, we develop a simplified M O S F E T model, which

allows for the analytical study of the switching behaviour.

3.1.1 MOS Device Modelling

Early work in the field of switching noise assumed square-law operation for the M O S

device [15, 59]; however, the model now widely in use for short-channel devices is the

a-power law model that accounts for velocity saturation effects [60]. Based on this model,

the drain current of a M O S device in the saturation region can be approximated using the

following equation:

ID = K(VGS-Vthr (3.1)

where Vth is the M O S F E T threshold voltage and a is a technology-dependent parameter,

derived to be equal to 2 for long-channel transistors and closer to 1 for deep submicron

devices. Using Equation 3.1 in supply/ground noise analysis leads to a system of nonlinear

' differential equations that is difficult, if not impossible, to solve analytically. Different

approximation techniques have been proposed to simplify and/or linearize the resulting


Figure 3.2: I-V characteristic of an N M O S device in 0.18pm technology and its linear approximation.

equations [15, 16]. In this section a linear approximation of the M O S device characteristic

- is used, which results in a set of linear differential equations [61].

Figure 3.2 shows the I-V characteristic of an N M O S device along with its linear ap

proximation. In this figure, S P I C E simulations for 0.18um C M O S technology were used

to obtain the N M O S I-V characteristic.

As Figure 3.2 shows, the linear approximation is in close agreement with the actual

' I -V characteristic, especially in the active region. This property is favourable, since the

switching N M O S transistor will most likely remain in the active region during switching

from high to low; therefore, it is expected that the linear approximation wil l give accurate

results in switching analysis. This is particularly true for output drivers where, due to the

large capacitive load, the output voltage remains almost constant during the switching of

the transistor. Using data obtained from Figure 3.2, we can write the linear approximation


of the M O S device as:

ID = K1(VGS-VGSO) for VGs > VGSO (3.2)

where K~i is a constant and VGSO is the intersection point of the approximation line and the

VQS axis, which is not necessarily equal to Vth of the M O S device. Simulation results show

that changes of VDS, within supply limits, have a negligible effect on the I-V characteristic

and is thus ignored in the calculations of this section. It should be further emphasized

that the more linear behaviour of the device, the better this approximation, meaning that

this model is expected to be more accurate for more deep submicron devices.

3.1.2 Supply/Ground Noise in a Single Gate

Figure 3.3 shows a typical C M O S inverter, along with package and bondwire parasitics.

In this figure, the parasitics of the power supply and ground lines are represented using

a lumped R L C model. The capacitive load of the inverter is shown by CL, and the input

signal is modelled with a ramp signal, changing from ground to supply with a finite rise-

time:

To derive an analytical formula for ground variations 2 due to switching, we assume

the noise on the ground line to be initially zero. The N M O S transistor is also initially in

the cut-off region and starts conducting after the input signal reaches V G S O - The following

2Due to the similarity of switching noise calculations on supply and ground lines, only the corresponding derivations for ground lines are presented here. The results can be readily modified to obtain equations for power-supply noise.

Vm — — V D D for 0 < t < tr (3-3)


Figure 3.3: A typical C M O S inverter along with the package model.

equations capture the behaviour of the circuit:

IN = K ^ - V n - V c s o )

IT, = I N C- dt

VN = R I L + L ^ dt

(3-4)

(3.5)

(3.6)

where IN is the current of the N M O S source terminal, II is the current through the

parasitic inductance and Vn is the noise voltage at the substrate node. Combining Equa

tions 3.4-3.6, we have:

L C ^ + (LKt + RC)d^ + (l + RKX)V = L K ^ + RKxVin - RKMso (3.7)

which is a second-order linear differential equation that can be solved analytically. It

should be noted that this linear equation is a result of the linear approximation of the I-V


characteristic of the M O S device.

The analytical solution of the differential equation has the following form:

Vn = Vh + Vp (3.8)

where, Vp is the particular solution and Vh is the general solution of the homogeneous

equation, and is given by:

Vh = dxexl + d2eX2 (3.9)

Ai and A 2 are the roots of the characteristic equation that can be complex and d\ and d 2

are constants that are calculated based on the initial conditions of the circuit. Assuming

a linear ramp approximation, as in Equation 3.3, Vp has the following form:

Vp = at + b (3.10)

where:

a = { l + RKl)tr

( 3 1 1 )

K X { ^ - RVGSO) - (LK, + RC) a B = ~ ^ TSTG " ( 3 1 2 )


3.1.3 Simultaneous Switching of Multiple Gates

It is a common practice in large circuits to replace individual logic blocks with a large

inverter or a chain of inverters that generate the same amount of switching current. This

approach decreases the computational complexity of simulations and is used in many noise

macromodelling applications [49]. The derivations of the previous section can be extended

to the case of N simultaneously switching gates or, equivalently, a large inverter with N

times the width of a single inverter. The equations can be derived in the same manner;

the final equation is as follows:

d2V dV L C ^ + (NLKi + R C ) ^ + (1 + NRKX)V =

dtz dt

N L K ^ + NRKiVin - NRK.VGSO (3.13) at

The solution of this differential equation can be used to find the maximum peak-to-

peak value of the switching noise. First, we look at the characteristic equation of this

differential equation:

L C A 2 + (NLKi + RC)X + (1 + RNKt) = 0 (3.14)

A = (NLKi - RC)2 - 4LC (3.15)

Depending on the value of the parameters and N, the discriminator of the quadratic

equation, A , can be either positive, negative, or zero. We define N^t as the value of N

for which A is zero:


For N > Ncrit the equat ion has two real roots, wh ich is most l ike ly to happen for

large values of N. Note that , as K\ increases (for example when using larger transistors) ,

N c r i t decreases, wh ich is the case for large output drivers. In cases where N < N c r i t , the

behaviour of the noise is different, and r ing ing due to the on-chip parasi t ic capacitance

and inductance is observed. Since output drivers, due to their large transient currents, are

the major contr ibutors to swi tch ing noise, here the equat ion is solved assuming N > N c r i t .

In this case, b o t h A i and A 2 are negative real numbers, resul t ing i n a decaying exponent ia l

t e rm i n the noise expression. Moreover , i t can be shown that under the circumstances

ment ioned above the m a x i m u m swi tch ing noise w i l l always occur at the end of the input

t r ans i t ion t ime, and its value can be calcula ted from the fol lowing formula:

Vnmax = (-ant0 -bn + ^ ) e A 2 ^ - * o ) + ajr + b n ( 3 1 7 )

where A i and A 2 are real roots of the characteris t ic equat ion and | A i | > | A 2 | , to is the

t ime at w h i c h the transistor starts conduc t ing and can be approximated by the fol lowing

formula:

to = ¥r^tr (3.18) VDD

In E q u a t i o n 3.17, an and bn are modif ied versions of a and b ca lcula ted for the case of N

s imultaneously swi tch ing gates and are given by:

RNKXVDD

a n = (1 + NRKJU ( 3 ' 1 9 )

_ NK^Zto* - RVGSQ) - (NLK, + RC)an

n ~ l + NRK, [d-2U)


3.1.4 Supply/Ground Noise Simulation Results

S P I C E simulations were performed in a C M O S 0.18//m technology to evaluate the accuracy

of the proposed model. Figure 3.4 presents the transient behaviour of the noise using

the linear approximation of Section 3.1.1. This figure verifies that the proposed approach

closely follows S P I C E simulation results, especially when the transistor is fully conducting.

100 150 200 250 Time (psec)

350

Figure 3.4: Switching noise voltage on ground line with L = InH, R = 2il, tr = 200ps, and N = 100.

The maximum value of the simultaneous switching noise (SSN) 3 as a function of the

number of switching gates is plotted in Figures 3.5 and 3.6. For the purpose of comparison,

the results of two other works are also included in these figures. To make a fair comparison,

the values of package resistance and capacitance are set to zero in Figure 3.5. The effect

3 This term is frequently used in the literature to represent the noise appearing on supply and ground lines due to the simultaneous switching of digital gates.


0 5 0 1 0 0 1 5 0 2 0 0 N u m b e r o f S w i t c h i n g G a t e s

Figure 3.5: Maximum noise on ground as a function of the number of switching gates (R = 0,tr = 200ps, L = InH, C = 0).

of these parasitics are included in Figure 3.6, where a resistance of 2fi and a capacitance

of 1 0 0 / F are added in the supply parasitic network. As can be seen in Figure 3.5, there is

- a large discrepancy between S P I C E results and those predicted by the approach presented

in [15], which is primarily due to neglecting the effect of velocity saturation in that work. In

the other work, the effects of package capacitance and resistance were ignored, resulting in

underestimating noise values. The results of the proposed model are within 2% of S P I C E

simulations in Figure 3.5. The accuracy decreases as the number of gates increases due to

' the increase in the approximation error used in determining the initial conditions of the

differential equation and neglecting subthreshold current.

Equation 3.17 can be used to analyze the effect of several parameters, such as the

power supply voltage, the parasitic inductance of the package and bondwires, and the

number of simultaneously switching gates, on the maximum amount of noise in the circuit.


0 5 0 1 0 0 1 5 0 2 0 0 N u m b e r o f S w i t c h i n g G a t e s

Figure 3.6: Maximum noise on ground as a function of the number of switching gates (R = 20, tr = 200ps, L = InH, C = 100 /F) .

While parasitic resistance has been neglected in simultaneous switching noise calculations

in [15, 16, 62], simulation results show that as C M O S technology scales down and the

integration level and transient currents increase the voltage drop across this resistance can

potentially be important; more specifically, Equation 3.17 suggests that this resistance

creates a term that increases linearly with time; hence it is more significant in slower parts

of the circuit, such as output drivers, that have larger switching time and contribute more

to noise.

Equation 3.17 verifies the previous result observed in [15] and [16] that the SSN max

imum value is a sublinear function of the inductance as shown in Figure 3.7. This can be

considered a consequence of the built-in negative feedback of the M O S device, which does

not allow the noise to increase unboundedly. Due to this built-in negative feedback, the

drain current decreases as the voltage of the source of the M O S transistor increases, hence


1000

Figure 3.7: M a x i m u m noise on ground lines as a funct ion of the inductance i n supply lines (R = 2Q, tr = 200ps, C = 1 0 0 / F , N = 200).

decreasing the amount of transient current th rough the paras i t ics . 4

A n impor tan t note is that , as can be seen i n the results of this section, the noise on

supply lines can potent ia l ly be large. Once a noise s ignal of hundreds of mi l l ivo l t s appears

on supp ly network of the chip, it can propagate through the substrate v i a supply and

substrate contacts and couple to the substrate node of analog devices; hence, this noise

can construct the major part of the external noise sources.

3.2 Internal versus External Noise Sources

' In the previous sections, s u p p l y / g r o u n d noise was discussed as one of the major cont r ibu

tors to external noise sources; nonetheless, the con t r ibu t ion of each of the two in t roduced

4Here it is assumed that the gate potential is constant.


L e n g t h of B o n d w i r e (urn)

Figure 3.8: Comparison of the internal and external noise sources.

sources (external and internal noises) to the total substrate noise is an interesting pa

rameter to observe. Since external noise sources are typically much larger than internal

sources they can potentially dominate the overall noise. Especially if the analog and dig

ital circuits share the same supply lines, any noise on digital lines wil l directly couple to

i the substrate area in the proximity of analog devices through substrate contacts of that

area, which will drastically increase the amount of noise; whereas in the case of separate

supplies, the only way for the noise on digital supply lines to disturb analog nodes is to

couple to the substrate through substrate contacts of the digital circuits.

Figure 3.8 represents SeismIC simulation results of the substrate noise at the bulk node

* of an analog N M O S located 100pm away from a chain of inverters. The total substrate

noise is plotted as a function of the length of the bondwire, which can be translated into


the amount of inductance. 5 Two cases are plotted in this figure; in the first one the analog

and digital supplies are separated, which means that the total noise is due only to internal

' sources, whereas in the second one supply lines are shared; therefore, both internal and

external noise sources contribute to the overall noise.

Figure 3.8 reveals an important point: the amount of noise increases significantly if the

supply lines of the analog and digital circuits are the same. A n immediate implication of

this observation is that using separate supplies for analog and digital sections significantly

' reduces the interaction between these two parts. In cases where use of separate supplies

is not possible, the total noise can be reduced using a low-inductance package such as

flip-chip. In fact based on Figure 3.8 for the circuit used in these simulations, the noise

coupling from supply lines will be dominant if the amount of the inductance is larger than

200pH, which means that above this value, most of the noise would be due to supply noise

rather than the direct effect of switching in digital cores.6 In other words, external noise

sources dominate very quickly as the inductance in the package increases.

Hereafter, unless otherwise specified, it is assumed that digital and analog supply lines

are separated, implying that only internal noise sources are causing noise at the substrate

of analog nodes. In most parts of this work, a simple inverter in C M O S 0.18/txm is used

as a testbench to study the effect of various parameters on substrate noise. The layout of

the test circuit is shown in Figure 3.9.7 The noise is measured at the substrate of digital

N M O S and a dummy N M O S , which is used to represent a sensitive analog device.

5 As a rule of thumb the inductance is linearly proportional to the length of the bond wire with the slope of InH/mm.

6Note that 200pH is very small compared to the inductance of most available packages. , 7 For more information on the layout of other testbenches please refer to [63]


Figure 3.9: Layout of substrate noise analysis testbench.

To quantify the noise behaviour, the noise attenuation factor is used in this study,

which is defined as the ratio of the peak-to-peak value of the noise at the bulk node of

the N M O S in the inverter to the peak-to-peak value of the noise at the bulk node of the

dummy N M O S :

(3.21) AttPmmrinn - V P P ' D i 9 i t a l

'pp,Analog

The attenuation factor depends on a variety of parameters, such as substrate type and

digital activity. The following sections deal with the characterization of substrate noise

using the attenuation factor.


3.3 Substrate Noise in Frequency Domain

T h e dependence of noise a t tenuat ion on the frequency of operat ion is an impor tan t pa

rameter i n noise analysis i n high-frequency appl icat ions. F igure 3.10 presents Se i smIC

s imula t ion results of the dependence of the a t tenuat ion factor on frequency for various

distances between noisy and sensitive parts. A s can be seen, the noise a t tenuat ion i m

proves as the frequency increases i n F igure 3.10(a). T h i s observation is interest ing because

one might t h ink that at higher frequencies there is more coupl ing between noisy parts and

the substrate. However, a l though the amount of noise coup l ing increases at higher fre

quencies due to the capaci t ive behaviour of the impedance coupl ing the swi tch ing nodes to

the substrate, the amount of substrate coup l ing to quiet lines increases at the same t ime

due to a s imi lar effect. T h i s can be shown by connect ing a noisy ground to the c i rcui t and

measur ing the amount of a t tenuat ion, as depicted i n F igure 3.10(b). In this figure there

has been a I n H inductance on supply lines that resulted i n a noisy ground and supply.

A s a result, the amount of noise a t tenuat ion decreased signif icantly at higher frequencies

due to the increased coupl ing of the c i rcu i t to noisy lines. Fur thermore , the loca l max

i m u m observed i n F igure 3.10(b) is an evidence of the existence of the two compet ing

mechanisms ment ioned above.

3.4 Noise versus Switching Time

A n o t h e r impor tan t parameter is the amount of noise as the swi tch ing t ime of the c i rcui t

changes. F igure 3.11 depicts waveforms of substrate noise i n t ime-domain for various input

clock rise-times. T h e waveforms represented i n F igure 3.11(a) show the case i n wh ich there

Chapter- 3. Substrate Noise Characterization 36

35

30 CD

C o '% 25 CD

20 • d=5 um •d=10u.m • d=50um •d=100um

?00 400 600 800 1000 1200 1400 1600 Frequency (MHz)

(a) Dependence of coupling on the frequency (no noise on supplies).

500 1000 1500 Frequency (MHz)

2000

(b) Dependence of coupling on the frequency (noisy power supply).

F igure 3.10: A t t e n u a t i o n factor as a funct ion of frequency.


§ 10

/ : 1 \ - ' \ \

I; i \ i »

t r= 1ns t = 500ps t =100ps t =10ps .

1: .' J V \

too 101 102 103 104 105 Time (nsec)

(a) Without noise on supply lines.

9 50

i ! i • i i

m 0

-50

'! |! :: Ii ,i

r. ii H

: j 5

-100 I = ! ' : 1 1

t r= 1ns tf = 500ps t =100ps

100 101 102 103 104 105 Time (nsec)

(b) With noise on supply lines.

F igure 3.11: Substrate noise waveforms for various clock rise-times.

is no inductance i n supp ly lines, i.e., there is no supp ly noise, and F igure 3.11(b) is the

same experiment but w i t h an inductance of I n H i n the supply pa th , wh ich has in t roduced

r inging . A s can be seen, there is no significant change i n the m a x i m u m value of the noise

or even the waveform, wh ich can be expla ined us ing the fact that the major contr ibutors

to the noise are those parts of the c i rcui t that draw the largest amount of current from the

supplies, e.g., the output stage, and since changing the inpu t clock rise-time does not affect


the rise-t ime of the output stage, the noise has not changed significantly. O n the other

450

1 5 ° 0 500 1000 1500 2000 2500 3000 Output Stage Rise-Time (psec)

Figure 3.12: Peak-to-peak value of substrate noise as a funct ion of the rise-t ime of the last stage.

hand, i f the swi tch ing t ime of the output stage changes, e.g., by changing its capaci t ive

load, then the peak-to-peak value of noise w i l l vary, as shown in F igure 3.12. T h e flat part

of the plot shows the s i tua t ion i n wh ich the noise of the output stage is not dominant ;

therefore, a further increase i n its r ise-time does not decrease the noise. Based on these

observations, i t can be concluded that increasing the swi tch ing t ime of the output drivers

is an effective way of reducing noise (however, at the expense of a slower system) but i t

does not help i f the noise due to those parts is not dominant .


3.5 Effect of Substrate Type on Noise

As discussed in Chapter 2, substrate type plays an important role in noise behaviour,

especially in noise propagation properties. Due to its resistive nature, the silicon substrate

itself exhibits attenuation to some extent; however, the amount of attenuation depends on

several parameters, such as substrate resistivity and structure.

To characterize noise coupling in different substrates used in C M O S technology, first,

two major types of silicon wafers wil l be reviewed, and the dependence of noise propagation

on a number of process and layout parameters wil l be studied in the following sections.

3.5.1 Different Substrate Types

Figure 3.13 shows the two most commonly used substrate types in C M O S integrated

circuits. The lightly-doped substrate (shown in Figure 3.13(a)) is the simplest silicon

substrate in terms of manufacturability; however, owing to its high susceptibility to latch-

up, this type of wafer was replaced by epitaxial substrates (shown in Figure 3.13(b)) in

older C M O S technologies. In an epitaxial wafer, a thin layer of silicon is deposited on top

of a heavily doped bulk several hundred micrometers thick. Active devices are built into

, this thin high-resistivity layer. This type of substrate circumvents the problem of latch-up

and allows for better device performance due to the better controllability of the doping

profile of the epitaxial silicon [64].

Currently, the most widely used wafer in digital C M O S applications is the epitaxial

substrate. The heavily-doped portion has a resistivity of several milliohm-cm (mfi.cm).

The resistance of the epitaxial layer is typically 2-3 orders of magnitude higher than the


300pm

P"-Bulk (15n.cm)

(a) A typical lightly-doped substrate.

i_ 10/im P -Epi layer(15f2.cm)

NWell

P+-Bulk (0.05rml.cm)

300/mi

(b) A typical epitaxial substrate (not to scale).

Figure 3.13: Two most commonly used silicon substrates.

bulk substrate, i.e., its resistivity is in the same order as the resistivity of a lightly-doped

substrate. Although epitaxial substrate has a better latch-up performance, there is a

compromise between substrate noise attenuation and latch-up immunity depending on

the thickness of the epitaxial layer; i.e., as the thickness of the epitaxial layer increases,

the noise suppression of the substrate improves, while the latch-up characteristic dete

riorates [65]. It should be noted that the scaling of CMOS technology and the use of

lower supply voltages in new CMOS generations has decreased the probability of latch-

up. Additionally, lightly-doped substrates exhibit better RF performance, e.g., better

on-chip spiral inductors, compared to their epitaxial counterparts [66]; therefore, recently,

there has been an increasing interest in using lightly-doped substrates due to their lower

manufacturing cost [35].


Heavily-doped bulk

(b) Epitaxial substrate (not to scale)

F igure 3.14: Resist ive mode l l ing of the substrate.

A s discussed before, the substrate is a resistive network; therefore, a s imple resistive

mode l can be used to analyze noise propagat ion behaviour. F igure 3.14 i l lustrates one

s imple representation of such a model . A s shown i n this figure, the heavi ly-doped bulk i n

ep i tax ia l substrates can be considered a single node due to the low res is t iv i ty of the bu lk

s i l icon [18]. T h i s is pa r t i cu la r ly impor tan t i n the noise propagat ion behaviour because this

' equipotent ia l layer (heavily-doped bulk) can act as the major noise pa th from d ig i t a l to

analog nodes instead of the surface pa th through the ep i tax ia l layer.

T h e presence of the bu lk node is the m a i n reason for the different behaviour of the

noise dependence on the layout parameters i n the two types of substrate. It is also the


basis for the development of lumped-element models for the substrate [18, 19] because

the bu lk defines a single node that is connected to a l l devices th rough the resistances

of the ep i tax ia l layer; whereas, i n l igh t ly -doped substrates, the d i s t r ibu ted nature of the

substrate does not al low for smal l lumped-element models. F r o m the mode l presented

i n F igu re 3.14, one can expect that i n l igh t ly -doped substrates, increasing the distance

between d ig i t a l and analog nodes decreases the amount of coupl ing because of the increase

i n the impedance of the noise pa th , whereas i n ep i tax ia l wafers, increasing the separat ion

is not an effective way, since the noise propagates mos t ly through the heavi ly-doped bu lk

tha t has negligible resistance.

3.5.2 Noise Behaviour in Different Substrates

Figure 3.15 shows the dependence of noise a t tenuat ion factor on the distance between

d ig i t a l and analog circui ts i n bo th types of substrate. A s can be seen, the a t tenuat ion

monoton ica l ly increases i n l ight ly-doped substrates as the distance increases, whi le i n the

, ep i t ax ia l substrates, increasing the distance above a cer ta in l i m i t does not increase the

a t tenuat ion of the noise.

T h e increase i n noise a t tenuat ion at short distances i n the ep i tax ia l substrate can be

a t t r ibu ted to the fact that at short distances a significant por t ion of noise propagates

th rough the high-resis t ivi ty ep i tax ia l layer; therefore, there is no difference between the

' propagat ion behaviour of l ight ly-doped and ep i tax ia l substrates; however, w i t h the i n

crease i n separation, the noise penetrates more through the bulk , hence reducing the

effect of surface at tenuat ion. A s a rule of thumb, increasing the distance between the

d ig i t a l and analog nodes beyond 4 t imes the thickness of the ep i tax ia l layer has a negli-


_ 3 0 co

C

o *= 2 5

CD

< 2 0

5 0 1 0 0 D i s t a n c e ( u m )

1 5 0 2 0 0

f E p i t a x i a l s u b s t r a t e

J 1 1 1 L

0 2 0 4 0 6 0 8 0 D i s t a n c e ( u m )

1 0 0 1 2 0

Figu re 3.15: A t t e n u a t i o n factor as a funct ion of the distance between analog and d ig i t a l nodes i n two types of substrate (Note that the scales are different.)

gible impac t on the noise at tenuat ion [18]. T h i s can also be expla ined us ing the s imple

resistive models of F igure 3.14. Based on the ep i tax ia l substrate model , increasing the

phys ica l separat ion does not increase the resistance of the noise path; thus no further noise

a t tenuat ion is provided.

A n o t h e r parameter of interest is the dependence of noise on the res is t iv i ty of the bu lk

i n l igh t ly-doped substrates. F igure 3.16 depicts the s imula t ion results of the inverter

c i rcui t for different values of substrate resist ivity. T h e a t tenuat ion factor at large phys ica l

separations has a d a behaviour , w i t h a depending on the resis t ivi ty of the bulk . T o just i fy

this effect, an unders tanding of the dependence of the substrate resistance on the distance

between two points is required. A l t h o u g h the ca lcula t ion of the ac tual resistance i n a

real chip is quite complex due to the effects of various parameters i nc lud ing ne ighbour ing


B u l k res i s t i v i t y = 1 0 Q . c m

B u l k res i s t i v i t y = 1 5 Q . c m

B u l k res i s t i v i t y = 2 0 £ X c m

5 0 1 0 0 D i s t a n c e ( u m )

1 5 0 2 0 0

Figure 3.16: T h e dependence of the a t tenuat ion factor on the res is t iv i ty of the bu lk i n l igh t ly-doped wafers.

contacts and devices, i n a s imple case of on ly two contacts (shown i n F igure 3.17) on a

l igh t ly -doped substrate, the fol lowing equat ion can be used [67]:

Rij — kd gmd (3.22)

where a and k are process-dependent fitting parameters, areai and areaj are the areas of

the contacts, and dgmd is the geometric mean distance between the two contacts, defined

as:

dgmd — SL2 fw3 SL! V r.dx1.dy1.dx2.dy2

Wi.Li.W2.L2 (3.23)

E q u a t i o n 3.22 implies a l inear increase i n the resistance at large distances and faster

t han l inear at short distances [67]; thus the observed behaviour i n F igure 3.16 is i n compl i -

http://Wi.Li.W2.L2


H W2 »4 Figure 3.17: I l lus t ra t ion of geometric mean distance {dgmd).

ance w i t h the equat ion of the resistance, ver i fying that the to ta l a t tenuat ion is p ropor t iona l

to the resistance of the substrate pa th .

In ep i tax ia l substrates, the s tudy of the relat ionship between the amount of the at ten

ua t ion and the thickness of the ep i tax ia l layer is instruct ive. One can expect increased

' a t tenuat ion i n thicker ep i tax ia l layers due to the increased resistance of the noise pa th to

sensitive devices. T h i s result can also be concluded from F igure 3.18, wh ich shows the

s imula t ion results for three different ep i tax ia l layer thicknesses.

T y p i c a l l y , the higher the res is t ivi ty of the substrate the better the i so la t ion perfor

mance; therefore, l igh t ly-doped substrates m a y seem to be advantageous i n terms of noise

' suppression. However, there are controversial views on this argument; the conflict arises

from the compromise between two basic mechanisms that control noise at tenuat ion. In

general, the amount of noise at sensitive nodes can be reduced either by d i rec t ing the noise

to a quiet l ine (such as supply or ground line) or the noise should be at tenuated on its way

to analog nodes (e.g, by the resistance of the substrate). T h e h igh res is t iv i ty substrate


• E p i t h i c k n e s s = 7 u m

• E p i t h i c k n e s s = 10u.m

• E p i t h i c k n e s s = 15u.m

4 0 6 0 8 0 D i s t a n c e ( u m )

1 2 0

Figure 3.18: The dependence of the attenuation factor on the thickness of the epitaxial layer.

seems to be better in the sense that its higher impedance results in more attenuation of

noise on its path from the digital source to the analog circuit. On the other hand, a heav

ily doped substrate provides a low impedance path that can transfer noise to the ground,

hence decreasing the effect of the noise on analog blocks [68].

3.6 PMOS versus NMOS

Since P M O S devices are capacitively isolated from the substrate by the underlying n-well,

one may think that they are less susceptible to substrate noise. To verify this argument, a

P M O S was used as a sensitive device, and the results were compared to that of an N M O S .

The additional attenuation provided by P M O S as a function of frequency is plotted in


Figure 3.19. Based on this figure, P M O S has significantly better noise isolation; however,

the advantage is compromised as the frequency increases due to the capacitive behaviour

of the isolation. The considerable amount of noise attenuation in P M O S even at high

70 r

65-

| 6 0 -c o '(3 55-C CD

< 50

45-

4 ° 0 200 400 600 800 1000 Frequency (MHz)

Figure 3.19: Frequency dependence of the additional attenuation provided by P M O S .

frequencies suggests that it is beneficial to use P M O S for sensitive nodes of the circuit

such as the input stage transistors of an L N A from the substrate noise point of view .

However, one should be aware of the inferior performance of P M O S as compared to N M O S ,

due to the lower mobility of carriers, which leads to lower transconductance values and,

consequently, a lower gain and a larger overall noise figure.

3.7 Summary

In this chapter, various aspects of substrate noise were studied. The dependence of sup

ply/ground noise on switching activity and package parasitics were analyzed. Further-


more, it was shown that using the same supply line for analog and digital circuits wil l

substantially increase the amount of substrate noise, mainly because supply lines wil l add

an additional source of the noise to analog circuits. It was also shown that the effect

of external noise sources can be mitigated using lower-inductance packages, even though,

this wi l l not be helpful if internal noise sources are dominant; a situation that requires

other techniques (e.g., lowering the switching time of the output drivers) to decrease the

amplitude of the noise.

It was shown that the substrate type has a crucial influence on the behaviour of the

noise; therefore, the effect of various parameters such as substrate resistivity and thickness

(for epitaxial wafers) on noise propagation properties was also studied.

Finally, it was shown that P M O S devices have better substrate noise performance as

compared to N M O S transistors, due to the extra isolation provided by their underlying

n-well. However, two considerations should be taken into account: first, P M O S is typically

inferior to N M O S in terms of device performance, due to its lower carrier mobility and,

second, the advantage decreases as the frequency of operation increases.

49

Chapter 4

M o d e l l i n g the Effect of Substrate

Noise

Substrate noise affects analog circuits in a multitude of mechanisms. Body effect is one of

them, which is defined as the modulation of the threshold voltage of a M O S device due to

variations in the source-bulk potential. It is shown that with body effect, the threshold

voltage of a M O S transistor can be written as:

where Vtho is the threshold voltage when source-bulk potential is zero, eSi is the substrate

dielectric permittivity, NA is the substrate doping, Cox is the gate oxide capacitance per

unit area, <£/ is the surface inversion potential, and V3b is the source-bulk potential. Vari

ations of Vth will impact both the large and small-signal behaviour of the device; i.e., it

changes the drain current as well as the transconductance of the M O S transistor. The

influence of body effect is typically accommodated in the small-signal model with an addi

tional voltage-controlled current source connected between the drain and source terminals

of the device.

(4.1)

Chapter 4. Modelling the Effect of Substrate Noise 50

In addition to body effect, substrate noise can directly couple to the analog nodes

through supply lines and the neighbouring supply or substrate contacts and junction

capacitances; however, here we assume that the supply lines of the analog and digital

parts are separated; therefore, the common substrate is the main means of communication

between noisy digital and sensitive analog nodes.

This chapter begins with a review of the M O S device noise model. Next, a modified

version of the existing model is introduced that incorporates substrate noise effects. F i

nally, the impact of substrate noise on a typical L N A is studied based on the proposed

model.

4.1 Noise Modelling in MOS Devices

A simplified M O S F E T small-signal model, including device intrinsic noise sources, is shown

in Figure 4.1, where all internal noise sources are combined and represented by a single

noise source at the output [69].1

Figure 4.1: M O S F E T small-signal model, including device internal noise sources (no substrate noise modelling or body effect).

^ h e reader is invited to refer to Appendix A for the full development of this model.


T w o major device noise sources have been incorporated i n this figure: channel thermal

noise and gate-induced noise. T h e current source, indg, represents the effect of b o t h of

these noises and is given by:

i-ndg = 9mZgSing + T)ind (4-2)

where gm is the transconductance of the device, ind and ing represent channel the rmal and

gate-induced noises, respectively, and Zgs and 77 are given by:

1 Z = " || Zdeg + Zg

sCgs 1 + gmZdeg

T) — 1 — ( ^ m ^ d e 9 \ Z

(4.3)

(4-4)

Based on E q u a t i o n 4.2, the mean-square value (i.e., power) of the noise, wh ich is a

more meaningful quant i ty i n noise analysis, can be found as:

i2ndg — inc ind9 = i2nd(\v\2 + 2Re{c ng 9S

nd J 1 nd

n 9 n 2 17 I2

9m\Zjgs\ (4.5)

where c is the correla t ion coefficient between channel thermal noise and gate-induced

noise:

(4.6) c = %nd%ng

nd0 ng

W e define device noise coefficient ( D N C ) as a measure of how int r ins ic device noise sources

are scaled when they are transferred to the output; therefore:

D N C = t^-1 nd

\n\2 + 2 i ? e | c \

^ g m V * Z g s \ + ^Lg2

m\Zgi2 (4.7) nd nd

T h e mode l shown i n F igure 4.1 can be used i n the noise figure ca lcu la t ion of a given

c i rcui t ; however, i t does not account for the effect of substrate noise, s imp ly because i t


neglects b o t h the substrate noise source and b o d y effect. In the fol lowing section, we

include the effect of substrate noise i n the current model , to derive a general mode l for

substrate noise analysis purposes.

4.2 MOSFET Small-Signal Model Including

Substrate Noise Effects

T h e impac t of substrate noise can be added by mode l l ing i t w i t h a voltage source connected

to the substrate of the M O S device, as shown i n F igure 4.2. A new t e rmina l is added to

G r -o

•a + V gs •

B' Csb

Cgs Q"mVgs

•n D

lout

© vs\\zdeg

Figu re 4.2: Smal l -s ignal mode l of a M O S F E T , inc lud ing device in ternal noise sources, substrate noise and b o d y effect.

the previous mode l representing the bu lk node and is connected to vns as the substrate

noise source. CSb is also added to F igure 4.2 because i t is the largest capaci tor among

a l l substrate parasi t ic capacitances that connect the bu lk node to transistor 's terminals .

It should be noted that here we have t ac i t l y assumed that inc lud ing b o d y effect has a

negligible impact on E q u a t i o n 4.5; therefore, indg i n this figure is the same as F igu re 4.1.


Csb

\ s +

^out

Figure 4.3: S impl i f ied version of F igure 4.2.

S imi l a r to the previous section, the effect of the add i t iona l noise source, vns, can be

combined w i t h the in ternal noise sources, inda, i n order to have a single source representing

a l l ex is t ing noises i n the device. T o find the output noise current due to substrate noise,

we s impl i fy F igure 4.2 to obta in F igure 4.3, where Zs is the to ta l impedance seen at the

source te rmina l :

ZS = (Zg + sG •'deg (4.8

and K is given by:

K = ~9n sCgs(Rs + sLg) + 1

(4.9)

Based on this figure, we can calculate the output noise current due to the substrate

noise. T h e fol lowing equations can be w r i t t e n : 2

tout = KVS + gmbVbs (4.10)

(4.11) Vs

sC, + v; sb (4.12)

2Note that since we are interested in the transfer function from vns to the output, all other independent sources including indg should be disabled.


where iout is the output current of the device (drain current), is is the current through

Csb, and Vs is the source potential. B y manipulating Equations 4.10-4.12, we have:

iout _ 9mb(sCsb + l/Zs) + sCsb{K - gmb) vns sCsb + 1/ZS - K + gmb

Similar to D N C , we define substrate noise coefficient (SNC) as:

\9mb(sCsb + l/Zs) + sCsb{K - gmb)

(4.13)

S N C = t p = V ns sCsb + l/Zs - K + gmb

(4.14)

Consequently, a modified version of the total noise current, including the effect of

substrate noise, would be: 3

^ s = D N C x ^ d + S N C x ^ n s (4.15)

where the first and the second terms on the right-hand side represent the effect of device

and substrate noise, respectively. The final model is the same as Figure 4.1, except that

the noise current source, indg, wil l be modified to indgs, given by Equation 4.15. The reader

may wonder why the final model does not include body effect and Csb. These components

were omitted because it is assumed that they have negligible effect on the transfer function

from the input to the output; nonetheless, their effect in the transfer function from the

substrate to the output is already taken into account by i2

ndgs-

3 It should be noted that here we have assumed that the internal noise sources and the substrate noise are uncorrelated.


4.3 Noise Figure Calculation

The model developed in the previous section can be used to study the effect of substrate

noise on an inductively-degenerated L N A as a sample analog circuit. The purpose of using

such L N A as a benchmark for our analysis is twofold: first, L N A s are among the most

sensitive analog circuits to noise because of the extremely low amplitude of the signal at

their input. 4 Second, this type of L N A is the most commonly used topology in practice;

therefore, it can well represent one of the critical blocks in mixed-signal SoCs. Figure 4.4

shows a generic schematic of such an amplifier.

lout

Figure 4.4: A typical inductively-degenerated L N A .

In this circuit, Lrieg is used to create a real component in the input impedance of the

circuit that can be tuned for input impedance matching and Lg is included to control the

resonance frequency.

In general, the noise factor, F, of an amplifier is defined as:

p _ Total output noise power _ i2

nout(tot) ,^ ^

Output noise due to input source i 2 ,+r,„> / b\J tt/b \ bib )

To calculate inout(tot) and inout(in), we refer to the M O S small-signal model introduced in the

4As an example, the power of GPS signal can be as low as -130dBm [70].


Vir,

Figure 4.5: Small-signal model of an inductively-degenerated L N A .

previous section, based on which, we construct the small-signal model of the inductively-

degenerated L N A as shown in Figure 4.5. Assuming that the amplifier is matched to the

output resistance of the input source, Rs, we have:

V = — (—— Rs + Zin JUJQC, as

1

2RS

vju,0<V u0Cga2RaT ~ 7

(9.\-^ ^nout(in) 9m\ • j^-ns

J

^2nout(in) = {9mQ) C 2

n (4.17)

where ens is the input noise of the L N A (due to Ra), LOQ is the center frequency, and Q is

the quality factor of the input network of the amplifier. Therefore, the noise factor wi l l

be:

F J9mQ) &2

ns "F l^ndgs _ ^ _|_ ^ndgs

(gmQ)2e (gmQ)2e2 (4.18)

Recall ing i2

ndgs from Equat ion 4.15, we have:

F= 1 + D N C x i\d + S N C x v\

(9mQ)2 x e 2

(4.19)


wh ich can be wr i t t en i n the fol lowing form:

F = 1 + D N F ( Q ) + S N F W ) (4.20)

where D N F ( Q ) and S N F ( Q ) are the device and substrate noise factors, respectively. D N F ( Q )

accounts for the effect of in ternal noise sources of the device , 5 whereas S N F ( Q ) shows the

con t r ibu t ion of substrate noise; more specifically, S N F ( Q ) is given by the fol lowing equat ion:

where k is B o l t z m a n n ' s constant and T is the temperature. T h i s equat ion shows the effect

of substrate noise on the noise figure of the L N A . Fur thermore , as w i l l be discussed shortly,

it reveals the trade-off between substrate noise and in t r ins ic device noise m i n i m i z a t i o n .

F igure 4.6 depicts D N F as a funct ion of Q i n a typ ica l L N A i n 0 .18^m technology for

. different values of c. A s defined i n E q u a t i o n 4.17, Q is the qua l i ty factor of the input

network of the L N A . Since Q is inversely p ropor t iona l to Cgs, a lower Q corresponds to

a wider transistor. A s can be seen, for a given c, an o p t i m u m Q exists that yields the

m i n i m u m D N F ( Q ) ; thus, the overall noise figure wou ld also be m i n i m u m (assuming that

there is no substrate noise). However, i n many cases, us ing this o p t i m u m Q leads to a

' large power consumpt ion i n the device; therefore, designers may consider us ing a higher

Q to decrease power consumpt ion , wh ich as imp l i ed by F igure 4.6, entails increased noise

figure from device noise perspective.

T o further s tudy the effect of substrate noise, various L N A s w i t h different Q values

3For the complete equation of DNF(Q) please refer to [69].


| c=0.8j | 0.21 ' 1 1 1 1

0 2 4 6 8 10 Q

Figure 4.6: Normalized device noise factor as a function of Q for different values of c.

were designed in 0.18//m technology. The topology of the circuit was the same as the

one shown in Figure 4.4. A n additional M O S transistor was used as cascode device to

increase the isolation between the input and the output and also reduce Miller effect. To

analyze the effect of substrate noise, it is instructive to study the dependence of S N F

on Q in Equation 4.21. The required data for this study such as the value of parasitic

elements and transconductance of the input device were extracted from simulation results

of the designed L N A s . B y substituting values in Equation 4.14 and using the results in

Equation 4.21, we obtain S N F as shown in Figure 4.7. As depicted in this figure, S N F

appears to be a decreasing function of Q. Indeed, considering the fact that Cgs, gm, and

gmb are inversely proportional to Q, one can show that S N F is a decreasing function of Q.

The behaviour of S N F with respect to Q reveals an important compromise between


substrate noise and device noise minimizat ion. A s shown i n Figure 4.7, SNF(Q) exhibits

an opposite trend as compared to DNF(Q), i.e., substrate noise effect is more significant

at low values of Q, whereas at high values of Q the dominant noise mechanism would be

the intrinsic noise of the device.

Figure 4.7: Normalized substrate noise factor as a function of Q.

To verify the preceding argument, the L N A s were simulated using Agilent Advanced

Design System ( A D S ) simulator. To include substrate noise effect a noise source was

connected to the bulk node of the input transistor and the resulting noise figure was

measured. Figure 4.8 depicts the noise figure for various levels of substrate noise and Qs.

A s can be seen, at low values of Q, substrate noise is dominant; however, as Q increases

the port ion of the noise figure due to substrate noise decreases substantially. O n the other

hand, at high values of Q, device noise starts dominating.


2.5

2

- e - S N = 0 - A - S N = 4 - » - S N = 1 6 - » - S N = 2 5

CQ

o 1.5h

0.5

0. 0 2 4 6

Q 8 10 12

Figu re 4.8: Noise figure as a funct ion of Q . T h e spectral densi ty of substrate noise is given

T h e noise figure as a funct ion of frequency is p lo t ted i n F igure 4.9 for two different

Qs. T h i s figure conveys impor tan t in format ion about the behaviour of the noise figure.

F i r s t , as expected, the effect of substrate noise is less i n F igure 4.9(b) (which corresponds

to a c i rcu i t w i t h a higher Q ) . A n o t h e r impor tan t result is tha t a frequency (fopt) exists

at w h i c h the noise figure i n the presence of substrate noise is almost the same as that

wi thou t any substrate noise.

T o elaborate more on this point , i t should be noted that a l l L N A s were designed

for 1 .5GHz, however, fopt is observed at 1.4GFfz, wh ich means that power ma tch ing and

noise suppression have not occurred at the same frequency. A more careful s tudy of these

figures shows that i n the absence of substrate noise the m i n i m u m noise figure is achieved at

1 .6GHz wh ich is s t i l l different from the center frequency. T h i s discrepancy was expectable

i n V2/Hz.


7

O 1 1 1 1

1 1.2 1.4 1.6 1.8 2 F r e q u e n c y ( G H z )

(a) Noise figure as a function of frequency (Q=1.8).

7

6

0

1 1 1 1

SN=25 /

- SN= 1 6 \ ^ ^ ^ ^ ^ ^ y /

- SN=4 / /

SN=0 \ V /

opt \ ^ / f

^ ^ ^ ^

11 , 1 , ,

1 1.2 1.4 1.6 1.8 2 F r e q u e n c y ( G H z )

(b) Noise figure as a function of frequency (Q=10).

Figure 4.9: Comparison of noise figure for different Qs. (The spectral density of substrate noise is given in V2/Hz.)


because our design method is based on the power matching at center frequency and not

on the noise matching. In fact, this type of behaviour is commonly encountered in LNA

design. Various LNA design methodologies are either based on noise or input matching or

they try to balance these two parameters [69, 70].6 However, as suggested by the results of

this section, the effect of substrate noise can be minimized by compromising the amount

of device noise or power matching.

4 .4 Summary

In this chapter, MOSFET small-signal model was revisited. A new small-signal model

was proposed that accommodates the effects of substrate noise. Based on this model, the

noise performance of an inductively-degenerated L N A was studied.

It was shown that increasing the quality factor of the input network alleviates substrate

noise problem to some extent, but at the same time increases the effect of device noise

sources. Based on the results in this chapter, to achieve the best noise performance

substrate noise effect should be taken into account since it changes the overall noise figure

characteristic of the amplifier, i.e, merely considering the effect of device noise will result

in solutions that may exhibit poor substrate noise performance.

6 In some cases, power consumption requirement is also added to the matching criteria.

63

Chapter 5

E v a l u a t i o n o f R e d u c t i o n M e t h o d s

Substrate noise cannot be eliminated completely, but its deleterious effects can be con

trolled or minimized. Many noise reduction methods have been used by analog designers

to mitigate the influence of the noise; however, the effectiveness of these techniques de-

' pends on a multitude of parameters, such as the properties of the substrate, the circuit's

clocking scheme, etc., that need to be studied in order to implement them properly.

In general, substrate noise reduction methods can be categorized into three different

classes: the first class consists of methods aimed at reducing the noise generated by digital

blocks; the second class focuses on reducing the noise propagated through the substrate,

and the last class tries to design noise-tolerant analog circuits. In this thesis, these classes

will be referred to as noise injection reduction, noise propagation reduction, and noise

reception reduction.

This chapter provides a review of noise reduction techniques. Since each of these

methods can be a topic for a separate research, only a brief introduction to some of them

is given, except for more detailed studies of two popular techniques, namely switching

activity spreading and the use of passive guard-rings (GRs), from the first and the second

classes, respectively.

Chapter 5. Evaluation of Reduction Methods 64

5.1 Noise Injection Reduction

In general, techniques used i n low-power design can be used to reduce swi tch ing noise,

especial ly i f they a t tempt to reduce c i rcui t act ivi ty . However, care should be taken since

i n some cases using low-power techniques can even aggravate the noise [40].

A s an example of a low-power technique, lower power supplies can be used for d ig i t a l

parts (not analog parts) . A lower swing for d ig i t a l nodes decreases the instantaneous

current d rawn from the supply; also use of a larger supply for analog c i rcui ts increases

their relative noise marg in [56]. One disadvantage of using this technique is that it m a y

cause increased delay i n logic gates, wh ich reduces the speed of the c i rcui t ; however, i t

, should be noted that i n a logic b lock not a l l the gates need to swi tch quick ly ; therefore,

less c r i t i ca l gates can be operated w i t h lower supply voltages. A n o t h e r disadvantage of

this me thod is the ex t ra rou t ing and package pins required for different supply lines on

the chip , wh ich are not favourable i n integrated circui ts .

Swi t ch ing ac t iv i ty spreading is another technique that changes the supp ly current

' waveform by in t roduc ing delays into the clock d i s t r ibu t ion network. T h i s w i l l spread

the swi tch ing ac t iv i ty of logic gates i n t ime, thus reducing the number of s imul taneously

swi tch ing gates. Since this technique introduces design complex i ty i n large d ig i t a l c i rcui ts ,

the idea can be appl ied on ly to those parts of the c i rcui t that contr ibute the most to

the noise, such as blocks that drive large capaci t ive loads. Fur thermore , a l though this

' technique has been proven useful i n the t ime-domain , its efficiency for R F appl icat ions ,

i.e., i n frequency-domain, needs to be verified.


5.1.1 Switching Activity Spreading

Figure 5.1 illustrates the idea of switching activity spreading 1 (SAS). In staggered digital

circuits, part of the switching gates wil l be triggered with a properly delayed clock with

respect to the rest of the circuit; therefore, the number of simultaneously switching gates

wil l be reduced.

Input Clock

Clock Region I

Clock Region III

Figure 5.1: Switching activity spreading.

To investigate the effectiveness of this technique, the following experiment was per

formed. First, two chain of inverters were simultaneously switched, and the noise wave

form was observed at the bulk node of a single transistor used as the noise sensor. Next,

the same experiment was repeated by applying SAS, i.e., the clock signal of one of the

chains was delayed by \ of the clock period with respect to the other one. The results of

both experiments are shown in Figure 5.2. As can be seen in Figure 5.2(a), the peak value

of the noise has decreased by almost a factor of 2.

In addition to time-domain waveforms, the frequency content of the noise in both cases

is shown in Figure 5.2(b). This graph reveals an important point; i.e., even though the

noise frequency content has considerably decreased at some frequencies, this result is not

a general rule. For example in Figure 5.2(b), the noise content at 650MHz has remained

1Also known as activity staggering.


20 Time (nsec)

400 600 Frequency (MHz)

1000

(a) Noise waveform in time-domain. (b) Frequency content of the noise.

Figure 5.2: Effect of SAS in time and frequency domains.

almost unchanged after applying SAS. Therefore, care should be taken in R F applications

to make sure that SAS decreases the in-band noise.

5.2 N o i s e P r o p a g a t i o n R e d u c t i o n

Another noise reduction method is to prevent the noise from propagating through the

substrate. Two strategies can be used: one is to increase the attenuation of the noise

path, and the other one is to block the noise propagation. The simplest reduction scheme

to increase the attenuation of the noise path is to increase the physical distance between

the digital and analog circuitry. The efficiency of this technique was discussed in Chapter 3,

where it was shown that the effectiveness of physical isolation is limited to lightly-doped

substrates; moreover, this technique involves wasting of precious silicon area; therefore,

several alternative methods have been exploited. Many of these techniques, such as the

use of GRs , trenches, buried n-wells are studied in the literature [32, 65, 71]. It should


be noted that all of these techniques, except for passive guard-rings, require additional

process features that might not be available or economically viable in all technologies. So

far, passive G R s have been the most commonly used technique due to their effectiveness

and relative simplicity; therefore, we wil l review their properties in more detail.

5.2.1 Passive Guard-Rings

Passive guard-rings are protective structures located around either the noise generating

or sensitive blocks and are connected to dedicated supplies. There are two types of GRs:

p + and n-well GRs , which operate based on totally different principles, although their

purpose is the same.

p + G R provides a low-impedance path to the ground so that the noise travelling

through the substrate is directed mainly to the ground before reaching sensitive devices.

, On the other hand, n-well G R tends to increase the impedance of the noise path, which wil l

effectively push the noise into deep parts of the substrate and provide a higher impedance

path or equivalently, more attenuation. In both cases, the G R is more effective if most

of the noise travels through the surface of the chip. Some of the following questions may

arise during the course of G R design:

• How do the properties of the G R change with frequency?

• What are the optimum dimensions of the G R ?

• Where should it be placed?

• Should the G R fully enclose the noisy or sensitive part?


• How does the substrate type affect the efficiency of the G R ?

SeismIC simulation results presented in the following sections reveal that in all cases

the use of G R s significantly helps decreasing the amount of noise; therefore, passive G R s

are an effective way to reduce substrate noise. To study G R properties, a simple lumped

model representation of p + and n-well G R s wil l be used, as shown in Figure 5.3. In this

figure, Rsub represents the substrate resistance, RGR is the resistance of the G R , RA and

CA are the resistance and capacitance connecting the bulk of the sensitive device to the

substrate, and RL is the lateral resistance between G R and the noise sensing node. In the

' n-well G R model (shown in Figure 5.3(b)) CQR is added to reflect the capacitance of the

n-well to the substrate.

Digital P+ GR Analog p+ GR

p~ substrate

(a) p + G R enclosing sensitive devices.

Digital n-woll GR Analog n-woll GR

I p substrate

(b) n-well GR enclosing sensitive devices.

Figure 5.3: Lumped model of G R s in lightly-doped substrates.

It can be shown that in p + GRs , the lower the impedance of the G R (RGR) the better


the noise suppression performance. In fact, the impor tan t parameters, wh ich determine

the efficiency of the G R , are the ratios of the G R impedance to the impedance of the

substrate and the impedance coupl ing the sensitive node to the substrate. O n the other

hand , i n n-wel l G R s , a higher G R impedance is more favourable, because the increased

impedance w i l l push the noise to deep port ions of the substrate, hence increasing the

overal l impedance of the noise pa th and consequently, increase the a t tenuat ion.

Frequency Dependence of GR Properties

T h e G R mode l in t roduced i n the previous section suggests that i n p + G R s , the effectiveness

of the G R decreases as the frequency increases because the ra t io of the impedance of the

G R to the impedance of the sensitive node increases; therefore, less noise is di rected to

the ground th rough the G R . O n the other hand , i n the case of n-well G R , this might not

be true because two compet ing mechanisms exist that control the impedance rat io . W h i l e

the coup l ing of sensitive nodes to the substrate increases at higher frequencies, at the same

, t ime the impedance of the G R decreases, wh ich can effectively decrease the impedance

rat io . These arguments were investigated us ing Se ismIC s imula t ion results for a chain of

inverters. F igure 5.4 shows s imula t ion results of the amount of noise a t tenuat ion for various

G R arrangements. T o compare the effectiveness of G R s , the amount of add i t iona l i so la t ion

provided by each G R configurat ion as a funct ion of frequency is shown i n F igure 5.5, where

• the curve marked as ' N o i so la t ion ' i n F igure 5.4 is used as the reference. 2

A s shown i n F igure 5.5, whi le the performance of n-wel l G R s has improved w i t h i n -

2 In this case the noise attenuation is due merely to the physical separation of the noisy and sensitive parts.


-a -n-we l l GR 10" - © - p + a n d n-well "

0 500 1000 1500 2000 2500 Frequency (MHz)

Figure 5 . 4 : Attenuation as a function of frequency for different G R arrangements.

creasing frequency, for the other G R the results are the opposite. Another interesting

point in the model for n-well GRs is that since at high frequencies the impedance due to

CQR decreases, n-well G R can act as a sink path to A C ground. As a result, one can think

of n-well GRs as p + GRs at very high frequencies. This argument is in agreement with

Figure 5 . 5 where at high frequencies the two plots of p + and n-well G R tend to converge.

In all cases, it is important to connect the G R to a dedicated supply; otherwise the G R

itself can provide an extra path for noise injection into the substrate.

The results shown in Figure 5 . 5 contrast with the previously reported results in [ 3 4 ]

that the efficiency of p + GRs is independent of frequency. The conflict comes from the

fact that in the experiment in [ 3 4 ] a simple substrate contact was used as the noise sensor

and no capacitive component was taken into account; thus the isolation did not change


35

- ^ - p + GR only — a — n-well GR only - • - B o t h

500 1000 1500 Frequency (MHz)

2000 2500

Figure 5.5: Additional attenuation provided by GRs as a function of frequency,

with frequency.

Effect of GR Width

Figure 5.6 presents the isolation provided by p + G R as a function of its width. As can be

seen, the isolation increases monotonically as the width of the G R increases, suggesting

that the wider the G R the lower the noise. These results could be predicted from the G R

model because, as the width of the G R increases, the impedance of the noise return path

to ground decreases, and so does the propagated noise.

Effect of GR Placement

Another important property to observe is the effect of the distance of the G R from the noise

generation point. Figure 5.7(a) depicts the simulation results of the testbench introduced


10 15 20 25 GR width (urn)

30

Figure 5.6: G R at tenuat ion as a function of w i d t h .

20 40 60 80 Distance from noise generator(u.m)

100 20 40 60 80 Distance from noise generator(n.m)

100

(a) Results for single inverter. (b) Results for a more complicated digital

circuit.

F igure 5.7: Effect of G R placement.


in Chapter 3, using a fixed-width G R at different distances from the noise generator. The

physical separation between analog and digital circuits in this figure is lOOyum. As can be

seen, more attenuation is achieved when the G R is located closer to the sensitive device.

The worst isolation is achieved when the G R is placed halfway between the analog and

digital blocks. Figure 5.7(b) illustrates the results of the same experiment using a more

complicated digital circuit. The same behaviour is observed, but the location of the local

minimum has changed, which is due to the change in the amount of the total capacitance

in the digital circuit.

Effect of G R shape

Since the only operation of the p + G R is to provide a path to a stable supply, one may

wonder if it is necessary to implement a full ring G R , while open guards may have the

desired performance. To show the effect of G R shape, three different GRs (shown in

' Figure 5.8) were examined using a chain of inverters circuit as a benchmark. Table 5.1

lists the results.

Sensitive N M O S \^45pm—\

20 firn

Without protection Protection wi th a single barrier

(«— 45/xm—*( 45/im—-\

G R with one side removed Full G R

Figure 5.8: Different G R shapes.


P r o t e c t i o n Scheme A t t e n u a t i o n ( d B )

Without protection 27.0

Protection with barrier 39.8

G R with one side removed 45.2

Full-ring G R 46.6

Table 5.1: Noise attenuation using GRs with different shapes.

As shown in Table 5.1, the amount of isolation provided by a full G R is more than a

single barrier; however, even using a barrier has a significant effect on the amount of noise

propagation; therefore, one may consider using a barrier instead of a full-ring G R to save

area in certain applications.

Effect o f subs t ra te t ype

Section 3.2 discussed that noise propagation properties through the substrate depend

on the type of the substrate and its characteristics. Since the performance of G R s also

depends on the impedance of the paths in the substrate and the G R , it is expected that

the substrate type plays an important role in the efficiency of GRs .

Although Figure 5.7(a) shows that the placement of the G R is important in its isola

tion properties, this does not hold for epitaxial substrates. It should be noted that G R s

are more effective in cases in which most of the noise travels through the surface of the

chip; however, in epitaxial substrates, due to the low-resistivity of the bulk, the main path

for noise propagation is through the deep portion of the substrate. In effect, increasing


, the distance between the points does not increase the attenuation, as was observed be

fore. The independence of the attenuation from the distance in epitaxial substrates is also

inferred from the G R model in epitaxial substrates, as shown in Figure 5.9. As can be

seen, only vertical impedances are important; therefore, increasing the distance does not

change the G R ' s noise attenuation. 3

Digital n-weil G R Analog n-woll G R

Heavily-doped bulk. •

(a) p + G R enclosing sensitive devices.

Digital P + G R Analog p+ G R

Heavily-doped bulk

(b) n-well G R enclosing sensitive devices.

Figure 5.9: Lumped model of GRs in epitaxial substrates.

Simulation results also verify the previous discussion on the dependence of attenuation

on the distance in various substrates. The results are shown in Figure 5.10. As can be seen,

, while the attenuation in lightly-doped substrates decreases monotonically as the distance

increases, in epitaxial ones increasing the distance does not affect the attenuation.

3 I t should be noted that all the models used in this chapter apply only to moderate and large separations between analog and digital blocks. At very short distances the effect of lateral surface resistances should also be taken into account.


14

s r 1 2

§ 1 0 o co

c o ro c CD

<

T —1

-e- Epitaxial - a - Lightly-doped

-

-e 0 0 (

0 10 20 30 Distance (urn)

40 50

Figure 5.10: Effect of substrate type.

5.3 N o i s e R e c e p t i o n R e d u c t i o n

This class of reduction techniques is typically used by analog designers to increase the

immunity of their circuits to substrate noise. The most popular technique is the use of

differential structures. Since substrate noise is mostly considered as common-mode noise,

ideally it can be suppressed by differential signalling; however, due to the mismatches and

the delay of noise propagation between the two inputs of the differential stage, they are not

able to fully remove substrate noise. To increase the noise rejection capability, the layout

must have the same parasitics coupling to each of the two differential branches, which

requires a symmetric layout that can be achieved either by mirror or common-centroid

symmetry.

On-chip decoupling capacitor is another technique that can be used to reduce both


noise generation and reception [72]. This technique is used both in digital and analog

circuits to decouple power supply and ground lines. The additional capacitor placed

• between supply and ground, can act as an extra source of charge for transient currents in

switching parts; therefore, a smaller transient current wil l be drawn from supplies; hence,

less noise is induced on power lines.

As discussed in Chapter 3, use of P M O S transistors for signal handling parts, such as

differential pair input transistors, and current mirrors wi l l decrease the amount of noise

' reception because these devices are further isolated from the substrate by the underlying

n-well. Finally, using a different supply line for analog circuits wil l decouple them from

the noise on the supply lines of digital blocks.

5.4 S u m m a r y

In this chapter, various noise reduction techniques were introduced and discussed. Switch

ing activity spreading was studied in time and frequency domains. It was shown that even

though this technique is useful in time-domain, for R F applications it might not be help

ful, since the frequency content of the noise at specific frequencies may remain unchanged

' after applying this technique.

In addition to SAS, passive G R s were also reviewed in detail, and the impact of several

parameters on their effectiveness was investigated. Lumped models for GRs in different

substrates were introduced and used to justify the simulation results. It was shown that,

while the isolation property of p + GRs deteriorates as the frequency increases, n-well G R s

might show an opposite trend; i.e., depending on the layout and structure of the circuit


the effectiveness of this type of G R may improve. Furthermore, it was shown that at high

frequencies, n-well GRs can act as p + G R . Finally, some general strategies for designing

noise-tolerant analog circuits were given.

79

Chapter 6

C o n c l u s i o n a n d F u t u r e W o r k

6 .1 C o n c l u s i o n

In this thesis, substrate noise, as one of the main obstacles in highly-integrated circuits,

was studied from three different aspects. First, the behaviour of the noise was explored in

the time and frequency domains. Internal and external noise sources were considered and it

was shown that external noise sources quickly dominate the overall noise as the inductance

in power supply lines increases. The dependence of noise on a variety of parameters such

as switching time and frequency of operation were also analyzed. The dependence of

the noise behaviour on the substrate type was extensively studied and the differences

between noise propagation properties in two most commonly used substrates, lightly-

doped and epitaxial, were analyzed. The difference between P M O S and N M O S devices

was also investigated and it was shown that, P M O S devices exhibit superior substrate

noise performance as compared to N M O S transistors owing to the additional isolation

provided by their underlying n-well.

Second, the effect of substrate noise on a typical L N A was investigated from a circuit-

level point of view rather than the signal-level approach exploited by previous works. A

new M O S F E T model that includes substrate noise effects was introduced. It was shown

Chapter 6. Conclusion and Future Work 80

that, while with lowering the quality factor of the input network the noise figure of the L N A

improves from the intrinsic device noise perspective, it deteriorates due to the effect of

the substrate noise; therefore, there is a compromise between substrate noise and intrinsic

device noise minimization inductively-degenerated L N A s .

Third , the properties of passive GRs , as the most popular noise reduction technique,

were studied. It was shown that in contrast to previous results, the isolation efficiency of

n-well G R s can improve by increasing frequency. In fact, an n-well G R at high frequencies

can act as a p + G R . Furthermore, the dependence of the additional isolation provided

by GRs on several parameters such as the width, placement, and shape of the G R were

investigated.

6 . 2 F u t u r e W o r k

Experimental verification of the approach proposed in Chapter 4 is a further step that

should be taken as future work. Another possible extension to this work can be the study

of the performance degradation of more analog circuits using the proposed M O S F E T

small-signal model. Furthermore, in addition to inductively-degenerated L N A , many other

L N A configurations exist that require further research to identify the least sensitive L N A

architecture to substrate noise.

In the software and C A D tool area, there are many opportunities that await explo

ration. The only commercially available substrate noise analysis tool is Substrate Noise

Analyst by Cadence™, performance of which is mostly limited to digital circuits, i.e., the

spectral analysis of substrate noise, which is crucial to noise analysis, is not addressed in

Chapter 6. Conclusion and Future Work 81

this tool ; therefore, there is a need for a too l w i t h R F capabil i t ies . T h e current too l does

not a l low for simultaneous s imulat ions of noise figure and substrate noise analysis; as a

result, development of a too l w i t h the capab i l i ty of cos imula t ion of R F and substrate noise

w i l l be extremely valuable to analog designers.

T h i s work has not addressed a l l possible noise reduct ion techniques; however, i n addi

t i on to passive G R s , many other techniques exist that may be i n some cases more efficient

than passive guard-rings; the s tudy of such techniques w i l l also be a p romis ing research

d i rec t ion .

82

B i b l i o g r a p h y

[1] A . A . A b i d i , " R F C M O S comes of age," IEEE J. Solid-State Circuits, vo l . 39, pp. 549-561, A p r . 2004.

[2] F . O . E y n d e , J . - J . Schmit , V . Char l i e r , R . Alexandre , C . S tu rman , K . Coffin, B . Mol lekens , J . C r a n i n c k x , S. Ter r i jn , A . Monte ras te l l i , S. Beerens, P . Goetscha lckx , M . Ingels, D . Joos, S. Guncer , and A . Pon t iog lu , " A fully-integrated single-chip S O C for B lue too th , " i n ISSCC Dig. Tech. Papers, Feb. 2001, pp. 196-197, 446.

[3] D . K . Su , M . Zargar i , P . Y u e , S. R a b i i , D . Weber , B . K a c z y n s k i , S. M e h t a , K . S ingh , S. M e n d i s , and B . A . Wooley, " A 5 G H z C M O S transceiver for I E E E 802.11a wireless L A N , " i n ISSCC Dig. Tech. Papers, Feb. 2002, pp. 92-93, 449.

[4] T . Fujisawa, J . Hasegawa, K . Tsuchie , T . Shiozawa, T . Fu j i ta , K . Sek i -Fukuda , T . H i -gashi, R . B a n d a r , N . Yosh ida , K . Shinohara , T . Watanabe , H . Ha tanoz , K . Noguchiz , T . Sai to , Y . Unekawa, and T . A i k a w a , " A single-chip 802.11a M A C / P H Y w i t h a 32b R I S C processor," i n ISSCC Dig. Tech. Papers, Feb. 2003, pp. 144-145, 483.

[5] W . K l u g e , L . Dathe , R . Jaehne, S. Ehrenre ich , and D . Eggert , " A 2 . 4 G H z C M O S transceiver for 802.11b wireless L A N s , " i n ISSCC Dig. Tech. Papers, Feb. 2003, pp. 360-361.

[6] H . Ishikuro, M . H a m a d a , K . - I . A g a w a , S. K o u s a i , H . K o b a y a s h i , D . M . Nguyen , and F . H a t o r i , " A single-chip C M O S B l u e t o o t h transceiver w i t h 1 . 5 M H z I F and direct modu la t i on t ransmit ter ," i n ISSCC Dig. Tech. Papers, Feb. 2003, pp. 94-95, 480.

[7] T . K a d o y a m a , N . Suzuk i , N . Sasho, H . I izuka, I. Nagase, H . U s u k u b o , and M . K a t a k u r a , " A complete single-chip G P S receiver w i t h 1.6-V 2 4 - m W radio i n 0.18yum C M O S , " i n IEEE Symp. on VLSI Circuits, Digest of Tech. Papers, June 2003, pp. 135-138.

[8] G . Gramegna , M . Franc io t ta , V . M a n d a r a , N . Bel lantone, M . V a i a n a , M . Paporo , M . L o s i , S. Das , and P . M a t t o s , " 2 3 m m 2 single-chip 0.18/xm C M O S G P S receiver w i t h 28mW-4.1mm2 radio and C P U / D S P / R A M / R O M , " i n Proc. of Custom Integrated Circuits Conference, O c t . 2004, pp. 81-84.

[9] K . M u h a m m a d , D . L e i p o l d , B . Staszewski , Y . - C . H o , C . H u n g , K . M a g g i o , C . Fernando, T . Jung , J . Wa l lbe rg , J . -S. K o h , S. John , I. Deng , O . M o r e i r a , R . Staszewski , R . K a t z , and O . F r i edman , " A discrete-t ime B l u e t o o t h receiver i n a 0.13^im d ig i t a l C M O S process," i n ISSCC Dig. Tech. Papers, Feb. 2004, pp. 268-269, 527.

Bibliography 83

[10] H . D a r a b i , S. K h o r r a m , Z . Zhou , T . L i , B . Marho l ev , J . C h i u , J . Cas taneda , E . C h e i n , S. A n a n d , S. W u , M . P a n , R . Rofoogaran, , H . K i m , P . Le t t i e r i , B . Ib rah im, J . R a e l , L . T r a n , E . Geronaga, H . Y e h , T . Frost , J . Trachewsky, and A . Rofougaran, " A fully integrated S o C for 802.11b i n 0 .18/ im C M O S , " i n ISSCC Dig. Tech. Papers, Feb. 2005, pp. 96-97, 586.

[11] S. M e h t a , D . Weber , M . Terrovi t i s , K . Onodera , M . M a c k , B . K a c z y n s k i , H . Samavat i , S. Jen , W . S i , M . Lee, K . S ingh , S. Mend i s , P . Hus ted , N . Zhang , B . M c F a r l a n d , D . S u , T . M e n g , and B . Wooley, " A n 8 0 2 . l l g W L A N S o C , " i n ISSCC Dig. Tech. Papers, Feb. 2005, pp. 94-95, 586.

[12] D . Sahu, A . Das , Y . Darwhekar , S. Ganesan, G . Ra jendran , R . K u m a r , C . B G , A . G h o s h , A . Gaurav , K . T , A . G o y a l , S. Bhagavatheeswaran, K . M . low, N . Y a n d u r u , and S. Venka t raman , " A 90nm C M O S single-chip G P S receiver w i t h 5 d B m out-of-band I I P 3 2 .0dB N F , " i n ISSCC Dig. Tech. Papers, Feb. 2005, pp. 308-309, 600.

[13] A . M o l n a r , R . M a g o o n , G . Hatcher , J . Zachen, W . Rhee, M . D a m g a a r d , W . D o m i n o , and N . V a k i l i a n , " A single-chip quad-band ( 8 5 0 / 9 0 0 / 1 8 0 0 / 1 9 0 0 M H z ) direct-conversion G S M / G P R S R F transceiver w i t h integrated V C O s and fract ionally synthesizer," i n ISSCC Dig. Tech. Papers, Feb. 2002, pp. 232-233, 462.

[14] T . M i s a w a , J . E . Iwersen, L . J . Loporcaro , and J . G . R u c h , "Single-chip per channel codec w i t h filters u t i l i z ing A — E modula t ion , " IEEE J. Solid-State Circuits, vo l . 16, pp. 333-341, A u g . 1981.

[15] A . V a i d y a n a t h , B . Thoroddsen , and J . L . P r ince , "Effect of C M O S driver load ing condit ions on simultaneous swi tch ing noise," IEEE Trans. Adv. Packag., vo l . 17, N o v . 1994.

[16] S. R . V e m u r u , "Accura te simultaneous swi tch ing noise es t imat ion inc lud ing veloci ty-sa tura t ion effects," IEEE Trans. Adv. Packag., vo l . 19, pp. 344-349, M a y 1996.

[17] T . J . Schmerbeck, R . A . R iche t t a , and L . D . S m i t h , " A 2 7 M H z m i x e d ana log /d ig i t a l magnet ic recording channel D S P us ing pa r t i a l response s ignal l ing w i t h m a x i m u m l ike l ihood detection," i n ISSCC Dig. Tech. Papers, Feb. 1991, pp. 136-137.

[18] D . K . Su , M . J . L o i n a z , S. M a s u i , and B . A . Wooley, "Expe r imen ta l results and mode l ing techniques for substrate noise i n mixed-s ignal integrated c i rcui ts ," IEEE J. Solid-State Circuits, vo l . 28, pp. 420-430, A p r . 1993.

[19] M . van Heiningen, J . Compie t , P . W a m b a c q , S. Donnay, M . G . E . Engels , and I. Bolsens, "Ana lys i s and exper imenta l verif icat ion of d ig i t a l substrate noise generat ion for epi-type substrates," IEEE J. Solid-State Circuits, vo l . 35, pp. 1002-1008, J u l y 2000.

[20] M . Bada rog lu , S. Donnay, H . J . D . M a n , Y . A . Z . G . G . E . Gie len , W . Sansen, T . Fonden, and S. Signel l , " M o d e l i n g and exper imenta l verif icat ion of substrate noise generation i n a 220-Kgates W L A N system-on-chip w i t h mul t ip le supplies," IEEE J. Solid-State Circuits, vo l . 38, pp. 1250-1260, J u l y 2003.

Bibliography 84

[21] M . X u , D. K . Su , D . K . Shaeffer, T . H . Lee, and B . A . Wooley, "Measur ing and m o d e l i n g t h e effects of substrate noise on the L N A for a C M O S G P S receiver," IEEE J. Solid-State Circuits, vo l . 36, pp. 473-485, M a r . 2001.

[22] X . Aragones and A . R u b i o , "Expe r imen ta l compar ison of substrate coup l ing us ing different wafer types," IEEE J. Solid-State Circuits, vo l . 34, pp. 1405-1409, Oc t . 1999.

[23] F . Herze l and B . R a z a v i , " A s tudy of osci l lator j i t t e r due to supply and substrate noise," IEEE Trans. Circuits Syst. II, vo l . 46, pp. 56-62, Jan . 1999.

[24] Y . Z inz ius , G . Gie len , and W . Sansen, " A n a l y z i n g the impac t of substrate noise on embedded analog-to-digi ta l converters," i n Proc. of Int. Conf. on Circuits and Systems for Communications, June 2002, pp. 82-85.

[25] T . B l a l a c k and B . A . Wooley, "The effects of swi tch ing noise on an oversampl ing A / D converter," i n ISSCC Dig. Tech. Papers, Feb. 1995, pp. 200-201.

[26] N . K . Verghese and D . J . A l l s t o t , "Veri f icat ion of R F and mixed-s ignal integrated circui ts for substrate coupl ing effects," i n Proc. of Custom Integrated Circuits Conference, M a y 1997, pp. 363-370.

[27] J . P . Cos t a , M . C h o u , and L . M . Si lve i ra , "Efficient techniques for accurate mode l ing and s imula t ion of substrate coupl ing i n mixed-s ignal ICs , " IEEE Trans. Computer-Aided Design, vo l . 18, pp. 597-607, M a y 1999.

[28] R . Gha rpu rey and E . C h a r b o n , "Substrate coupl ing: model ing , s imula t ion and design perspective," i n Proc. of Int. Symp. on Quality of Electronic Design, M a r . 2004, pp. 283-290.

[29] P . M i l i o z z i , L . C a r l o n i , E . C h a r b o n , and A . Sangiovanni -Vincente l l i , " S U B W A V E : a methodology for model ing d ig i t a l substrate noise inject ion i n mixed-s ignal ICs , " i n Proc. of Custom Integrated Circuits Conference, M a y 1996, pp. 385-388.

[30] K . M a k i e - F u k u d a , S. M a e d a , T . Tsukada , and T . M a t s u u r a , "Substrate noise reduc t ion using active guard band filters i n mixed-s ignal integrated c i rcui ts ," i n IEEE Symp. on VLSI Circuits, Digest of Tech. Papers, June 1995, pp. 33-34.

[31] M . S. Peng and H . - S . Lee, "S tudy of substrate noise and techniques for m i n i m i z a t i o n , " IEEE J. Solid-State Circuits, vo l . 39, pp. 2080-2086, Nov . 2004.

[32] J . -P . R a s k i n , A . V i v i a n i , D . F landre , and J . -P . Col inge , "Substrate crosstalk reduct ion us ing S o l technology," IEEE Trans. Electron Devices, vo l . 44, pp. 2252-2261, Dec. 1997.

[33] J . B r i a i r e and S. K i r s c h , "Pr inc ip les of substrate crosstalk generation i n C M O S circuits ," IEEE J. Solid-State Circuits, vo l . 19, pp. 645-653, June 2000.

[34] K . Joardar , " A simple approach to mode l ing crosstalk i n integrated c i rcui ts ," IEEE J. Solid-State Circuits, vo l . 29, pp. 1212-1219, Oc t . 1994.

Bibliography 85

T . B la l ack , J . L a u , F . J . R . Clement , and B . A . Wooley, "Expe r imen ta l results and mode l ing of noise coupl ing i n a l igh t ly doped substrate," i n Digest of Technical Papers International Electron Devices Meeting, 1996, pp. 623-626.

S. D o n n a y and G . Gie len , Eds . , Substrate Noise Coupling in Mixed-Signal ASICs. Norwe l l , M A : K l u w e r A c a d e m i c Publ ishers . , 2003.

A . L . L . P u n , T . Yeung , J . L a u , J . R . Clement , and D . K . S u , "Substrate noise coupl ing th rough planar sp i ra l inductor ," IEEE J. Solid-State Circuits, vo l . 33, pp. 877-884, June 1998.

J . Hui j s ing , R . van de Plassche, and W . Sansen, Eds . , Analog Circuit Design. N o r w e l l , M A : K l u w e r A c a d e m i c Publ ishers . , 1999.

M . Naga ta , M . Fukazawa, N . H a m a n i s h i , M . Sh ioch i , T . L i d a , J . Watanabe , Y . M u r a s a k a , and A . Iwata, "Substrate integr i ty beyond 1 G H z , " i n ISSCC Dig. Tech. Papers, Feb. 2005, pp. 266-267, 597.

X . Aragonez , J . L . Gonzalez , and A . R u b i o , Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs. Norwe l l , M A : K l u w e r A c a d e m i c Publ ishers . , 1999.

R . Senth ina than and J . P r ince , " A p p l i c a t i o n specific C M O S output dr iver c i rcu i t design techniques to reduce simultaneous swi tch ing noise," IEEE J. Solid-State Circuits, vo l . 28, pp. 1383-1388, Dec. 1993.

J . Catrysse , "Measured d i s tor t ion of the ouptput-waveform of an integrated O p - A m p due to substrate noise," IEEE Trans. Electromagn. Compat., vo l . 37, pp. 310-312, M a y 1995.

P . H e y d a r i , "Ana lys i s of the P L L j i t te r due to power /g round and substrate noise," IEEE Trans. Circuits Syst. I, vo l . 51, pp. 2404-2416, Dec. 2004.

Y . Z inz ius , G . Gie len , and W . Sansen, " M o d e l i n g the impac t of d ig i t a l substrate noise on embedded regenerative comparators ," i n Proc. of Int. Conf. on Circuits and Systems for Communications, Sept. 2003, pp. 253-256.

N . K . Verghese, D . J . A l l s t o t , and M . A . Wolfe, "Ver i f ica t ion techniques for substrate coupl ing and their appl ica t ion to mixed-s ignal I C design," IEEE J. Solid-State Circuits, vo l . 31, pp. 354-365, M a r . 1996.

E . C h a r b o n , R . Gharpurey, P . M i l i o z z i , R . G . Meyer , and A . Sangiovanni -Vincen te l l i , Eds . , Substrate Noise Analysis and Optimization for IC Design. Norwe l l , M A : K l u w e r A c a d e m i c Publ ishers . , 2001.

S P A C E layout to c i rcui t extractor , Delft Un ive r s i ty of Technology. [Online]. Ava i l ab le : h t tp : / /www.space . tude l f t .n

(2002) Se i smIC Users ' G u i d e by Cadence Des ign Systems.

http://www.space.tudelft.n

Bibliography 86

[49] N . K . Verghese, T . J . Schmerbeck, and D . J . A l l s t o t , Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits. N o r w e l l , M A : K l u w e r A c a d e m i c Publ ishers . , 1995.

[50] M . van Heiningen, M . Badarog lu , S. Donnay, G . G . E . G ie len , and H . J . D . M a n , "Substrate noise generation i n complex d ig i t a l systems: efficient mode l ing and s imu la t ion methodology and exper imental verif icat ion," IEEE J. Solid-State Circuits, vo l . 37, pp. 1065-1072, A u g . 2002.

[51] S. M i t r a , R . A . Rutenbar , L . R . Car ley, and D . J . A l l s t o t , " A methodology for r ap id es t imat ion of substrate-coupled swi tch ing noise," i n Proc. of Custom Integrated Circuits Conference, M a y 1995, pp. 129-132.

[52] E . F . M . Albuquerque and M . M . S i lva , "Eva lua t ion of substrate noise i n C M O S and low-noise logic cells," i n Proc. of IEEE Int. Symp. on Circuits and Systems, M a y 2001, pp. 750-753.

[53] , " A compar ison by s imula t ion and by measurement of the substrate noise generated by C M O S , C S L , and C B L d ig i t a l c i rcui ts ," IEEE Trans. Circuits Syst. I, vo l . 52, pp. 734-741, A p r . 2005.

[54] D . J . A l l s t o t , S . - H . Chee, S. K i a e i , and M . Shrivastawa, "Folded source-coupled logic vs. C M O S stat ic logic for low-noise mixed-s ignal ICs , " IEEE Trans. Circuits Syst. I, vo l . 40, pp. 553-563, Sept. 1993.

[55] K . Leung , "Con t ro l l ed slew rate output buffer," i n Proc. of Custom Integrated Circuits Conference, M a y 1998, pp. 551-554.

[56] T . B la l ack , "Swi tch ing noise i n mixed-s ignal integrated circui ts ," P h . D . dissertat ion, Stanford Univers i ty , 1997.

[57] N . Verghese, "Noise coupl ing i n mixed- s igna l / r f socs," i n Visual Supplement to ISSCC Digest of Technical Papers, Feb. 2004, pp. 729-733.

[58] S. P o n n a p a l l i , N . Verghese, W . K . C h u , and G . C o r a m , "Prevent ing a noisequake [substrate noise analysis]," IEEE Circuits and Devices Magazine, vo l . 17, pp. 19-28, Nov . 2001.

[59] K . T . T a n g and E . G . F r iedman , "Simultaneous Swi t ch ing Noise i n O n c h i p C M O S Power D i s t r i b u t i o n Networks ," IEEE Trans. VLSI Syst, vo l . 10, pp . 487-493, A u g . 2002.

[60] T . Sakura i and A . R . Newton , "Alpha -Power L a w M O S F E T M o d e l and its A p p l i ca t ion to C M O S Inverter Delay and other Formulas ," IEEE J. Solid-State Circuits, vo l . 25, pp. 584-594, A p r . 1990.

[61] M . Hekma t , S. M i r a b b a s i , and M . Hashemi , " G r o u n d Bounce C a l c u l a t i o n due to Simultaneous Swi t ch ing i n Deep Sub-mic ron Integrated C i r cu i t s , " i n Proc. of IEEE Int. Symp. on Circuits and Systems, M a y 2005.

Bibliography 87

[62] L . D i n g and P. M a z u m d e r , "Accura te es t imat ing simultaneous swi tch ing noise by using appl ica t ion specific device model ing ," i n Proc. of Design Automation and Test in Europe, M a r . 2002, pp. 1038-1043.

[63] M . H e k m a t and S. M i r a b b a s i , "Single chip noise coupl ing analysis," Un ive r s i t y of B r i t i s h C o l u m b i a , Vancouver , C a n a d a , Tech. Rep . , Dec . 2004.

[64] B . E lka reh , Fundamentals of Semiconductor Processing Technologies. Norwe l l , M A : K l u w e r A c a d e m i c Publ ishers , 1999.

[65] R . B . M e r r i l l , W . M . Y o u n g , and K . Brehmer , "Effect of substrate mate r ia l on crosstalk i n m i x e d ana log /d ig i t a l integrated c i rcui ts ," i n Digest of Technical Papers International Electron Devices Meeting, 1994, pp. 433-436.

[66] B . R a z a v i , Design of Integrated Circuits for Optical Communications. M c G r a w H i l l , 2003.

[67] H . L a n and R . D u t t o n , "Synthesized compact models ( S C M ) of substrate noise coup l i n g analysis and synthesis i n mixed-s ignal ICs , " i n Proc. of Design Automation and Test in Europe, Feb. 2003, pp. 836-841.

[68] M . X u , "Substrate noise i n mixed-s ignal integrated circui ts ," P h . D . dissertat ion, S tanford Univers i ty , 2001.

[69] M . Perro t t . (2005, Feb.) M I T ' s OpenCourseWare . [Online]. Ava i l ab le : h t t p : / / o c w . m i t . e d u / O c w W e b / E l e c t r i c a l - E n g i n e e r i n g -and-Compute r -Sc ience /6 -976High-Speed-Communica t ion-Ci rcu i t s -and-Sys temsSpr ing2003/ CourseHome / index, h t m /

[70] D . K . Shaeffer and T . H . Lee, " A 1.5-V, 1 .5-GHz C M O S low noise amplifier ," IEEE J. Solid-State Circuits, vo l . 32, pp. 745-759, M a y 1997.

[71] C . - Y . Lee, T . - S . C h e n , and C . - H . K a o , "Methods for noise isola t ion i n R F C M O S ICs , " IEEE Electron Device Lett, vo l . 24, pp. 478-480, J u l y 2003.

[72] T . B la l ack , Y . Leclercq , and C . P . Y u e , "On-chip R F isolat ion techniques," i n Proc. of Bipolar/BiCMOS Circuits and Technology Meeting, Sept. 2002, pp. 205-211.

http://ocw.mit.edu/OcwWeb/Electrical-Engineering-

88

Appendix A

M O S F E T S m a l l - S i g n a l M o d e l

T h i s a p p e n d i x 1 reviews the small-s ignal mode l of the M O S transistor used i n noise analysis.

F igu re A . l i l lustrates the comprehensive small-s ignal mode l of the M O S device inc lud ing

parasi t ic capacitances and various device noise sources.

G p z-ngpar a gd

-MSN-D

Csb T I

*nff(T) 9g^.Cgs- = Vgs gmVgs -gmbVs r 0 > ind(\^) Cdb--

Figure A . l : De ta i l ed small-s ignal mode l of the M O S device, i nc lud ing device in ternal noise sources, parasi t ic capacitances, and b o d y effect.

In this figure, Rgpar and engpar represent the parasi t ic resistance of the gate and the

noise associated w i t h i t , gg accounts for the effect of the d i s t r ibu ted nature of the channel ,

ind represents channel thermal and flicker noise, and ing represents gate-induced noise.

Paras i t i c capacitances between terminals of the device are also shown. No te that the

substrate is assumed to be connected to the small-s ignal ground.

T o s impl i fy this model , we make some assumptions: we ignore Rgvar and engpar, for

1 The material presented in this appendix are from [69].

Appendix A. MOSFET Small-Signal Model 89

they can be m i n i m i z e d by proper layout techniques; gg is also neglected because its value

is significant only at very h igh frequencies, i.e., frequencies close to the cut-off frequency

of the device, and finally, we ignore b o d y effect and parasi t ic capacitances (except Cgs);

therefore, the s implif ied version of the mode l is as i l lus t ra ted i n F igure A.2 .

F igu re A.2 : Simpl i f ied M O S F E T smal l -s ignal mode l (parasit ic capacitances, gate dist r ibu ted resistance, and b o d y effect are ignored).

In this figure, two major device noise sources are inc luded (i.e., ind and ing), the power

spec t rum of wh ich are given by:

i\d = 4kT19d0Af + § Af fn

j2 = WT6ggAf

( A . l )

(A.2)

where gdo is the drain-source conductance at zero VDS, 7 a n d S are channel noise and gate

noise coefficients , respectively, Kf is an empi r i ca l coefficient and parameter gg is:

9g = 50 dO

(A.3)

N o w , we app ly superposi t ion to this mode l to find the to ta l ou tput current due to these

noise sources and replace them w i t h a single noise source, indg, as shown i n F igu re A . 3 .


G o— + I

Cgs — — Vgs OmVgs ^ ^ ^ndg ^ ^

D -o

Figure A . 3 : M O S F E T smal l -s ignal mode l w i t h a single noise source representing the effects of bo th channel thermal and gate-induced noise.

T h i s single noise source can be wr i t t en as:

tndg — ^n,ng ~b ^n,nd (A.4)

where i n m and in,nd represent the por t ion of the to ta l noise due to gate-induced and

channel the rmal noises, respectively.

F i r s t , we find the noise output current due to gate-induced noise (in,ng)- Since the

to ta l output noise depends on the impedances connected to the gate and the source, these

components are also inc luded i n F igure A.4 and denoted by Zg and Zrieg. A s can be seen

i n this figure, the output current due to ing can be found using the fol lowing equat ion:

F igure A.4: M O S F E T mode l for the ca lcu la t ion of the effect of gate-induced noise


O

+ Zdeg Vi

Figure A . 5 : Equiva len t c i rcui t to find Zt gs-

i"n,ng — 9m,ZgSi ng (A .5)

where Zgs is the impedance seen between the gate and the source. T o find the value of this

impedance, we use F igure A . 5 , based on which , by w r i t i n g K C L equations at the source

and the gate of the transistor we have:

_. Vtest _ Vl Itest + 1 ,, N i 9mVteat rv

*-l\s^gs) ^deg Vtest + Vl _ . Vtest

~ — %test + 1/sC,

(A.6)

(A.7)

Therefore, Zgs can be found as:

Vtest 1 I, Zdeg + Zg z = hest SCgS "1+0 mZdeg

(A.8)

T o calculate the effect of ind, we use F igu re A.6 , based on which , the fol lowing equations


F igure A . 6 : M O S F E T mode l for the ca lcu la t ion of the effect of channel t he rma l noise.

can be wr i t t en :

l>n,nd — ind ~P QvnYgs

V(sCgs) Vns = -Vl l/{sCgS) + Zg

Vl = in,nd(Zdeg || + Zg))

(A.9)

(A.10)

( A l l )

therefore:

1n,nd ( i - ( 7 % ) ^ ) " ^ = ' Zdeg + Zg

V

Vlnd

N o w , us ing superposi t ion pr inc ip le we find indg i n F igure A . 3 as:

(A.12)

I'ndg — V^nd A~ 9m,Zgs^ng (A.13)

A s discussed i n Chap te r 4, the mean-square valueof the noise (i.e. its power) is the m a i n


parameter used i n the noise figure calculat ions, wh ich can be found as follows:

i2ndg = iWndg = (V*i*nd + 9mZ*gsi*ng){r]ind + gmZgsing)

= M ind^nd + indingdmV*Zgs + inding(gmT]* Zgs)* + inging\gmZ,

= \v\ i2nd + 2Re{indinggmrf Zgs] + i 2

n s | # m Z ,

- \V\2i2

nd + 2Re{ y* nd^ ngQmV ^gsj ' 1 nglym^i d^ng

(AAA)

Reca l l i ng that c was defined as the corre la t ion factor between channel t he rma l noise and

gate-induced noise, we can rearrange this equat ion i n the fol lowing form:

i2nd9 = i2nd\H2 + 2Re{c '2 "2

L M „ n*7 \ -L.%-H£.n2 \7 \ 2 \ ^—9mV AgsJ + ^^9m\Zjgs\ j 1 nd 1 nd

(A.15)

wh ich is the equat ion used i n Chap te r 4 to derive the noise figure of the amplifier; therefore,

the final M O S F E T small-s ignal mode l is as shown i n F igure A . 3 w i t h i2

ndg given by

E q u a t i o n A . 1 5 .

94

I n d e x

Act ive noise suppression, 17 A D C , see Analog-to-digital converter Analog-to-digital converter, 1, 14, 15

Bandgap reference, 14 B E M , see Boundary element method B i C M O S , 1 Bipolar , 1 B J T , 11 Bluetooth, 3, 6 B o d y effect, 7, 11-13, 15, 49, 52, 54, 88,

89 Bondwire, 9, 21, 23, 29, 32 Boundary element method, 16

Cascode, 58 Channel thermal Noise, see Noise Comparator, 15 Complementary current balanced logic, 17 Correlat ion factor

between channel thermal and gate-indi noises, 51, 93

Current balanced logic, 17 Current mirror, 77 Current steering logic, 17

Decoupling, 76 Device noise coefficient, 51, 54, 56 Device noise factor, 57-59 Diode, 11 D N C , see Device noise coefficient D N F , see Device noise factor

F D M , see F ini te difference method Fini te difference method, 16 Fl ip-chip package, 33 Flip-flop, 13 Folded source-coupled logic, 17

Gate noise coefficient, 89 Gate-induce noise, see Noise

Geometric mean distance, 44 G P S , 3, 6, 12, 14, 55 Green's function, 16 Ground bounce, 20 Guard-ring, 17, 66-75

frequency response, 69-71 modelling, 68, 75 placement, 71-73 shape, 73-74 width, 71

I E E E 8 0 2 . i l , 3 Impact ionization, 20 Intermodulation, 7, 14

Latch-up, 39, 40 Leakage current, 9, 20 L N A , see Low noise amplifier Low noise amplifier, 14, 47

inductively-degenerated, 55 Low-noise amplifier, 56, 57, 59, 60, 62 Low-noise digital design, 17

Matching impedance, 55 noise, 62 power, 60

Mi l l e r Effect, 58 Mismatch , 76 M O S

modelling, 21-23 small-signal model, 49-54, 88-93 threshold voltage, 21, 23, 49

Mult i -s tandard, 1

Noise attenuation factor, 34, 35, 42, 43 channel thermal, 88-93

power spectrum, 89 channel thermal, 51 common-mode, 11, 76

http://IEEE802.il

Index 95

external, 19, 31-33 flicker, 88 gate-induced, 51-93

power spectrum, 89 internal, 19, 31-33 mean-square value, 51, 92 simultaneous switching, 28, 30 switching, 7, 20, 21, 23, 26, 27 white, 6

Noise factor device, 57, 59 substrate, 57-62

Noise figure, 47, 55-62

Operational amplifier, 14 Output driver, 22, 27, 38

low-noise, 18

Phase locked loop, 11, 14, 15 Photon-induced current, 20 P L L , see Phase locked loop P M O S , 46, 47 Power matching, 60

Qual i ty factor, 56-62

Sampling, 14 S A S , see Switching activity spreading SeismIC, 16, 20, 68 Signal-to-noise ratio, 14, 15 S N C , see Substrate noise coefficient S N F , see Substrate noise factor S N R , see Signal-to-noise ratio SoC, see System-on-a-chip SOI, 10 • Spiral inductor, 11, 40 Staggering, 65 Substrate

epitaxial, 16, 39-46, 74, 75 lightly-doped, 16, 39-46, 66, 68, 75

resistance, 44 modeling, 41

Substrate noise coefficient, 54, 56 Substrate noise factor, 57, 59 Subthreshold current, 29 Switching activity spreading, 18, 64-66

Symmetry common-centroid, 76 mirror, 76

System-on-a-chip, 1, 2, 13, 14, 55

Transconductance, 15, 47, 49, 58

Var actor, 11, 15 V C O , see Voltage-controlled oscillator Velocity saturation, 21, 29 Voltage-controlled oscillator, 11, 14

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