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Abstract- The project that our group chose was the high

speed data converters project where we will design a first-

order switched-capacitor sample/hold and amplifier with a

closed-loop gain of 2. Sample and hold circuits are analog

devices that grab the voltage of a varying signal and then

hold it for a specific time at a constant level. These are the

elementary analog memory devices. The sample and hold

that we will be designing will be used specifically for pipeline

analog to digital converters.

I. SPECIFICATIONS AND BACKGROUND

typical sample and hold uses capacitors to store the

charge of the input signal. Most sample and holds use at

least one operational amplifier which charges or

discharges the capacitor so that the voltage across the

capacitor is equal to the input voltage. A switch connects the

capacitor with the output buffer. Here is diagram of a very

simple sample and hold as well as a graph showing how a

signal is sampled. C is a control signal controlling when the

switch is open and closed.

Figure 1. Sample and hold Diagram and Plot

For our sample and hold, we will be using an

operational amplifier that needs to have gain above 50 dB and

a GBW greater than 250 MHz. The phase margin should be

greater than 45 degrees and it should have a slew-rate above

250 V/us. Our supply voltages will be +/- 1.5 volts.

II. SEARCH OF EXISTING SOLUTIONS

There are a multitude of sample and hold circuits

and applications and many that pertain to pipeline analog to

digital converters. We went online to IEEExlore and found a

couple of papers on pipelined ADCs. This helped us gain a

better understanding of the functionality of our project and

also realize the applications of this field. It also gave us some

ideas that we could use for our own projects. The papers that

we went over are listed in the reference section at the end of

the report. We also used the Razavi textbook in our search.

Chapter 12 on switched capacitor circuits was very useful and

we were able to learn many new concepts as well as gain

valuable insight for our project. Much of the circuits in our

project stemmed from the textbook.

III. JUSTIFICATION AND DEFINITION OF ARCHITECTURE

We decided to implement our sample and hold circuit

using the differential realization of the unity-gain sampler in

Razavi’s book. The circuit is described in detail in Ch.12.3 on

switched-capacitor amplifiers. Here is the schematic of the

circuit we implemented.

Figure 2. Differential Unity-gain Sampler

For the switches in this circuit, we used simple

MOSFETs. These switches are also described in Razavi’s

book in the previous section. There are two types of switches

that we tried to implement. The first is the charge injection

cancelling switch which uses a dummy transistor to reduce

charge injection and clock feedthrough. This switch is shown

below:

A Sample and Hold Circuit for Pipeline ADCs

ECEN 474 Final Project

Samuel Lee, Alexander Edward, and Peter Zhou

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Figure 3. Dummy Transistor Switch to Reduce

Charge Injection

The second switch we used was the complementary

switch containing a PMOS and NMOS transistor which also

reduces charge injection. We will run tests using these two

switches and see which one gives us the best performance.

Figure 4. Complementary Switch to Reduce Charge

Injection

For the operational amplifier, we modeled our op-

amp after the one that is described in Abo and Gray’s paper

“A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital

Converter”. This

paper on CMOS ADCs has a very good op-amp design that

should work well for our project. It is a fully differential op-

amp that is used in many pipeline ADC applications.

Figure 5. Bias Generator and Low-Voltage Op-amp

The final piece of our sample and hold was trying

achieving the gain of two that is required in the specifications.

The solution to this was found in Razavi’s book in the section

on precision multiply-by-two circuits. By changing our

differential sampler to use this gain of two configurations, we

were able to achieve the gain that was required.

Figure 6. Multiply-by-two Circuit

IV. DESIGN AND SIMULATION WITH RESULTS

1) Op-Amp

The first thing that needed to be designed for our

project was the op-amp. A cascode compensated two-stage

design using folded-cascode input and common-source output

stage is shown in following figure. At first glance, the op-amp

should be able to provide 3-stage worth of gain, rail-to-rail

output swing, and high-speed operation important to meet the

specification in this project. The fully-differential topology

cancels switch’s charge injection to first order and removes

the current-mirror pole present in a single-ended op-amp.

Figure 7. Fully Differential Two-Stage Op-amp

For the op-amp to achieve high-speed operation

(relative to the technology used), the transistor’s parasitic

capacitances should be considered. If not careful, these

capacitances can degrade the phase margin of the op-amp and

cause instability. The differential-mode equivalent circuit for

the circuit in Fig. 7 is shown in Fig. 8.

We ignored the effects of Cgd1 and Cgd6 in this

analysis. The parasitic capacitances C1, C2, and C3 are given

by

C1 = Cgs6 + Cgd3 + Cbd3 + Cgd5 + Cbd5

C2 = Cgs5 + Cbs5 + Cgd4 + Cbd4

C3 = Cbd1 + Cgd2 + Cbd2 + Cgs3 + Cbs3

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The transfer function of the circuit is of the form:

By inspection, the DC gain is approximately about

three-stage worth of gain. Note that M2’s output resistance

loads the drain of M1, degrading the gain compared to the

telescopic cascode topology. The gain-bandwidth is simply

gm1/Cc.

Figure 8. AC Differential-Mode Equivalent Circuit

The LHP zero is of gm5/Cc. The coefficients affecting

the non-dominant poles are approximately given by:

From these equations, we can deduce the advantage

of cascode compensation. The RHP zero in conventional

Miller compensation is replaced by LHP zero. In addition, the

first non-dominant pole is approximately pushed to a high

frequency of gm6/ (C1 + C1CL/Cc) which is a huge

improvement compared to gm6/CL in Miller compensation.

The drawback in cascode compensation is potential peaking if

ωp2 and ωp3 is placed too close to each other. Therefore,

careful design is necessary.

Now we will show the hand calculations that we did for our

op-amp and the results from simulation in Cadence. Here the

aspect ratios and the bias currents for the transistors’ in the

signal path are determined using the equations we have

developed. The extra design equations are the following:

This is the fully-differential slew-rate assuming that the output

stage current consumption is large and

is the input-referred noise spectral density assuming that the

gain per stage is high for the differential mode equivalent

circuit. Multiply this number by two if the output is taken

differentially.

The sizing of the transistors was done using the gm/ID

technique. We characterized the transistor in the diode

connected configuration and obtained the current density,

VD,SAT , gm/ID, gmro,

fT = (gm/2π)(Cgs + Cgd + Cgb), and relative sizes of parasitic

capacitances to Cgs versus the gate bias.

The transistor’s aspect ratio is 9.9/0.6 μm/μm. Their

threshold voltage is about 623 and 870 mV respectively for

the NMOS and PMOS.

We can see that the PMOS transistor is the main

bottleneck in this design. Its gain per stage is only around 15.

This will be worse due to loading from other transistor’s ro. Its

transition frequency is around 1 to 5 GHz dependent on the

bias and limited by the VD,SAT .

It is also worth mentioning that Cbd is about 1.25Cgs.

Since the main parasitic capacitances in the op-amp are Cbd +

Cgd, we need to take into account of this fact. Here are the

gm/ID plots that we used for the 0.6um process:

The design process was iterative. Our comment with

the gm/ID method is that it is only somewhat accurate. Since

the design is fully-differential, the CMFB network alters the

transistor’s bias points we intended to have. This is due to

large systematic offset (current source mismatch and low ro) in

small channel length transistor. Nevertheless, the technique

greatly helps reducing the number of iterations to get optimum

design although some tweaking is still required.

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In the following, we illustrate the analysis of the final

design of the op-amp. The transistor’s operating points

obtained by Spectre’s DC analysis is tabulated in Table. 1.

For load capacitance of 1.5 pF (arbitrary choice, depends on

the next stage and hold capacitor) and compensation

capacitance of 1.5 pF, we have

which definitely exceeds specification. The reason we

overdesigned the op-amp is because of the finite overlapping

period for the non-overlapping clock generator. After

simulation, the width of the clock is about 4 ns which

considerably increases the requirement of the op-amp’s gain-

bandwidth. The slew rate is given by

From table 1, we have the parasitic capacitances:

C1=418.6 fF, C2=391.2 fF, and C3 = 527.7 fF. Next, let us

calculate the denominator in Eq. 4. The parasitic poles are

located at: ωp2 = 2π*326.1 MHz, ωp2ωp3 = 4π2*x2567.32

MHz2, and ωp2ωp3ωp4 = 8π

3714.33 MHz

3. The LHP zero

ωz1 is located at 519.6 MHz. The phase margin is given by

After substituting the number, we obtained phase margin of

60.11o which is satisfactory. Here is the schematic design of

our op-amp in Cadence as well as our simulation results:

Figure 9. Op-Amp Schematic

Figure 10. Gain of op-amp

Figure 11. Noise of Op-Amp

As you can see, the simulated results match very well

with our hand calculations and meet all the specifications that

we designed for.

2) Clock Generator

Usually, switched capacitor circuits require a non-

overlapping clock waveform to avoid charge sharing or short

circuits. The separation of two neighboring edges must be

large enough to ensure that the circuit functions properly. We

designed an edge separation of approximately 1ns.

However, complex switched capacitor circuits will often

demand slightly earlier or later clocks to ensure charge

conservation at some high impedance node. We extracted four

nodes from the generator as shown below in the schematic.

Figure 12. Clock Generation Signal

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Two complementary clock signals are generated by a

single input clock and applied to a SR latch. Delay cells are

inserted between two output nodes to extract delayed clock

versions. The NAND gate outputs are the delayed versions of

the signal while the other two are the complementary clock

signals. The inverter chains after the outputs are made to

provide enough driving capability as the single clock provides

signals to different parts of circuit components. We must be

careful when designing the inverter chains for our outputs to

ensure that there is no accidental overlap of two signals that

are supposed to be non-overlapping.

Figure 13. Clock Generation Schematic

3) Switches

We tried two different types of transistor switches to

implement in our design. These two are both shown in the

background section of the paper. After some tests, we found

that the complementary switch performed much better than the

dummy transistor switch and decided to use that one for our

simulations. Here is a schematic of our switch:

Figure 14. Complementary MOSFET Switch

We had to use an early clock for this switch to obtain

better results for our circuit. This meant having some switches

turning on before other ones by a slight delay. This is the

reason for having early clocks in our clock generation

schematic. Here is the schematic of our unity-gain sampler

with non-ideal switches as well as the resulting transient plot:

Figure 15. Non-Ideal Switch Sampler

Figure 16. Non-Ideal Switch Transient Plot

As you can see, there are many errors in the signal as

and the sampling is not exactly at the input data. This is due

to the fact that our 0.6um process cannot run at fast enough

speeds. Our frequency is 100MHz which is very fast for this

process. Also there is still some charge injection that occurs.

Even though we used the complementary switch to reduce

charge injection, it cannot completely eliminate the errors.

Parasitic capacitances of the transistor will also obviously

degrade our operation and limit our design specifications.

4) Final Circuit

Once we had all the different components of our project

built, we had to put them all together to create our sample and

hold circuit. We first built a unity gain differential sampler to

test our designs and made sure that everything was working

correctly. Here is the schematic and the results we obtained

from simulation. Our input was at 1V and we had capacitance

values of 1.5pF. These simulations are all done with ideal

switches to minimize our errors.

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Figure 17. Unity Gain Sampler Schematic

Figure 18. Transient Plots of Input and Sample

Once we had the unity gain sampler working

correctly, we then implemented a differential gain of two

circuit. This circuit was based off the multiplier from

Razavi’s textbook. Here is a schematic our design and a

transient plot of our simulation:

Figure 19. Gain of 2 Circuit

Figure 20. Gain of 2 Transient Plots

As you can see from the plot, there are slight errors in

our data. The slew rate limitations of our op-amp cause the

rising and falling time issues and there are also glitches due to

the non-idealities in our design. However the circuit performs

the necessary tasks that we want and is able to sample our

signal at twice the magnitude very accurately.

V. CONCLUSION

We were able to successfully design our project to

meet the specifications and achieve our sample and hold.

There were errors due to the op-amp limitations as well as

many problems with the non-ideal switches. The circuit

worked very well with ideal switches and we were able to get

very good results from these tests. With the two different

types of non-ideal switches we used, many more problems

were introduced and we did our best to get the optimal results

for our design. The op-amp that we built worked very well

and far exceeded the required specifications. We were able to

put the final circuit together and have it operate according to

our calculations and design.

This project was a great experience for us as a group

to learn more about sample and hold circuit as well as data

converters in general. It helped us solidify all the material that

we learned in class and lab this semester. It also let us have a

real world application to work with in which we needed to

design a specific circuit to meet specifications.

REFERNECES

Design of Analog CMOS Integrated Circuits, B.

Razavi, McGraw-Hill, 2001.

A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-

to-Digital Converter. Andrew M. Abo and Paul R. Gray

A 14-b 12-MS/s CMOS Pipeline ADC

With Over 100-dB SFDR. Yun Chiu, Paul R. Gray, and

Borivoje Nikolic

Pipelined 13-bit, 250-ks/s, 5-V Analog- to- Digit a1

Converter. Sutarja and Gray

A 12-bit l-Msample/s CapacitorError -Aver aging

Pip elined A/D Converter. Song, Tompsett, and

Lakshmikumar