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Hindawi Publishing CorporationInternational Journal of Power Management ElectronicsVolume 2008, Article ID 862510, 9 pagesdoi:10.1155/2008/862510

Research ArticleA Novel Soft-Switching Synchronous Buck Converter forPortable Applications

Anup Kumar Panda,1 Swapnajit Pattnaik,1 and K. K. Mohapatra2

1 Department of Electrical Engineering, National Institute of Technology, Rourkela 769008, India2 Department of Electronics and Communication Engineering, National Institute of Technology, Rourkela 769008, India

Correspondence should be addressed to Anup Kumar Panda, [email protected]

Received 8 June 2007; Revised 26 October 2007; Accepted 10 December 2007

Recommended by Burak Ozpineci

This paper proposes a zero-voltage-transition (ZVT) pulse-width-modulated (PWM) synchronous buck converter, which is de-signed to operate at low voltage and high efficiency typically required for portable systems. A new passive auxiliary circuit thatallows the main switch to operate with zero-voltage switching has been incorporated in the conventional PWM synchronous buckconverter. The operation principles and a detailed steady-state analysis of the ZVT-PWM synchronous converter implementedwith the auxiliary circuit are presented. Besides, the main switch and all of the semiconductor devices operate under soft-switchingconditions. Thus, the auxiliary circuit provides a larger overall efficiency. The feasibility of the auxiliary circuit is confirmed by sim-ulation and experimental results.

Copyright © 2008 Anup Kumar Panda et al. This is an open access article distributed under the Creative Commons AttributionLicense, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properlycited.

1. INTRODUCTION

Current trends in consumer electronics demand progres-sively lower-voltage supplies. Portable electronics equip-ment, such as laptop computers, cellular phones, and futuremicroprocessor and memory chips, requires low-power cir-cuitry to maximize battery run time. Because of significantlylower conduction losses, synchronous rectifiers are now usedin essentially all low-voltage DC power supplies [1–4]. Asynchronous rectifier is an electronic switch that improvespower-conversion efficiency by placing a low-resistance con-duction path across the diode rectifier in a switch-mode reg-ulator. MOSFETs usually serve this purpose.

However, higher input voltages and lower output volt-ages have brought about very low duty cycles, increasingswitching losses and decreasing conversion efficiency. So inthis paper, we have optimized the efficiency of the syn-chronous buck converter by eliminating switching lossesusing soft-switching technique. The voltage-mode soft-switching method that has attracted most interest in recentyears is the zero-voltage transition [5–24]. This is becauseof its low additional conduction losses and because its op-eration is closest to the PWM converters. The auxiliary cir-

cuit of the ZVT converters is activated just before the mainswitch is turned on and ceases after it is accomplished. Theauxiliary circuit components in this circuit have lower rat-ings than those in the main power circuit because the auxil-iary circuit is active for only a fraction of the switching cy-cle; this allows a device that can turn on with fewer switchinglosses than the main switch to be used as the auxiliary switch.The improvement in efficiency caused by the auxiliary circuitis mainly due to the difference in switching losses betweenthe auxiliary switch and the main power switch if it wereto operate without the help of the auxiliary circuit. Previ-ously proposed ZVT-PWM converters have at least one of thefollowing key drawbacks. (i) The auxiliary switch is turnedoff while it is conducting current. This causes the switchinglosses and EMI to appear, which offsets the benefits of usingthe auxiliary circuit. In converters such as the ones proposedin [6, 12, 15, 16], the turnoff is very hard. (ii) The auxiliarycircuit causes the main converter switch to operate with ahigher peak current stress and with more circulating current.This results in the need for a higher current-rated device forthe main switch and an increase in conduction losses. Theconverters proposed in [5, 8, 9, 13, 14, 17] are having highcurrent stresses on the main switch. (iii) The auxiliary circuit

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2 International Journal of Power Management Electronics

S

S1

Co

CbDS1

Vi+−

Cr

DS2

DS3

Lr Lo

Ro

Vo

Figure 1: The proposed synchronous buck converter.

components have high voltage and/or current stresses, suchas converters proposed in [5, 8, 9, 14, 17]. The converter pro-posed in [23] reduces the current stress on the main switch,but the circuit is very complex. (iv) In addition, most ac-tive circuits are seriously criticized due to their complexity,high cost, difficult control, large circulating energy, excessivevoltage and current stresses, and also narrow line and loadranges. Additionally, it has been reported that the passive cir-cuits are cheaper and more reliable and have a higher perfor-mance/cost ratio than the active ones [25, 26].

Reducing switching losses for low-power circuit such assynchronous buck is not known to be present in the liter-atures [1–26]. The converter shown in Figure 1 is designedfor a low-voltage, high-current circuit, and it is found to behighly efficient. Hence, this paper presents a new class ofZVT synchronous buck converters. By using a resonant aux-iliary network, the proposed converters achieve zero-voltageswitching for the main switch and synchronous switch, andzero-current switching for the auxiliary switch without in-creasing their voltage and current stresses.

The paper is organized as follows. Section 2 gives a shortdescription of the proposed circuit followed by a review ofthe various modes of operation with their key waveforms andthe representation of their equivalent operation modes andanalysis. Section 3 presents the design considerations andSection 4 includes basic features of the converter. Section 5includes simulation and experimental results to illustratethe features of the proposed converter scheme. Section 6 in-cludes some conclusions.

2. THE ZVT-PWM SYNCHRONOUS BUCK CONVERTER

2.1. Circuit description and assumption

The ZVT-PWM synchronous buck converter is shown inFigure 1. It is the combination of the conventional PWM syn-chronous buck converter and the proposed auxiliary snubbercircuit. The auxiliary circuit consists of a resonant inductorLr, resonant capacitor Cr, a buffer capacitor Cb, and threeauxiliary Schottky diodes DS1, DS2, and DS3. Body diodes ofmain switch S and synchronous switch S1 are also utilized inthis converter.

To analyze the steady-state operations of the proposedcircuit, the following assumptions are made during oneswitching cycle.

(1) Input voltage Vi is constant.

(2) Output voltage Vo is constant or output capacitor Co

is large enough.

(3) Output current Io is constant or output inductor Lo islarge enough.

(4) Output inductor Lo is much larger than resonant cir-cuit inductor Lr.

(5) Resonant circuits are ideal.

(6) Semiconductor devices are ideal.

(7) Reverse recovery time of all diodes is ignored.

2.2. Operation principles and analysis

Based on these assumptions, circuit operations in oneswitching cycle can be divided into eight stages. The keywaveforms of these stages are given in Figure 2 and the equiv-alent circuit schemes of the operation stages are given inFigure 3. The detailed analysis of every stage is presented asfollows.

Mode 1 t0-t1. Prior to t1, the body diode of switch S1 wasconducting, while the main switch S was off. The equationsiS = 0, iD1 = Io, iLr = 0, vCr = 0, vCb = 0 are valid at thebeginning of this stage. At t = t0, the main switch is turnedon, which realizes zero-current turn-on as it is in series withthe resonant inductor Lr. During this stage, iLr rises and cur-rent iD1 through body diode of switch S1 falls simultaneouslyat the same rate linearly. The mode ends at t = t1 when iLr

reaches Io and iD1 becomes zero. The body diode D1 is turnedoff with ZVS because ofCr andCb being existent. In this state,

iS = iLr = Vi

Lr

(t − t0

),

iD1 = Io − iLr = −Vi

Lr

(t − t0

)+ Io,

t01 = Lr

ViIo.

(1)

Mode 2 t1-t2. The diode DS2 starts conducting at the in-stant when body diode D1 is turned off. At t = t1, IS = iLr =Io, iD1 = 0, vCr = 0, and vCb = 0. In this interval, resonanceoccurs with the inductor Lr and capacitors Cr and Cb. Thismode ends with Cr charged up to the input voltage Vi;

iLr(t − t1

) = Vi

Z1sinω1

(t − t1

)+ Io,

vCr(t − t1

) = Ce

Cr

[−Vi cosω1(t − t1

)+ Vi

],

vCb(t − t1

) = Ce

Cb

[−Vi cosω1(t − t1

)+ Vi

],

(2)

Anup Kumar Panda et al. 3

VGS

iS

iS1

iLr

vCr

vCb

vS

vS1

iDS2

iDS1

iDS3

t0 t1 t2 t3 t4 t5 t6 t7 t8

Io

Vi

Vi

Vi

VCbm

ILr maxIo

Io

Io

Figure 2: Key theoretical waveforms of the proposed converter.

where

Ce = CrCb

Cr + Cb,

ω1 = 1√LrCe

,

Z1 =√

Lr

Ce.

(3)

The diode DS1 is turned on with ZVS at the moment whenvCr becomes Vi. In this state,

t12 = 1ω1

sin−1(Cr

Ce− 1)

. (4)

Mode 3 t2-t3. At t = t2, iS = Io, iLr = iLr max , vCr =VCr max = Vi, and vCb = VCb1. When diode DS1 turns on,new resonance starts with Lr and Cb. This mode ends wheniLr becomes equal to load current Io, and Cb is charged upto its maximum voltage VCbm. Both diodes DS1 and DS2 areturned off under ZCS due to the existence of Lr. The volt-age and current expressions that govern this circuit mode aregiven by

iLr(t − t2

) = (ILr max − Io)

cosω2(t − t2

)

− VCb1

Z2sinω2

(t − t2

)+ Io,

vCb(t − t2

) = (ILr max − Io)Z2 sinω2

(t − t2

)

+ VCb1 cosω2(t − t2

).

(5)


S

S1 Co

CbDS1

Vi +−

Cr

DS2

DS3

Lr Lo

Ro

Mode 1 (t0-t1)

(a)

S

S1 Co

CbDS1

Vi +−

Cr

DS2

DS3

Lr Lo

Ro

Mode 2 (t1-t2)

(b)

S

S1 Co

CbDS1

Vi +−

Cr

DS2

DS3

Lr Lo

Ro

Mode 3 (t2-t3)

(c)

S

S1 Co

CbDS1

Vi +−

Cr

DS2

DS3

Lr Lo

Ro

Mode 4 (t3–t4)

(d)

S

S1 Co

CbDS1

Vi +−

Cr

DS2

DS3

Lr Lo

Ro

Mode 5 (t4-t5)

(e)

S

S1 Co

CbDS1

Vi +−

Cr

DS2

DS3

Lr Lo

Ro

Mode 6 (t5-t6)

(f)

S

S1 Co

CbDS1

Vi +−

Cr

DS2

DS3

Lr Lo

Ro

Mode 7 (t6-t7)

(g)

S

S1 Co

CbDS1

Vi +−

Cr

DS2

DS3

Lr Lo

Ro

Mode 8 (t7-t8)

(h)

Figure 3: Modes of operation.

The time interval of this stage can be found as follows:

t23 = 1ω2

tan−1(ILr max − Io

VCb1

), (6)

where

ω2 = 1√LrCb

,

Z2 =√

Lr

Cb.

(7)

Mode 4 t3-t4. Since both diodes DS1 and DS2 have beenturned off at t3, now only the main switch S and inductorLr carry the load current. There is no resonance in this modeand the circuit operation is identical to that of a conventionalPWM buck converter. The voltage and current equations forthis mode are

iS = iLr = Io. (8)

Mode 5 t4-t5. This mode starts with the initial conditionsiS = Io, iLr = Io, vCr = VCr max = Vi, VCb = VCbm. The main


switch is turned off under ZVS, and at the same instant, thesynchronous switch is turned on under ZCS. Since the syn-chronous switch S1 is conducting the voltage across capaci-tor, Cb is clamped to zero. Resonance occurs with Lr and Cr.The voltage and current equations for this mode are

vCb(t − t4

) = 0,

iLr(t − t4

) = Io cosω3(t − t4

)− Vi

Z3sinω3

(t − t4

),

(9)

vCr(t − t4

) = IoZ3sinω3(t − t4

)+ Vi cosω3

(t − t4

). (10)

The time duration of this mode can be found as follows:

t45 = 1ω3

tan−1 Vi

IoZ3, (11)

where

ω3 = 1√LrCr

,

Z3 =√

Lr

Cr.

(12)

This mode ends when voltage across Cr becomes zero. There-fore, the diode DS2 turns on under ZVS.

Mode 6 t5-t6. In this stage, new resonance takes placethrough Lr-Cb-DS2-DS1. At t = t5, iS = 0, iLr = ILr2, vCr = 0,and vCb = 0 are initial conditions for this mode. For thisstate, the equations are

vCb(t − t5

) = ILr2Z2sinω2(t − t5

),

iLr(t − t5

) = ILr2 cosω2(t − t5

).

(13)

When iLr becomes Io, this mode comes to an end. The timeinterval for this mode is given as

t56 = 1ω2

tan−1(

Io

ILr2

), (14)

where

ω2 = 1√LrCb

,

Z2 =√

Lr

Cb.

(15)

Mode 7 t6-t7. At t = t6, iS = 0, iLr = Io, vCr = 0,and vCb = VCb2 are initial conditions for this mode. As iLr

becomes Io, synchronous switch is turned off under ZCS.Stored energy of inductor Lr and capacitor Cb is now trans-ferred to load. ON state resistances of diodes and switches areneglected. The voltage and current equations for this modeare given as

vCb(t − t6

) = − Io

Cb

(t − t6

)+ VCb2,

iLr(t − t6

) = −Vo

Lr

(t − t6

)+Io.

(16)

This mode ends when iLr becomes zero. The interval of thismode is given by

t67 = IoLr

Vo. (17)

Mode 8 t7-t8. Now the load current will flow throughbody diode of synchronous switch S1. During this mode, theconverter operates like a conventional PWM buck converteruntil the switch S is turned on in the next switching cycle. Inthis mode,

iD1 = Io. (18)

2.3. Output voltage

The output voltage can be specified by evaluating the energyfrom the supply, through the input resonant inductor Lr [27].The output voltage is given by

Vo= Vi

τ

(12t01 + t12 + t23 + t45 + t56 + t67

)

=Vi

τ

⎛

⎜⎜⎜⎜⎝

12IoLr

Vi+

1ω1

sin−1(Cr

Ce−1)

+1ω2

tan−1(ILr max−Io

VCb1

)

+1ω3

tan−1(VCr max

IoZ3

)+

1ω2

tan−1(

Io

ILr2

)+

12IoLr

Vo

⎞

⎟⎟⎟⎟⎠

.

(19)

Since time intervals of Modes 1 and 7 have low value ascompared to other terms in the above expression, the firstand last terms are neglected for simplification.

Then, the voltage conversion ratio will be

Vo

Vi= 1

τ

⎛

⎜⎜⎜⎜⎝

1ω1

sin−1(Cr

Ce− 1)

+1ω2

tan−1(ILr max − Io

VCb1

)

+1ω3

tan−1(VCr max

IoZ3

)+

1ω2

tan−1(

Io

ILr2

)

⎞

⎟⎟⎟⎟⎠

,

(20)

where τ = 1/ fS, and f S is the switching frequency.From the expression, it can be seen that the voltage con-

version ratio depends upon switching frequency rather thanduty ratio.

3. DESIGN PROCEDURE

Design of conventional PWM converters has been well pre-sented in literatures. Thus, it is more significant to focus ondesign procedures of the auxiliary circuit. The resonant in-ductor and resonant capacitor are the most important com-ponents when designing the auxiliary circuit. The proposedauxiliary resonant circuit provides soft-switching conditionsfor the main transistor. The following design procedure is de-veloped considering procedures such as those presented pre-viously in [5–7].


(1) Snubber inductor Lr is selected to permit its current torise up to at most the maximum output current withintr time periods, during the turn-on of the main tran-sistor or the turnoff of the synchronous switch. In thiscase, from (1),

Vi

Lrtr ≤ Io max (21)

can be written. Here, tr is the rise time of the maintransistor. These equations provide ZCS turn-on forthe main transistor and ZVS turnoff for the body diodeof synchronous switch.

(2) Snubber capacitor Cr is selected to be discharged fromVi to zero with the maximum output current over atleast the time period t f during the turnoff of the maintransistor. For this state, according to (10) and (11),

1Io maxZ3

Vi ≥ t f . (22)

Here, t f is the fall time of the main transistor and

Z3 =√

Lr

Cr. (23)

(3) Buffer capacitor Cb is selected to be charged from zeroup to at most a value decided before, such as half theinput voltage. This capacitor takes on the energies thatare stored in the snubber inductor during the turnoffof the synchronous switch and charge of the snubbercapacitor. This energy balance can be defined as fol-lows:

12CrV

2i +

12CbV

2Cbm =

12LrI2

o max. (24)

The value of Cb is normally larger than the value ofCr. Consequently, the bigger the value of selected Cb

is, the lower the value of VCb max will be. Moreover, ifthe value of Cb increases, the voltage across the syn-chronous switch falls, but the time periods t23, t45, t56,and t67 during which the inductor energies are trans-ferred to Cb or the load rise.

4. CONVERTER FEATURES

The features of the proposed soft-switching converter arebriefly summarized as follows.

(1) All of the active and passive semiconductor devices areturned on and off under exact ZVS and/or ZCS.

(2) The proposed converter has a simple structure, lowcost, and ease of control.

(3) The converter acts as a conventional PWM converterduring most of the switching cycles.

(4) The presented snubber cell can be easily applied to theother basic PWM DC-DC converters and to all switch-ing converters.

(5) The proposed converter has a larger total efficiency anda wider load range.

Table 1: Components used in the proposed converter.

ComponentValue/model

Simulation Experiment

Main switch (S) Ideal IRF1312

Synchronous switch (S1) Ideal IRF1010E

Schottky diode (DS1) Ideal MBR60L45CTG



Resonant inductor (Lr) 15 nH 15 nH

Resonant capacitor (Cr) 1 nF 1 nF

Buffer capacitor (Cb) 3.3 nF 3.3 nF

Output capacitor (Co) 15 μF 15 μF

Output inductor (Lo) 5 μH 5 μH

(6) The main switch and the auxiliary switch are not sub-jected to additional voltage stresses. Current stress onthe main switch is slightly higher, but current stress onthe auxiliary switch is within safe limit.

5. SIMULATION AND EXPERIMENTAL RESULTS

A prototype of the proposed converter, as shown in Figure 1,has been built in the laboratory. The newly proposed con-verter operates with an input voltage Vi = 12 V, output volt-age Vo = 3.3 V, load current of 11 A, and a switching fre-quency of 500 kHz. The converter is simulated using simula-tion software PSIM, version 6.0. The major parameters andcomponents are given in Table 1.

Figures 4(a)–4(d) show the simulation results of the pro-posed converter and Figures 5(a)–5(d) present the experi-mental results. All the waveforms except the efficiency curverepresent a time period of one switching cycle, which is 2microseconds in this case. The amplitudes are denoted inFigure 4 with each of their waveforms, respectively.

5.1. Main switch S

It is noted from Figures 4(a) and 5(a) that the main switchS is turned on under ZCS, and the body diode D1 of syn-chronous switch S1 is turned off under ZVS. The main switchtakes the load current and the charging current of the capac-itors Cr and Cb. The inductor starts to transfer its stored en-ergy to capacitors Cr and Cb during the turn-on period ofmain switch. The converter has not exceeded the voltage lim-its; however, the current stress is slightly higher for a veryshort period of time. The main switch also switches off un-der ZVS. The current and voltage wave shapes are identicalto theoretical waveforms.

5.2. Synchronous switch S1

After the main switch is turned on under ZCS, the bodydiode of synchronous switch is turned off under ZVS, whichcan be observed from Figures 4(b) and 5(b). The syn-chronous switch is turned on under ZCS when the main


−2.5

0

2.5

5

7.5

10

12.5

15

−2.5

0

2.5

5

7.5

10

12.5

15

83.5 83.7 83.9 84.1 84.3 84.5 84.7 84.9 85.1 85.3 85.5

VS

i S

Time (μs)

(a)

−5

0

5

10

15

20

25

−10

−5

0

10

15

20

83.5 83.7 83.9 84.1 84.3 84.5 84.7 84.9 85.1 85.3 85.5

VS1

i S1

Time (μs)

(b)

−2.5

0

2.5

5

7.5

10

12.5

15

−1

0

1

2

3

4

5

6

83.5 83.7 83.9 84.1 84.3 84.5 84.7 84.9 85.1 85.3 85.5

VD

S1VC

r

Time (μs)

(c)

0

5

10

15

20

−1

0

1

2

3

4

5

6

83.5 83.7 83.9 84.1 84.3 84.5 84.7 84.9 85.1 85.3 85.5

VC

bVD

S3

Time (μs)

(d)

Figure 4: Simulated voltage and current waveforms: (a) main switch S: VS, IS; (b) synchronous switch S1: VS1, IS1; (c) diode DS1 and capacitorCr; (d) capacitor Cb and diode DS3.

switch is turned off under ZVS. After the turnoff of themain switch, both capacitors Cr and Cb are discharged.As soon as both capacitors are discharged near zero, thebody diode of synchronous switch S1 is turned on un-der ZVS. The converter has not exceeded the current lim-its; however, the voltage stress across the switch is slightlyhigher for a very short period of time. The synchronousswitch operates within the safe limits, and it can be notedhere that the conduction period of S1 is more confiningto the design values and it operates at a low power whencompared to the other switches. The shapes of the fig-ures are identified to confine much to the theoretical wave-forms.

5.3. Schottky diodes DS1, DS2, and DS3

The Schottky diodes work for a very short period to dis-charge the resonant capacitors Cr and Cb as can be observedfrom Figures 4(c), 4(d), 5(c), and 5(d). Moreover, it canbe seen that the Schottky diodes DS1, DS2, and DS3 oper-ate under soft-switching conditions. The Schottky diodes areturned on and off under ZVS. The conduction of Schottkydiodes may cause a considerable drop in output voltage forlow-power circuits, but due to the advancement in semi-conductor techniques, Schottky diodes are also now avail-able with a low-forward-voltage drop for high-frequency cir-cuits.


(a) (b)

(c) (d)

Figure 5: Experimental voltage and current waveforms: (a) main switch S: VS, IS (V : 5 V/div, I: 10 A/div, time: 0.2 μs/div); (b) synchronousswitch S1: VS1, IS1 (V : 5 V/div, I: 10 A/div, time: 0. 2 μs/div); (c) diode DS1 and capacitor Cr: VDS1, VCr (V : 5 V/div, I: 2 V/div, time: 0. 2 μs/div);(d) capacitor Cb and diode DS3: VCb, VDS3 (V : 5 V/div, I: 2 V/div, time: 0.2 μs/div).

Additionally, during the turn-on and turnoff of mainswitch S and synchronous switch S1, a slight overlap oc-curs between their own voltages and currents. Therefore, theswitching losses are zero, but a little additional conductionloss takes place, and so the conduction losses dominate thetotal loss in the soft-switching converter.

Efficiency curve

From Figure 6, it can be observed that the efficiency values ofthe soft-switching converter are relatively high with respectto those of the hard-switching converter. The efficiency val-ues towards the minimum output power decrease naturallybecause the converter is designed for the maximum outputcurrent. At 70% output power, the overall efficiency of theproposed converter increases to about 96% from the valueof 87% in its counterpart hard-switching converter. The highefficiency concludes the correctness of the design values.

6. CONCLUSION

The concepts of ZVT used in medium and high power wereimplemented in synchronous buck converter, and it wasshown that the switching losses in synchronous buck wereeliminated. Besides, the main switch ZCS is turned on andZVS is turned off. The synchronous switch is also turned

8082

84

8688

9092949698

100

Effi

cien

cy(%

)

15 20 25 30 35

Output power

Soft switching

Hard switching

Figure 6: Efficiency curve.

on under ZCS and turned off under ZVS. Hence, switchinglosses are reduced and the newly proposed ZVT synchronousbuck is highly efficient than the conventional converter. Theadditional voltage and current stresses on the main devicesdo not take place, and the auxiliary devices are subjected toallowable voltage and current values. Moreover, the converterhas a simple structure, low cost, and ease of control. A pro-totype of a 3.3 V, 11 A, 500 kHz system was implemented toexperimentally verify the improved performance.


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