a novel hybrid t-type three-level inverter based on svpwm for...

Research ArticleA Novel Hybrid T-Type Three-Level Inverter Based onSVPWM for PV Application

Ayiguzhali Tuluhong 12 WeiqingWang 1 Yongdong Li2 and Lie Xu2

1Electrical Engineering Xinjiang University Urumqi Xinjiang 830046 China2State Key Laboratory of Power System Department of Electrical Engineering Tsinghua University Beijing 100084 China

Correspondence should be addressed to Weiqing Wang wwq59xjueducn

Received 22 January 2018 Revised 6 April 2018 Accepted 17 April 2018 Published 3 June 2018

Academic Editor Yongheng Yang

Copyright copy 2018 Ayiguzhali Tuluhong et al This is an open access article distributed under the Creative Commons AttributionLicense which permits unrestricted use distribution and reproduction in any medium provided the original work is properlycited

We describe several recently reported new topologies and compare themwith each other in order to find out the optimalmultilevelgrid-connected inverter topology Then we classify these topologies according to the basic unit which predecessors proposedEventually we propose the hybrid T-type inverter topology structure which is composed of two best basic units This structuretakes full advantage of the two components to reduce the harmonic content and the power loss of the converter and improvethe conversion efficiency of the system At the same time the space vector pulse width modulation (SVPWM) method is used tosimulate the proposed topology in the MATLABSIMULINK platform while the loss of each semiconductor switch is calculatedusing MELCOSIM software The results show that the proposed structure is superior to the most widely used topology ie thediode clamped and the T-type three-level circuits

1 Introduction

Nowadays the contradictions between the consumptionpattern of the traditional petrochemical energy and theeconomic development and environmental protection arebecoming more and more prominent People gradually real-ize the importance of taking sustainable development roadvigorous developing and utilizing of the renewable energiesAmong the renewable energies the solar energy representsthe largest and the most commonly distributed resourceThephotovoltaic power generation technology using the solarcells effectively absorbs the solar energy and changes it intoelectricityThe grid-connected inverter is the key componentand important equipment in a photovoltaic grid-connectedsystem

In the design of general inverters synthetically consider-ing the cost-effective factors insulated-gate bipolar transistor(IGBT) represents the most employed device However dueto the nonlinearity of the IGBTrsquos conduction voltage drop itdoes not significantly increase with the increase of currentthus ensuring that the inverter still presents a relatively low

loss and high efficiency at the maximum load conditionHowever since the European efficiency is mainly relatedto the efficiency of the inverter at different light-load theaforementioned characteristics of the IGBT represent thedisadvantage of the photovoltaic grid-connected inverter Forlight loads the turn-on voltage drop of the IGBT does notsignificantly reduce which in turn reduces the Europeanefficiency of the inverter In contrast due to linear conductionvoltage drop of the MOSFET it provides lower turn-on volt-age drop for light loads Considering the excellent dynamiccharacteristics and high frequency work ability MOSFETbecomes the first choice for photovoltaic inverting [1]

Three-level inverter has been widely used in the middleand high voltage large capacity AC speed regulating fieldssince its output has higher power quality lower harmoniccontents better electromagnetic compatibility lower switch-ing losses and other advantages However it still suffersfrom some key problems including the simplification of thethree-level algorithm neutral point voltage control in theovermodulation region and the stability of the system at highvoltage In view of the above problems this paper studies

HindawiJournal of Electrical and Computer EngineeringVolume 2018 Article ID 7245039 12 pageshttpsdoiorg10115520187245039

2 Journal of Electrical and Computer Engineering

S1

V

S2

+

(a) Basic unit A

E

E

S1 S2

S3 S4

S5 S6

(b) Basic unit B

S15

S13S11

S14 S12

V12

V11

Vout

(c) Basic unit C

Figure 1 Basic unit of the inverter

the structure and principle of the three-level inverter thecontrol of the neutral point voltage of the capacitor and therealization of the SVPWM algorithm

In this paper we study novel T-type inverter topology inPV system using SVPWM control algorithm The structureis organized as follows Section 21 introduces basic cellsof the new multilevel PV inverters and classifies themSection 22 presents and compares new types of multilevelinverters Section 23 analyzes and compares switch losses andconversion efficiency of diode clamped T-type and proposedhybrid T-type Section 24 details SVPWMcontrol algorithmSection 3 gives simulation results Finally Section 4 concludesthe paper

2 Materials and Methods

21 Basic Unit Inverter basic unit refers to the minimumcomponent that meets the demands of the topological multi-level grid-connected inverter Odeh [2] proposed one basicconcept of the basic unit of multilevel grid-connected invert-er

As shown in Figure 1(a) after achieving the basic unitit may be extended in form of series-parallel and parallel-series connections to present higher voltage levels Odeh[3] analyzes the connection between the topologies of themultilevel grid-connected inverters and proposes a regu-lar pattern that is followed when general multilevel grid-connected inverter topology simplifies to other multilevelgrid-connected inverter topology For example the mainswitches must be all maintained all switching devices mustbe deleted symmetrically diodes and capacitors must bedistributed symmetrically and so on With the developmentof power electronic devices in order to unify the pressuredrop of the power electronic switch transistors a morepractical basic unit is put forward

Figure 1(b) shows the stacked commutation cells or three-pole cells As the employed conduction strategy one of thetwo transistors in the outer leg is in a frequent switching stateonly during half-cycle while the other transistor is switchedonly once during the fundamental wave period whichgreatly reduces the switching loss This conduction strategyalso avoids the voltage-equalization problem caused by thesimultaneous turn-on and turn-off of the series devicesFigure 1(c) shows the structure of a multilevel inverter basicunit reported byDraxe et al [4]This inverter is formed using

five switches with antiparallel diodes where S11 to S14 arearranged as the traditional CHB inverter while however S15is added to increase the output voltage levels by selecting theappropriate voltage source This structure produces highervoltage levels with minimum number of switches by optimiz-ing the circuit layout and reducing the gate drive circuitry

Recently reported inverter topologies aim to reduce thenumber of the power electronic devices to improve theconversion efficiency Figure 2 shows the classification ofthe inverters based on their topologies As we see from thisfigure the largest portion of the proposed inverter topologiesformed by the basic unit A due to its relatively simpleconstruction The topologies composed of basic units B andC have not yet appeared because of their complex basicconstitution unit

The basic unit of the inverter consists of a DC powersupply and a pair of switches By using the same basic unittaking Figure 1(a) for example in the form of series-parallelcombinations a new circuit topology as shown in Figure 3called single phase H-bridge topology is obtained Or byseries-parallel combinations between different basic unitsalso a new one is got For instance three parallel basic units Aand one basic unit B constitute the three-level T-type invertertopology as shown in Figure 4 Different multilevel inverterscan be obtained by multiseries and multiparallel connectionsof multiple basic units And the construction of the othertopologies in Figure 2 can be deduced by the same analogy

22 New Type Inverter Topology The work in [5] proposedthe split capacitor H-bridge (SC-HB) inverter topologyAdding a simple DC-DC converter this topology overcomesthe capacitance-voltage balance problem while reducing theleakage current with improved efficiency The work in [2]presented the improved cascaded H-bridge topology whichconsists of a half-bridge level latching circuit and a maininverter H-bridgeThus it reduces the number of the devicesswitching loss and harmonic content An asymmetric cas-caded H-bridge topology with different and proportionalDC voltage source values is reported in [4] This reducesthe capacity and number of the devices as well as the costsA sine-wave pulse width modulation (SPWM) three-phasemultilevel inverter topology may be achieved by insertingtwo auxiliary switches in each phase bridge to change thebasic two-level to three-level inverter to synthesize higherlevels [3] In comparisonwith traditional diode clamps flying

Journal of Electrical and Computer Engineering 3

(8) H5 topology

New Topological Structure ofPV Grid - connected Inverter

Basic unit B Basic unit CBasic unit A

Basic units Aand B

Basic units Aand C

(17) T-typetopology

(5) SC-HB topology

(4) Asymmetric CHBtopology

(6) Improved CHB topology

(13) Low leakage current H6 topology

(10) OH5 topology

(12) H6 type topology

(11) FB-DCBP topology

(14) Common - emitter double - buck topology

(15) Hybrid-bridge topology

(9) Heric topology

(7) SPWM three level topology

(16) HB-ZVR topology

Figure 2 Per-phase circuit configuration of the conventional multilevel inverter

S1

V

S2

(a) Basic unit A

Vo1 Vo2

V1

V2

S1

S2

S3

S4

(b) Parallel-connection

V1

V2

V3

S1

S2

S3

S4

Vo1

Vo2

(c) Series-connection

Figure 3 Parallel-series-connection topology of the same basic units


Sa2

Sc3Sc2

Sb3E

Sa3

Sb2

E

E A

B

O

Sa1

Sc2

Sb3Sb2

Sa3Sa2

Sc3

Sb1

Sa4

C

Sc1

Sb4 Sc4

Sa1

Sa4

Cdc1

Cdc2

Figure 4 Parallel-series-connection topology of the different basic units

Cdc

1

2

3

4

V

S1

S2

S3

S4

S5

L1

L2

C1 GridM

(a)

Cdc1

V

N

S1

S2

S3

S4

S5

S6

L1

L2

C1

GridM

(b)

N

Cdc1

Cdc2

V

S1

S2

S3

S4

S5

S6

L1

L2

C1 GridM

(c)

V

N

P

O

Cdc1

Cdc2

L1

L2

C1

GridM

Sa1

Sa2 Sa3

Sa4

Sb1

Sb2Sb3

Sb4

A

B

(d)

Figure 5 Some new topology structure (a) H5 topology (b) Heric topology (c) OH5 topology and (d) T-type topology

capacitors and cascaded H-bridge inverters this topologyuses only a DC power supply and lower power electronicsproviding the same number of the levels

Figure 5(a) shows the H5 topology [6] composed of afreewheeling circuit by adding a high frequency switch inthe positive end of the DC input side where the efficiencymay reach up to 981 However it suffers from big lossand heat and unbalanced thermal stress Figure 5(b) showsthe structure of the Heric topology [7] where a new free-wheeling circuit is added which itself is composed of a setof bidirectional switch branches on the AC side based on thetraditional full-bridge inverter topologyThe efficiency of thistopology may reach more than 98 The OH5 topology isshown in Figure 5(c) [8] which uses a switch and capacitorto form the bidirectional clamping circuit on the basis ofthe H5 topology which greatly inhibits the leakage currentand improves the conversion efficiency However in such astructure the clamping circuit is constrained by the dead timeof the switch and a large on-state loss is presented The work

in [9] proposes the FB-DCBP topology which achieves thecomplete elimination of the leakage current by adding twocontrollable switch and clampdiodes in theDC side to formatthe clamping circuit The leakage current suppression capa-bility of this topology is stronger than that of theH5 andHerictopologies but suffers from large on-state loss and high num-ber of devices providing the maximum efficiency of 974

H6-type topology is proposed in [10] and it is a variantof the Heric topology It does not require setting dead timebetween the switches of the same bridge arm and doesnot pass through the body diode of the switch Thereforeall switches may be formed by MOSFET but the topol-ogy requires extra two freewheeling diodes so the costis increased Moreover the efficiency is lower than theHeric topology and the efficiency is up to 976 The low-leakage current H6 topology is reported in [11] which is acompromise between the H5 and Heric topologies A newfreewheeling circuit is formed based on the H5 topology byadding a switch to make the number of switches through two


half-frequency cycles of the network current at power transfermode not the same yielding reduced on-state loss Theefficiency of the H6 topology is lower than that of the Herictopology and higher than that of H5 topology The commonmode is inferior to H5 topology and superior to Herictopology A common emitter double BUCK topology may beconsidered [12] composed of four controllable switches andtwo diodes The leakage current of this structure is basicallyzero and there is no high frequency dead zone betweenthe switches In addition this structure presents no break-through phenomenon high reliability and small switchingloss where the efficiency may reach more than 985However the topological magnetic component utilization islow and cannot output reactive current

The hybrid bridge topology proposed in [13] consists ofsix controllable switches and two freewheeling diodes Thistopologymoved the switch on the AC side of the Heric topol-ogy to the middle of the bridge arm A similar to H6-typetopology HB-ZVR (H-bridge zero-voltage state rectifier)topology is proposed in [14] introducing an AC bypass cir-cuit which itself is composed of a IGBT and a group of dioderectifiers which is clamped to the midpoint of the two capac-itors on the DC bus to achieve low common mode currentand high efficiency inverter topologyThe HB-ZVR topologysolves the problem that bidirectional switches S5 and S6 of theHeric topology cannot turn on and this topology will alwaysfind a way in the bidirectional switch Figure 5(d) shows theT-type inverter topology [15] formed by a set of switchesSa3Sa4 as a bidirectional switch to achieve the main switchSa1Sa2 clamping function It uses the clamp diodes or clampbit capacitance to improve the midpoint clamping circuitreducing the number of devices and uneven distribution ofthe loss In the topological selection T-type three-level circuitleverages many advantages of the nonisolation technology aswell as the multilevel technologyTherefore it is very suitablefor the photovoltaic grid-connected power generation occa-sions however it is required to effectively suppress the circuitleakage current and system efficiency

By comparing the above different new topologies we seethat the proposed multilevel inverter topology optimizes theperformances of the inverter by adding auxiliaryclampingcircuit using hybrid switch or asymmetric structure

Figure 6 shows the topology of the hybrid T-type inverterwhich is on the basis of T-type structure and composed ofnine MOSFET switches ie Sa2 Sb2 Sc2 Sa4 Sb4 Sc4We choose IGBT for Sa1 Sb1 and Sc1 since the reverserecovery ability of the body diode in the field effect transistoris poor therefore they act in low frequencies The highfrequency MOSFET semiconductor switches ie Sa2 Sb2Sc2 Sa4 Sb4 Sc4 provide good switching characteristicsand low on-resistance Moreover due to the low speedcharacteristics of the built-in diode of MOSFETs MOSFETcannot be used in the upper bridge arm We take advantageof the two devices to reduce the harmonic content andthe power loss of the converter and improve the conversionefficiency of the system

23 Loss Analysis of the Proposed Topology The high powerinverter works in high voltage and large current situations

Cdc1

Cdc2

N

P

VO

Sa1

Sa2

Sa3

Sa4

Sb1

Sb2

Sb3

Sb4

A

B

C

da1da2

da3

da4

Sc1

Sc2

Sc3

Sc4

Figure 6 The proposed hybrid T-type inverter

＞1

＞2

６

３1

３2

３3

３4

３＜1

３＜2

３＜3

３＜4

A BC

３＝1

３＝2

３＝3

３＝4

＄1

＄2

２

２

２

+minus

Figure 7 Diode clamped three-level inverter

where various losses caused by the opening device are rela-tively large Besides optimization of the switching character-istics of the power electronic devices yields bigger conductionlosses of the system especially for soft switching technologywhere the switching loss of the power electronic devicesis reduced and the source of the power loss is convertedto the conduction loss [16] Therefore it is a key step toaccurately calculate the state loss for the design of grid-connected inverter systems Take A phase of Figures 6 and7 as an example we compare the various losses of diodeclamped (Figure 7) and hybrid T-type (Figure 6) inverterlosses and their conversion efficiency We assume that theoutput current of the grid-connected inverter is an idealsine wave the output voltage of the inverter integrates theconduction period in the period T Then the conductionlosses per device may be expressed as

1198751199041198861 = 12120587 [int120587minus1205790 119889 (120596119905)119880com (119894) (119868com sin (120596119905) 119889 (120596119905))] (1)

where1198751199041198861 is the conduction loss of the per device 119889(120596119905) is theduty cycle 119880com(119894) represents the conduction voltage drop ofthe IGBT 119868com denotes the conduction current peak of theIGBT and 120596 is the angle speed The integral interval from 0to 120587-120579 is a chopper phase of the semiconductor switch Sa1 in


a fundamental periodThe conduction loss of the antiparalleldiode in the IGBT reads1198751198891198861 = 12120587 int120587120587minus120579 (minus119898 lowast sin (120596119905 + 120601)) [119880119900119889119868com sin (120596119905)+ 119877119900119889 (119868com sin (120596119905))2] 119889 (120596119905) (2)

where 1198751198891198861 is the conduction loss of the antiparallel diode inthe IGBT 119898 is the modulation index B is the output powerfactor angles and 119877119900119889 and 119880119900119889 are the conduction pressuredrop constants of the antiparallel diode

When IGBTMOSFET is turned off the current flowsfrom the clamped diodes and then reads the followingclamped diode conduction loss

1198751198631198861 = 12120587 int120587minus1205790 (1 minus 119898 lowast sin (120596119905 + 120601))sdot [119880119889119905119868com sin (120596119905)+ 119877119889119905 (119868com sin (120596119905))2] 119889 (120596119905) + 12120587sdot int120587minus1205790(1 + 119898 lowast sin (120596119905 + 120601)) [119880119889119905119868com sin (120596119905)+ 119877119889119905 (119868com sin (120596119905))2] 119889 (120596119905)

(3)

where119880119889119905 and119877119889119905 are the conduction pressure drop constantsof the clamped diode

We considered the DC side voltage of 700V carrierfrequency fc of 5 kHz gate resistance of 165 ohm outputfrequency equal to 60Hz modulation rate of unity andpower factor of 08 We used MELCOSIM software to sim-ulate the loss Table 1 presents the calculated loss of differentcomponents

In Table 1 the power losses of Sa1 and Sa4 as well as Sa2and Sa3 IGBT switches are identical The four antiparalleldiode power dissipations da1 da2 da3 and da4 are alsoidentical Moreover clamping diodes Da1 and Da2 have thesame loss Table 2 lists the overall loss of the two topologieswhichmay be calculated based on the number of componentscontained in two topologies This table also presents the totalpower of the inverter which is 10 kW and the conversionefficiency of each topology

The conversion efficiency is lower than 90because of thehigher switching frequencyWe chose the frequency of 10KhzMOSFET and the switching frequency is relatively high atthe same time the switching loss itself is higher than at powerfrequency so the conversion efficiency is lower than 90

Table 3 shows the comparison between theNP andT-typethree-level inverters

24 SVPWM Control Method The theoretical basis of theSVPWM is the mean equivalent principle that is combiningthe fundamental voltage vectors in a switching cycle to makethe average value equal to the given voltage vector At acertain moment the voltage vector rotates into a certainregion which may be achieved by a different combinationover time of two adjacent nonzero vectors and zero vectorsthat make up this region The action time of the two vectors

(100)(0-1-1)

(11-1)

(1-1-1)

(010) (10-1)(0-10)

(01-1)(-11-1)

(-110)

(-101)

(-1-11) (0-11) (1-11)

(1-10)

(110)(00-1)

(011)(-100)

(001)(-1-10)

(101)(0-10)

(000)(111)(-1-1-1)

Figure 8 Three-level space vector diagram

is repeatedly applied in one sampling period so that itcontrols the action time of each voltage vector This rotatesthe voltage space vector in accordance with the circulartrajectory and approaching ideal flux circle through the actualmagnetic flux generated by different switching states of theinverter Then it determines the inverter switch state by thecomparison at the end form of the PWM waveform

SVPWMpresents lower total harmonic distortion (THD)compared to other control strategies and it may refine thesteady and dynamic state performances of the PV grid-connected system simultaneously Meanwhile output resultsof the inverters with SVPWM control strategy provide betterpower quality than that of the inverters with other controlstrategies The SVPWM control strategy with three-phasethree-level voltage source inverter is effective and feasible[17] The detailed equations of the SVPWM strategies basedon the proposed topology are as follows

In this paper we used decomposition hexagon method

Idea decompose the multilevel space vector into a combi-nation of multiple two-level space vectors to achieve greatlysimplified PWM calculation method

The three-level space vector diagram is shown in Figure 8Any reference vector must fall within a small triangle Thevertex of this triangle is the basic voltage vector that composesthis reference vector

The reference vector falling into the shadow in Figure 8can be decomposed into an offset vector and a two-levelvector as shown in Figure 9

Steps

241 Sector Judgments Based on Clarkrsquos transformationthe normalized output vectors transformed from abc to 120572120573reference frame may be expressed as

(119881120572119881120573119881119900) =(23 minus13 minus130 1radic3 minus 1radic31 1 1 )(119881119860119881119861119881119862) (4)


Table 1 The loss of each device in hybrid T-type inverter

Switch type device Loss (W)Conduction loss Switching loss Total loss

IGBT Sa1 9045 2646 11692Sa2 3178 103 3282

Freewheeling diode da1 4059 047 4107Clamped diode Da1 223 993 1217

Table 2 The power loss and conversion efficiency of two topologies

component The number of DC Loss (W) conversion efficiencyIGBT diode Total loss

NPC 1 99888 31072 13096 08690Hybrid T-type 1 89844 31944 121788 08782

Table 3 Similarities and differences of diode clamped and T-type three-level circuit topologies

Compared items Diode clamped three-level inverter T-type three-level inverterSwitch pressure Sa1simSa4 05UPV Sa1Sa2 Upv Sa3Sa4 05Upv

Commutation path Long commutation path and shortcommutation path All paths are consistent

Efficiency The higher switching frequency (gt16 kHZ)increases efficiency

The lower switching frequency (lt16 kHZ)increases efficiency

Modulation strategy Traditional control strategy of current PI loop Traditional control strategy of current PI loopNumber of components 4 switches plus 2 diodes 4 switchesDrive power 4 groups 3 groups

Table 4 The relations between N and the sector where 119881ref islocated

N 1 2 3 4 5 6sector II VI I IV III V

where119881120572119881120573119881119900 are voltages on the two-phase stationarycoordinate system and 119881119860 119881119861 119881119862 are voltages on the three-phase stationary coordinate system

We define119873 = 119860+2119861+4119862 and the value of119873 determinesin which sector the reference vector 119881ref is located So therelations between119873 and the corresponding sector are shownin Table 4

242 Basic Vector Dwell Time Calculation We assume119881ref islocated at sector I which yields the following equation

119881120572119879119904 = 1198791 100381610038161003816100381611988111003816100381610038161003816 + 1198792 100381610038161003816100381611988121003816100381610038161003816 cos 1205873119881120573119879119904 = 1198792 100381610038161003816100381611988121003816100381610038161003816 sin 1205873119879119904 = 1198791 + 1198792 + 11987907(5)

where 119879119904 is the sampling period 1198791 1198792 and 1198790 represent thedwell times of the basic vectors 1198811 1198812 and 1198810 respectively

(100)(0-1-1)

(1-1-1)

(10-1)

(1-10)

(110)(00-1)

(101)(0-10)

(000)

(111)(-1-1-1)

VＬ

VＩffＭＮ

VＬ

V1

V2

I

II

III

IVV

VI

Figure 9 Decomposed two-level space vector diagram

According to the above expressions we can obtain the follow-ing equation 1198791 = radic31198791198782119881119889119888 (radic3119881120572 minus 119881120573)1198792 = radic311987911990411988112057311988111988911988811987907 = 119879119904 minus 1198791 minus 1198792

(6)


Table 5 The relations between vector dwelling time and its sector

sector I II III IV V VI1198791 Z Y -Z -X X -Y1198792 Y -X X Z -Y -Z

Maximumamplitude

voltagevector

boundary

Maximumundistorted

circularvoltagevector

boundary

I

II

III

IV

V

VI

５1

５2

５3 ５4

５5

５6

５out

Figure 10 Voltage vector amplitude boundary in SVPWMmode

Following the same principle the dwell time of eachvector we achieve 119881ref of different sectors To facilitate thesolution we may define it as (7) The value of 1198791 and 1198792 atdifferent sectors could be set according to Table 5119883 = radic3 119879119878119881119889119888119881120573119884 = 119879119904119881119889119888 (radic32 119881120573 + radic32 119881120572)119885 = 119879119904119881119889119888 (radic32 119881120573 minus radic32 119881120572)

(7)

243 Vector Switching Point Calculation When the syn-thesized voltage vector endpoint falls between the regularhexagon and the circumscribed circle as shown in Figure 10the overmodulation has occurred and the output voltage willbe distorted So we use a proportional scaling algorithmto control the overmodulation The vector dwell time thatfirst occurs in each sector is defined as 119879Nx and the vectordwell time that occurs after is defined as 119879Ny When 119879119909 +119879119910 ⩽ 119879NPWM the vector endpoint is within the regular hex-agon and no overmodulation occurs When 119879Nx + 119879Ny gt119879NPWM the vector endpoint is beyond the regular hexagonand overmodulation occurs The output waveform will beseriously distorted and must take the following measures

Suppose that the nonzero vector dwell time is 1198791015840Nx 1198791015840Nywhen the endpoint of the voltage vector trace is pulled backto the inscribed circle of the regular hexagon and then thereis a proportional relationship1198791015840119873119909119879119873119909 = 1198791015840119873119910119879119873119910 (8)

Therefore 1198791015840119873119909 1198791015840119873119910 1198791198730 1198791198737 can be obtained by thefollowing formula1198791015840119873119909 = 119879119873119909119879119873119909 + 119879119873119910119879119873PWM

1198791015840119873119910 = 119879119873119910119879119873119909 + 119879119873119910119879119873PWM1198790 = 1198797 = 0(9)

According to the above process the action time of twoadjacent voltage space vectors and zero-voltage vectors ineach sector can be obtained The operation relationship isshown in Figure 11 when 119880ref is in sector I After the 119880refsector and the corresponding effective voltage vector aredetermined according to the PWM modulation principlethe value of each corresponding comparator is calculated andthe operation relationship is as follows119905aon = (119879119904 minus 119879119909 minus 119879119910)2119905bon = 119905aon + 119879119909119905con = 119905bon + 119879119910

(10)

Other sectors follow the same above principleHere 119879cm1 119879cm2 119879cm3 denote the transistorrsquos switching

time And the relation between sector switching point and itsappropriate sector is tabulated in Table 6

3 Results and Discussion

This study put forward a novel hybrid T-type invertertopology which is composed of basic units A and B on thebasis of previous research studies We established a three-phase three-level hybrid T-type photovoltaic grid-connectedinverter topology model which is shown in Figure 12 usingMATLAB platform Considering the A-phase bridge leg forexample it consists of one half-bridge IGBT one half-bridgeMOSFET and two neutral point MOSFETs Switches Sa1and Sa2 work in the mutual intermittent state and switchesSa3 and Sa4 only work near the current zero-crossing pointwith high frequency This topology is rather suited for thephotovoltaic nonisolated AC system applications

The topological structure is on the basis of T-type struc-ture changing the nine switches into MOSFET ie Sa2 Sb2Sc2 sdot sdot sdot Sa4 Sb4 and Sc4 We choose IGBT for Sa1 Sb1 andSc1 since the reverse recovery ability of the body diode inthe field effect transistor is poor therefore they act in lowfrequencies The high frequency MOSFET semiconductorswitches ie Sa2 Sb2 Sc2 Sa4 Sb4 Sc4 provide goodswitching characteristics and low on-resistance Moreoverdue to the low speed characteristics of the built-in diode ofMOSFETsMOSFET cannot be used in the upper bridge armWe take advantage of the two devices to reduce the harmoniccontent and the power loss of the converter and improve theconversion efficiency of the system

Regarding the topology selection the three-level circuitcombines the advantages of the nonisolation and multilevel


Table 6 The relationship between the vector switching point and its corresponding sector

sector I II III IV V VI119879119886 119879bon 119879aon 119879aon 119879con 119879con 119879bon119879119887 119879aon 119879con 119879bon 119879bon 119879aon 119879con119879119888 119879con 119879bon 119879con 119879aon 119879bon 119879aon

Ts

T02 T12 T22 T72 T72 T22 T12 T02

0 1 1 1 11 1 0

0 0 1 11 1 0

0 0 0 10 0 0

0

0

Tcon

Taon

Tbon

Tpwm

TNPW

M

TNaon TN

bon TNcon

TNx

TNy

TN0

TNPW

M-TN

aon

TNPW

M-TN

bon

TNPW

M-TN

bon

Figure 11 Operation relationship when 119880ref is in sector I

Figure 12 The simulation model of the SVPWM controlled novel T-type three-phase three-level inverter


Table 7The classification of the influence of the switching state of the short andmedium vectors on the direction of the neutral point current

Positive short vectorswitching status io Negative short vector

switching status io Medium vectorswitching status io

100 ia 211 - ia 210 ib221 ic 110 - ic 120 ia010 ib 121 - ib 021 ic122 ia 011 - ia 012 ib001 ic 112 - ic 102 ia212 ib 101 - ib 201 ic

Current Voltage0

50

100

150

200

250

300

Three kinds of inverters

Current12345678


THD

( o

f fun

dam

enta

l)

0( o

f fun

dam

enta

l)TH

D

NPCT-typeHybrid T-type

Figure 13 The current and voltage THD comparison of three typesof inverters

technologies which is very suitable for the photovoltaic grid-connected power generation

System simulation parameters are as followsTheDC-linkvoltage is 700V with the frequency of 50Hz the value of thesupport capacitor reads 3300 uF with the AC-side inductanceof 3mH the AC-side resistance is 01Ω and the switchingfrequency is 10 kHzThe value of the stray capacitance is 10eminus6 F and the small resistor is connected in parallel with thestray capacitance of 119877 = 10e minus 6 ohm

Table 7 shows the neutral point current when the positiveand negative short vector and medium vector act It can beseen that positive and negative short vector and mediumvectors will cause neutral voltage fluctuations

The neutral point voltage control method is based onthe SVPWM According to the influence of the mediumand short vectors on the neutral point voltage offset andby selecting the appropriate switching state and the mostsuitable switching sequence for the neutral point voltage themidpoint voltage offset during each control cycle has beenminimized

So selecting the excellent transistor sequence is reallyimportant To solve this problem we run through all thetransistors in every possible combination andpermutation onthe condition of the following switch rules

(1) The switching states of the devices in every bridge legare independent (2)The switching states of any two adjacent

switches of each bridge leg are complementary (eg if Sa1 isturned on then Sa2 must be switched off) (3) According tothe principle of complementarity if the switching state of anyof the devices in the same bridge leg is determined the stateof the other switching devices of that bridge leg can also beconfirmed [18]

The influence of harmonic current on the power gridis greater than the harmonic voltage and it is the fun-damental cause of most of the problems and the neutralvoltage fluctuations are proportional to the amount of theharmonic current So as can be seen from Table 8 givingcomprehensive consideration choose the following optimaltransistor sequence Sa1-Sa3-Sa4-Sa2-Sb1-Sb3-Sb4-Sb2-Sc1-Sc3-Sc4-Sc2

The control method is achieved by the SVPWM with12 trigger pulses Switching sequence reads Sa1-Sa3-Sa4-Sa2-Sb1-Sb3-Sb4-Sb2-Sc1-Sc3-Sc4-Sc2

Figure 13 shows the output voltage and current harmoniccontent of the three types of inverter topology structure usingSVPWM control method From Figure 13 we could see thatcurrent and phase voltage THD (total harmonic distortion)of the NPC inverter is the biggest the T-type inverter is themiddle one and the proposed hybrid T-type is the smallestone Meanwhile the amplitude of the three kinds of invertercurrent harmonics is not obvious however the voltage THDresults of the three kinds of inverter are sharply comparable

The topology and control strategy of the two circuits arethe same except the devices used The T-type topology con-sists of 12 IGBTs while the hybrid T-type topology consistsof 9 MOSFETs and 3 IGBTs And the off-delay time and deadtime of the IGBT are longer than those of the MOSFET

Although the proportion of dead time is often very smallrelative to one switching cycle the dead zone will make thethree-phase control system deviate from the ideal mathemat-ical model When the switching frequency becomes higherthe dead-zone effect will gradually accumulate and when itaccumulates to a certain degree it will distort the AC-sidevoltage waveform which will affect the waveform quality ofthe input current It will also cause fluctuations in the DCvoltage which degrades the accuracy of the entire systemIn addition the dead time can cause common mode voltagewaveform distortion resulting in higher harmonics [19] Sothe THD of the novel T-type inverter is the lowest

From Figure 14 we see that the common mode current ofthe proposed novel T-type inverter is smaller than the pre-vious T-type inverter topology In conclusion the proposed


Table 8 Comparison of output parameters under various switching sequence (simulation time 01 s)

Sequence of the transistors Power factor Current harmonics voltage harmonicsSa1- Sa2- Sb1- Sb2- Sc1- Sc2- Sa3- Sa4- Sb3- Sb4- Sc3-Sc4 07209 2727 15899

Sa1- Sa2- Sb1- Sb2- Sc1- Sc2- Sa4- Sa3- Sb4- Sb3- Sc4-Sc3 07263 2173 23675

Sa1- Sc2- Sb1- Sa2- Sc1- Sb2- Sa3- Sa4- Sb3- Sb4- Sc3-Sc4 0647 1161 14913


Sa1- Sa2- Sa3- Sa4- Sb1- Sb2- Sb3- Sb4- Sc1- Sc2- Sc3-Sc4 05799 063 15603




0 20 30 40 50 60 70 8010t (s)

minus40

minus20

0

20

40

60

80

Icm

(A)

Novel T-typeT-type

Figure 14 The obtained CM-current of the novel and previous T-type inverters

hybrid T-type inverter has priority compared to the NPC andT-type inverter

The instantaneous common mode voltage and groundleakage current could be given by the following equation119906cm = 119906AN + 119906BN + 119906CN3119894cm = 119862119889119906cm119889119905 (11)

where 119906AN 119906BN and 119906CN are the pulse voltages between thebranch midpoint and the dc bus minus terminal respectively

It can be seen from the equation that the common modecurrent 119894cm is proportional to the change rate of the commonmode voltage 119906cm

According to the above interpretation it can be got thatthe dead time of the proposed topology is the shortest becauseof the smallest number of IGBTs comparedwith the other twotopologies so that the commonmode voltage and current arealso the smallest

4 Conclusions

We introduced a variety of new multilevel photovoltaicgrid-connected inverter topologies compared them witheach other and classified them according to the basic unitwhich predecessors proposed We proposed the hybrid T-type inverter topology which is composed of two best basicunitsThis structuremakes full advantages of the two deviceswhich leads to reducing the harmonic content and power lossof the converter and improving the conversion efficiency ofthe system By comparing the new topology the new mul-tilevel inverter topology is formed by the basic constituentelements to increase the auxiliaryembedded circuit or witha hybrid switch or with asymmetric structure to optimize theinverter performance We use the space vector pulse widthmodulation (SVPWM) method to build the SIMULINKmodels of the proposed hybrid T-type and NPC three-levelinverter in the MATLAB software and compare them witheach other The simulation results show that the proposedtopology presents lower output harmonics than the NPCtopology We then provided further loss analysis for thesetwo topologies using the MELCOSIM software to calculatethe loss of different components in each topology as wellas the total power loss The outcome is that the loss of theT-type topology is significantly lower than that of the NPCtopology and the conversion efficiency is higher than thatof the NPC topology Moreover the simulation results showthat the commonmode current of the proposed novel T-typeinverter is smaller than the previous T-type inverter topology


The proposed inverter topology has a certain practicality andeconomy to meet the actual needs

Data Availability

The data used to support the findings of this study areavailable from the corresponding author upon request

Conflicts of Interest

All the authors declare that there are no conflicts of interestregarding the publication of this paper

Acknowledgments

The work was supported by the National Natural ScienceFoundation ofChina (Grants no 51667020 andno 61364010)theOutstandingDoctorGraduate Student InnovationProjectof Xinjiang University (no XJUBSCX-2016018) and Grad-uate Student Innovation Project of Xinjiang Uygur Auton-omous Region (no XJGRI2017025)

References

[1] F Michael and E Temesi ldquoHigh Efficient Topologies for NextGeneration Solar Inverterrdquo Inverter World vol 03 pp 31ndash362009

[2] C I Odeh ldquoA cascaded multi-level inverter topology withimproved modulation schemerdquo Electric Power Components andSystems vol 42 no 7 pp 768ndash777 2014

[3] C I Odeh ldquoSinusoidal pulse-width modulated three-phasemulti-level inverter topologyrdquo Electric Power Components andSystems vol 43 no 1 pp 1ndash9 2015

[4] K P Draxe M S B Ranjana and K M Pandav ldquoA cascadedasymmetric multilevel inverter with minimum number ofswitches for solar applicationsrdquo in Proceedings of the 2014 Powerand Energy Systems Conference Towards Sustainable EnergyPESTSE 2014 15 13 pages ind March 2014

[5] M Azri N A Rahim and W A Halim ldquoA highly efficientsingle-phase transformerless H-bridge inverter for reducingleakage ground current in photovoltaic grid-connected systemrdquoElectric Power Components and Systems vol 43 no 8-10 pp928ndash938 2015

[6] H Schmidt C Siedle and J Ketterer ldquoInverter for transforminga DC voltage into an AC current or an AC voltagerdquo Tech RepEP1369985(A2) Germany 2003-12-10

[7] D Jovcic andK Ahmed ldquoMethod of converting a direct currentvoltage form a source of direct current voltage more specificallyfrom a photovoltaic source of direct current voltage into aalternating current voltagerdquo Tech Rep US7411802(B2) UnitedStates 2008

[8] H Xiao S Xie Y Chen and R Huang ldquoAn optimized trans-formerless photovoltaic grid-connected inverterrdquo IEEE Trans-actions on Industrial Electronics vol 58 no 5 pp 1887ndash18952011

[9] R Gonzalez J Lopez P Sanchis and L Marroyo ldquoTrans-formerless inverter for single-phase photovoltaic systemsrdquo IEEETransactions on Power Electronics vol 22 no 2 pp 693ndash6972007

[10] W Yu J-S Lai H Qian and C Hutchens ldquoHigh-efficiencyMOSFET inverter with H6-type configuration for photovoltaic

nonisolated AC-module applicationsrdquo IEEE Transactions onPower Electronics vol 26 no 4 pp 1253ndash1260 2011

[11] L Zhang K Sun and L L Feng ldquoH6 non-isolated full bridgegrid-connected PV inverters with low leakage currentsrdquo in Pro-ceedings of the CSEE 32 vol 3215 pp 1ndash7 2012

[12] S V Araujo P Zacharias and R Mallwitz ldquoHighly efficientsingle-phase transformerless inverters for grid-connected pho-tovoltaic systemsrdquo IEEE Transactions on Industrial Electronicsvol 57 no 9 pp 3118ndash3128 2010

[13] X Zhang L L Sun and P Xu ldquoResearch on the restrainingof common mode current in the single-phase transformerlessgrid-connected PV systemrdquo Acta Energiae Solaris Sinica 309vol 30 no 9 pp 1202ndash1208 2009

[14] T Kerekes R Teodorescu P Rodrıguez G Vazquez and EAldabas ldquoA New high-efficiency single-phase transformerlessPV inverter topologyrdquo IEEE Transactions on Industrial Electron-ics vol 58 no 1 pp 184ndash191 2011

[15] U-M Choi F Blaabjerg and K-B Lee ldquoReliability improve-ment of a T-type three-level inverter with fault-tolerant controlstrategyrdquo IEEE Transactions on Power Electronics vol 30 no 5pp 2660ndash2673 2015

[16] C Yang and Y Liu ldquoThe contrast of conduction dissipationof T-type 3-level inverter and diode-clamped 3-level inverterrdquoAutocontrol 02 vol 02 pp 61ndash66 2015

[17] WKun Y XiaojieWChenchen andZMinglei ldquoAn equivalentdual three-phase SVPWM realization of the modified 24-sector SVPWM strategy for asymmetrical dual stator inductionmachinerdquo in Proceedings of the 2016 IEEE Energy ConversionCongress and Exposition ECCE 2016 Milwaukee WI USASeptember 2016

[18] T Mingting Research on Three-Phase T-Type Three-Level Non-Isolated Grid-Connected Inverter Hefei University of Technol-ogy 2013

[19] J-WChoi and S-K Sul ldquoInverter output voltage synthesis usingnovel dead time compensationrdquo IEEE Transactions on PowerElectronics vol 11 no 2 pp 221ndash227 1996

International Journal of

AerospaceEngineeringHindawiwwwhindawicom Volume 2018

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Hindawiwwwhindawicom Volume 2018


Active and Passive Electronic Components

VLSI Design



Shock and Vibration


Civil EngineeringAdvances in

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Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawiwwwhindawicom

Volume 2018

Hindawi Publishing Corporation httpwwwhindawicom Volume 2013Hindawiwwwhindawicom

The Scientific World Journal

Volume 2018

Control Scienceand Engineering

Journal of



Journal ofEngineeringVolume 2018

SensorsJournal of



RotatingMachinery


Modelling ampSimulationin EngineeringHindawiwwwhindawicom Volume 2018


Chemical EngineeringInternational Journal of Antennas and

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Navigation and Observation


Hindawi

wwwhindawicom Volume 2018

Advances in

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Submit your manuscripts atwwwhindawicom


S1

V

S2

+

(a) Basic unit A

E

E

S1 S2

S3 S4

S5 S6

(b) Basic unit B

S15

S13S11

S14 S12

V12

V11

Vout

(c) Basic unit C

Figure 1 Basic unit of the inverter

the structure and principle of the three-level inverter thecontrol of the neutral point voltage of the capacitor and therealization of the SVPWM algorithm

In this paper we study novel T-type inverter topology inPV system using SVPWM control algorithm The structureis organized as follows Section 21 introduces basic cellsof the new multilevel PV inverters and classifies themSection 22 presents and compares new types of multilevelinverters Section 23 analyzes and compares switch losses andconversion efficiency of diode clamped T-type and proposedhybrid T-type Section 24 details SVPWMcontrol algorithmSection 3 gives simulation results Finally Section 4 concludesthe paper

2 Materials and Methods

21 Basic Unit Inverter basic unit refers to the minimumcomponent that meets the demands of the topological multi-level grid-connected inverter Odeh [2] proposed one basicconcept of the basic unit of multilevel grid-connected invert-er

As shown in Figure 1(a) after achieving the basic unitit may be extended in form of series-parallel and parallel-series connections to present higher voltage levels Odeh[3] analyzes the connection between the topologies of themultilevel grid-connected inverters and proposes a regu-lar pattern that is followed when general multilevel grid-connected inverter topology simplifies to other multilevelgrid-connected inverter topology For example the mainswitches must be all maintained all switching devices mustbe deleted symmetrically diodes and capacitors must bedistributed symmetrically and so on With the developmentof power electronic devices in order to unify the pressuredrop of the power electronic switch transistors a morepractical basic unit is put forward

Figure 1(b) shows the stacked commutation cells or three-pole cells As the employed conduction strategy one of thetwo transistors in the outer leg is in a frequent switching stateonly during half-cycle while the other transistor is switchedonly once during the fundamental wave period whichgreatly reduces the switching loss This conduction strategyalso avoids the voltage-equalization problem caused by thesimultaneous turn-on and turn-off of the series devicesFigure 1(c) shows the structure of a multilevel inverter basicunit reported byDraxe et al [4]This inverter is formed using

five switches with antiparallel diodes where S11 to S14 arearranged as the traditional CHB inverter while however S15is added to increase the output voltage levels by selecting theappropriate voltage source This structure produces highervoltage levels with minimum number of switches by optimiz-ing the circuit layout and reducing the gate drive circuitry

Recently reported inverter topologies aim to reduce thenumber of the power electronic devices to improve theconversion efficiency Figure 2 shows the classification ofthe inverters based on their topologies As we see from thisfigure the largest portion of the proposed inverter topologiesformed by the basic unit A due to its relatively simpleconstruction The topologies composed of basic units B andC have not yet appeared because of their complex basicconstitution unit

The basic unit of the inverter consists of a DC powersupply and a pair of switches By using the same basic unittaking Figure 1(a) for example in the form of series-parallelcombinations a new circuit topology as shown in Figure 3called single phase H-bridge topology is obtained Or byseries-parallel combinations between different basic unitsalso a new one is got For instance three parallel basic units Aand one basic unit B constitute the three-level T-type invertertopology as shown in Figure 4 Different multilevel inverterscan be obtained by multiseries and multiparallel connectionsof multiple basic units And the construction of the othertopologies in Figure 2 can be deduced by the same analogy

22 New Type Inverter Topology The work in [5] proposedthe split capacitor H-bridge (SC-HB) inverter topologyAdding a simple DC-DC converter this topology overcomesthe capacitance-voltage balance problem while reducing theleakage current with improved efficiency The work in [2]presented the improved cascaded H-bridge topology whichconsists of a half-bridge level latching circuit and a maininverter H-bridgeThus it reduces the number of the devicesswitching loss and harmonic content An asymmetric cas-caded H-bridge topology with different and proportionalDC voltage source values is reported in [4] This reducesthe capacity and number of the devices as well as the costsA sine-wave pulse width modulation (SPWM) three-phasemultilevel inverter topology may be achieved by insertingtwo auxiliary switches in each phase bridge to change thebasic two-level to three-level inverter to synthesize higherlevels [3] In comparisonwith traditional diode clamps flying


(8) H5 topology



Basic units Aand B

Basic units Aand C

(17) T-typetopology

(5) SC-HB topology




(10) OH5 topology





(9) Heric topology




S1

V

S2

(a) Basic unit A

Vo1 Vo2

V1

V2

S1

S2

S3

S4


V1

V2

V3

S1

S2

S3

S4

Vo1

Vo2




Sa2

Sc3Sc2

Sb3E

Sa3

Sb2

E

E A

B

O

Sa1

Sc2

Sb3Sb2

Sa3Sa2

Sc3

Sb1

Sa4

C

Sc1

Sb4 Sc4

Sa1

Sa4

Cdc1

Cdc2


Cdc

1

2

3

4

V

S1

S2

S3

S4

S5

L1

L2

C1 GridM

(a)

Cdc1

V

N

S1

S2

S3

S4

S5

S6

L1

L2

C1

GridM

(b)

N

Cdc1

Cdc2

V

S1

S2

S3

S4

S5

S6

L1

L2

C1 GridM

(c)

V

N

P

O

Cdc1

Cdc2

L1

L2

C1

GridM

Sa1

Sa2 Sa3

Sa4

Sb1

Sb2Sb3

Sb4

A

B

(d)












Cdc1

Cdc2

N

P

VO

Sa1

Sa2

Sa3

Sa4

Sb1

Sb2

Sb3

Sb4

A

B

C

da1da2

da3

da4

Sc1

Sc2

Sc3

Sc4


＞1

＞2

６

３1

３2

３3

３4

３＜1

３＜2

３＜3

３＜4

A BC

３＝1

３＝2

３＝3

３＝4

＄1

＄2

２

２

２

+minus










(3)







(100)(0-1-1)

(11-1)

(1-1-1)

(010) (10-1)(0-10)

(01-1)(-11-1)

(-110)

(-101)

(-1-11) (0-11) (1-11)

(1-10)

(110)(00-1)

(011)(-100)

(001)(-1-10)

(101)(0-10)

(000)(111)(-1-1-1)








Steps






IGBT Sa1 9045 2646 11692Sa2 3178 103 3282




NPC 1 99888 31072 13096 08690Hybrid T-type 1 89844 31944 121788 08782












119881120572119879119904 = 1198791 100381610038161003816100381611988111003816100381610038161003816 + 1198792 100381610038161003816100381611988121003816100381610038161003816 cos 1205873119881120573119879119904 = 1198792 100381610038161003816100381611988121003816100381610038161003816 sin 1205873119879119904 = 1198791 + 1198792 + 11987907(5)


(100)(0-1-1)

(1-1-1)

(10-1)

(1-10)

(110)(00-1)

(101)(0-10)

(000)

(111)(-1-1-1)

VＬ

VＩffＭＮ

VＬ

V1

V2

I

II

III

IVV

VI



(6)




Maximumamplitude

voltagevector

boundary

Maximumundistorted


boundary

I

II

III

IV

V

VI

５1

５2

５3 ５4

５5

５6

５out



(7)




1198791015840119873119910 = 119879119873119910119879119873119909 + 119879119873119910119879119873PWM1198790 = 1198797 = 0(9)


(10)










Ts

T02 T12 T22 T72 T72 T22 T12 T02

0 1 1 1 11 1 0

0 0 1 11 1 0

0 0 0 10 0 0

0

0

Tcon

Taon

Tbon

Tpwm

TNPW

M

TNaon TN

bon TNcon

TNx

TNy

TN0

TNPW

M-TN

aon

TNPW

M-TN

bon

TNPW

M-TN

bon








Current Voltage0

50

100

150

200

250

300


Current12345678


THD

( o

f fun

dam

enta

l)

0( o

f fun

dam

enta

l)TH

D


























0 20 30 40 50 60 70 8010t (s)

minus40

minus20

0

20

40

60

80

Icm

(A)

Novel T-typeT-type







4 Conclusions




Data Availability




Acknowledgments


References























RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia



(8) H5 topology



Basic units Aand B

Basic units Aand C

(17) T-typetopology

(5) SC-HB topology




(10) OH5 topology





(9) Heric topology




S1

V

S2

(a) Basic unit A

Vo1 Vo2

V1

V2

S1

S2

S3

S4


V1

V2

V3

S1

S2

S3

S4

Vo1

Vo2




Sa2

Sc3Sc2

Sb3E

Sa3

Sb2

E

E A

B

O

Sa1

Sc2

Sb3Sb2

Sa3Sa2

Sc3

Sb1

Sa4

C

Sc1

Sb4 Sc4

Sa1

Sa4

Cdc1

Cdc2


Cdc

1

2

3

4

V

S1

S2

S3

S4

S5

L1

L2

C1 GridM

(a)

Cdc1

V

N

S1

S2

S3

S4

S5

S6

L1

L2

C1

GridM

(b)

N

Cdc1

Cdc2

V

S1

S2

S3

S4

S5

S6

L1

L2

C1 GridM

(c)

V

N

P

O

Cdc1

Cdc2

L1

L2

C1

GridM

Sa1

Sa2 Sa3

Sa4

Sb1

Sb2Sb3

Sb4

A

B

(d)












Cdc1

Cdc2

N

P

VO

Sa1

Sa2

Sa3

Sa4

Sb1

Sb2

Sb3

Sb4

A

B

C

da1da2

da3

da4

Sc1

Sc2

Sc3

Sc4


＞1

＞2

６

３1

３2

３3

３4

３＜1

３＜2

３＜3

３＜4

A BC

３＝1

３＝2

３＝3

３＝4

＄1

＄2

２

２

２

+minus










(3)







(100)(0-1-1)

(11-1)

(1-1-1)

(010) (10-1)(0-10)

(01-1)(-11-1)

(-110)

(-101)

(-1-11) (0-11) (1-11)

(1-10)

(110)(00-1)

(011)(-100)

(001)(-1-10)

(101)(0-10)

(000)(111)(-1-1-1)








Steps






IGBT Sa1 9045 2646 11692Sa2 3178 103 3282




NPC 1 99888 31072 13096 08690Hybrid T-type 1 89844 31944 121788 08782












119881120572119879119904 = 1198791 100381610038161003816100381611988111003816100381610038161003816 + 1198792 100381610038161003816100381611988121003816100381610038161003816 cos 1205873119881120573119879119904 = 1198792 100381610038161003816100381611988121003816100381610038161003816 sin 1205873119879119904 = 1198791 + 1198792 + 11987907(5)


(100)(0-1-1)

(1-1-1)

(10-1)

(1-10)

(110)(00-1)

(101)(0-10)

(000)

(111)(-1-1-1)

VＬ

VＩffＭＮ

VＬ

V1

V2

I

II

III

IVV

VI



(6)




Maximumamplitude

voltagevector

boundary

Maximumundistorted


boundary

I

II

III

IV

V

VI

５1

５2

５3 ５4

５5

５6

５out



(7)




1198791015840119873119910 = 119879119873119910119879119873119909 + 119879119873119910119879119873PWM1198790 = 1198797 = 0(9)


(10)










Ts

T02 T12 T22 T72 T72 T22 T12 T02

0 1 1 1 11 1 0

0 0 1 11 1 0

0 0 0 10 0 0

0

0

Tcon

Taon

Tbon

Tpwm

TNPW

M

TNaon TN

bon TNcon

TNx

TNy

TN0

TNPW

M-TN

aon

TNPW

M-TN

bon

TNPW

M-TN

bon








Current Voltage0

50

100

150

200

250

300


Current12345678


THD

( o

f fun

dam

enta

l)

0( o

f fun

dam

enta

l)TH

D


























0 20 30 40 50 60 70 8010t (s)

minus40

minus20

0

20

40

60

80

Icm

(A)

Novel T-typeT-type







4 Conclusions




Data Availability




Acknowledgments


References























RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia



Sa2

Sc3Sc2

Sb3E

Sa3

Sb2

E

E A

B

O

Sa1

Sc2

Sb3Sb2

Sa3Sa2

Sc3

Sb1

Sa4

C

Sc1

Sb4 Sc4

Sa1

Sa4

Cdc1

Cdc2


Cdc

1

2

3

4

V

S1

S2

S3

S4

S5

L1

L2

C1 GridM

(a)

Cdc1

V

N

S1

S2

S3

S4

S5

S6

L1

L2

C1

GridM

(b)

N

Cdc1

Cdc2

V

S1

S2

S3

S4

S5

S6

L1

L2

C1 GridM

(c)

V

N

P

O

Cdc1

Cdc2

L1

L2

C1

GridM

Sa1

Sa2 Sa3

Sa4

Sb1

Sb2Sb3

Sb4

A

B

(d)












Cdc1

Cdc2

N

P

VO

Sa1

Sa2

Sa3

Sa4

Sb1

Sb2

Sb3

Sb4

A

B

C

da1da2

da3

da4

Sc1

Sc2

Sc3

Sc4


＞1

＞2

６

３1

３2

３3

３4

３＜1

３＜2

３＜3

３＜4

A BC

３＝1

３＝2

３＝3

３＝4

＄1

＄2

２

２

２

+minus










(3)







(100)(0-1-1)

(11-1)

(1-1-1)

(010) (10-1)(0-10)

(01-1)(-11-1)

(-110)

(-101)

(-1-11) (0-11) (1-11)

(1-10)

(110)(00-1)

(011)(-100)

(001)(-1-10)

(101)(0-10)

(000)(111)(-1-1-1)








Steps






IGBT Sa1 9045 2646 11692Sa2 3178 103 3282




NPC 1 99888 31072 13096 08690Hybrid T-type 1 89844 31944 121788 08782












119881120572119879119904 = 1198791 100381610038161003816100381611988111003816100381610038161003816 + 1198792 100381610038161003816100381611988121003816100381610038161003816 cos 1205873119881120573119879119904 = 1198792 100381610038161003816100381611988121003816100381610038161003816 sin 1205873119879119904 = 1198791 + 1198792 + 11987907(5)


(100)(0-1-1)

(1-1-1)

(10-1)

(1-10)

(110)(00-1)

(101)(0-10)

(000)

(111)(-1-1-1)

VＬ

VＩffＭＮ

VＬ

V1

V2

I

II

III

IVV

VI



(6)




Maximumamplitude

voltagevector

boundary

Maximumundistorted


boundary

I

II

III

IV

V

VI

５1

５2

５3 ５4

５5

５6

５out



(7)




1198791015840119873119910 = 119879119873119910119879119873119909 + 119879119873119910119879119873PWM1198790 = 1198797 = 0(9)


(10)










Ts

T02 T12 T22 T72 T72 T22 T12 T02

0 1 1 1 11 1 0

0 0 1 11 1 0

0 0 0 10 0 0

0

0

Tcon

Taon

Tbon

Tpwm

TNPW

M

TNaon TN

bon TNcon

TNx

TNy

TN0

TNPW

M-TN

aon

TNPW

M-TN

bon

TNPW

M-TN

bon








Current Voltage0

50

100

150

200

250

300


Current12345678


THD

( o

f fun

dam

enta

l)

0( o

f fun

dam

enta

l)TH

D


























0 20 30 40 50 60 70 8010t (s)

minus40

minus20

0

20

40

60

80

Icm

(A)

Novel T-typeT-type







4 Conclusions




Data Availability




Acknowledgments


References























RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia








Cdc1

Cdc2

N

P

VO

Sa1

Sa2

Sa3

Sa4

Sb1

Sb2

Sb3

Sb4

A

B

C

da1da2

da3

da4

Sc1

Sc2

Sc3

Sc4


＞1

＞2

６

３1

３2

３3

３4

３＜1

３＜2

３＜3

３＜4

A BC

３＝1

３＝2

３＝3

３＝4

＄1

＄2

２

２

２

+minus










(3)







(100)(0-1-1)

(11-1)

(1-1-1)

(010) (10-1)(0-10)

(01-1)(-11-1)

(-110)

(-101)

(-1-11) (0-11) (1-11)

(1-10)

(110)(00-1)

(011)(-100)

(001)(-1-10)

(101)(0-10)

(000)(111)(-1-1-1)








Steps






IGBT Sa1 9045 2646 11692Sa2 3178 103 3282




NPC 1 99888 31072 13096 08690Hybrid T-type 1 89844 31944 121788 08782












119881120572119879119904 = 1198791 100381610038161003816100381611988111003816100381610038161003816 + 1198792 100381610038161003816100381611988121003816100381610038161003816 cos 1205873119881120573119879119904 = 1198792 100381610038161003816100381611988121003816100381610038161003816 sin 1205873119879119904 = 1198791 + 1198792 + 11987907(5)


(100)(0-1-1)

(1-1-1)

(10-1)

(1-10)

(110)(00-1)

(101)(0-10)

(000)

(111)(-1-1-1)

VＬ

VＩffＭＮ

VＬ

V1

V2

I

II

III

IVV

VI



(6)




Maximumamplitude

voltagevector

boundary

Maximumundistorted


boundary

I

II

III

IV

V

VI

５1

５2

５3 ５4

５5

５6

５out



(7)




1198791015840119873119910 = 119879119873119910119879119873119909 + 119879119873119910119879119873PWM1198790 = 1198797 = 0(9)


(10)










Ts

T02 T12 T22 T72 T72 T22 T12 T02

0 1 1 1 11 1 0

0 0 1 11 1 0

0 0 0 10 0 0

0

0

Tcon

Taon

Tbon

Tpwm

TNPW

M

TNaon TN

bon TNcon

TNx

TNy

TN0

TNPW

M-TN

aon

TNPW

M-TN

bon

TNPW

M-TN

bon








Current Voltage0

50

100

150

200

250

300


Current12345678


THD

( o

f fun

dam

enta

l)

0( o

f fun

dam

enta

l)TH

D


























0 20 30 40 50 60 70 8010t (s)

minus40

minus20

0

20

40

60

80

Icm

(A)

Novel T-typeT-type







4 Conclusions




Data Availability




Acknowledgments


References























RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia







(3)







(100)(0-1-1)

(11-1)

(1-1-1)

(010) (10-1)(0-10)

(01-1)(-11-1)

(-110)

(-101)

(-1-11) (0-11) (1-11)

(1-10)

(110)(00-1)

(011)(-100)

(001)(-1-10)

(101)(0-10)

(000)(111)(-1-1-1)








Steps






IGBT Sa1 9045 2646 11692Sa2 3178 103 3282




NPC 1 99888 31072 13096 08690Hybrid T-type 1 89844 31944 121788 08782












119881120572119879119904 = 1198791 100381610038161003816100381611988111003816100381610038161003816 + 1198792 100381610038161003816100381611988121003816100381610038161003816 cos 1205873119881120573119879119904 = 1198792 100381610038161003816100381611988121003816100381610038161003816 sin 1205873119879119904 = 1198791 + 1198792 + 11987907(5)


(100)(0-1-1)

(1-1-1)

(10-1)

(1-10)

(110)(00-1)

(101)(0-10)

(000)

(111)(-1-1-1)

VＬ

VＩffＭＮ

VＬ

V1

V2

I

II

III

IVV

VI



(6)




Maximumamplitude

voltagevector

boundary

Maximumundistorted


boundary

I

II

III

IV

V

VI

５1

５2

５3 ５4

５5

５6

５out



(7)




1198791015840119873119910 = 119879119873119910119879119873119909 + 119879119873119910119879119873PWM1198790 = 1198797 = 0(9)


(10)










Ts

T02 T12 T22 T72 T72 T22 T12 T02

0 1 1 1 11 1 0

0 0 1 11 1 0

0 0 0 10 0 0

0

0

Tcon

Taon

Tbon

Tpwm

TNPW

M

TNaon TN

bon TNcon

TNx

TNy

TN0

TNPW

M-TN

aon

TNPW

M-TN

bon

TNPW

M-TN

bon








Current Voltage0

50

100

150

200

250

300


Current12345678


THD

( o

f fun

dam

enta

l)

0( o

f fun

dam

enta

l)TH

D


























0 20 30 40 50 60 70 8010t (s)

minus40

minus20

0

20

40

60

80

Icm

(A)

Novel T-typeT-type







4 Conclusions




Data Availability




Acknowledgments


References























RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia





IGBT Sa1 9045 2646 11692Sa2 3178 103 3282




NPC 1 99888 31072 13096 08690Hybrid T-type 1 89844 31944 121788 08782












119881120572119879119904 = 1198791 100381610038161003816100381611988111003816100381610038161003816 + 1198792 100381610038161003816100381611988121003816100381610038161003816 cos 1205873119881120573119879119904 = 1198792 100381610038161003816100381611988121003816100381610038161003816 sin 1205873119879119904 = 1198791 + 1198792 + 11987907(5)


(100)(0-1-1)

(1-1-1)

(10-1)

(1-10)

(110)(00-1)

(101)(0-10)

(000)

(111)(-1-1-1)

VＬ

VＩffＭＮ

VＬ

V1

V2

I

II

III

IVV

VI



(6)




Maximumamplitude

voltagevector

boundary

Maximumundistorted


boundary

I

II

III

IV

V

VI

５1

５2

５3 ５4

５5

５6

５out



(7)




1198791015840119873119910 = 119879119873119910119879119873119909 + 119879119873119910119879119873PWM1198790 = 1198797 = 0(9)


(10)










Ts

T02 T12 T22 T72 T72 T22 T12 T02

0 1 1 1 11 1 0

0 0 1 11 1 0

0 0 0 10 0 0

0

0

Tcon

Taon

Tbon

Tpwm

TNPW

M

TNaon TN

bon TNcon

TNx

TNy

TN0

TNPW

M-TN

aon

TNPW

M-TN

bon

TNPW

M-TN

bon








Current Voltage0

50

100

150

200

250

300


Current12345678


THD

( o

f fun

dam

enta

l)

0( o

f fun

dam

enta

l)TH

D


























0 20 30 40 50 60 70 8010t (s)

minus40

minus20

0

20

40

60

80

Icm

(A)

Novel T-typeT-type







4 Conclusions




Data Availability




Acknowledgments


References























RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia





Maximumamplitude

voltagevector

boundary

Maximumundistorted


boundary

I

II

III

IV

V

VI

５1

５2

５3 ５4

５5

５6

５out



(7)




1198791015840119873119910 = 119879119873119910119879119873119909 + 119879119873119910119879119873PWM1198790 = 1198797 = 0(9)


(10)










Ts

T02 T12 T22 T72 T72 T22 T12 T02

0 1 1 1 11 1 0

0 0 1 11 1 0

0 0 0 10 0 0

0

0

Tcon

Taon

Tbon

Tpwm

TNPW

M

TNaon TN

bon TNcon

TNx

TNy

TN0

TNPW

M-TN

aon

TNPW

M-TN

bon

TNPW

M-TN

bon








Current Voltage0

50

100

150

200

250

300


Current12345678


THD

( o

f fun

dam

enta

l)

0( o

f fun

dam

enta

l)TH

D


























0 20 30 40 50 60 70 8010t (s)

minus40

minus20

0

20

40

60

80

Icm

(A)

Novel T-typeT-type







4 Conclusions




Data Availability




Acknowledgments


References























RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia





Ts

T02 T12 T22 T72 T72 T22 T12 T02

0 1 1 1 11 1 0

0 0 1 11 1 0

0 0 0 10 0 0

0

0

Tcon

Taon

Tbon

Tpwm

TNPW

M

TNaon TN

bon TNcon

TNx

TNy

TN0

TNPW

M-TN

aon

TNPW

M-TN

bon

TNPW

M-TN

bon








Current Voltage0

50

100

150

200

250

300


Current12345678


THD

( o

f fun

dam

enta

l)

0( o

f fun

dam

enta

l)TH

D


























0 20 30 40 50 60 70 8010t (s)

minus40

minus20

0

20

40

60

80

Icm

(A)

Novel T-typeT-type







4 Conclusions




Data Availability




Acknowledgments


References























RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia







Current Voltage0

50

100

150

200

250

300


Current12345678


THD

( o

f fun

dam

enta

l)

0( o

f fun

dam

enta

l)TH

D


























0 20 30 40 50 60 70 8010t (s)

minus40

minus20

0

20

40

60

80

Icm

(A)

Novel T-typeT-type







4 Conclusions




Data Availability




Acknowledgments


References























RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia












0 20 30 40 50 60 70 8010t (s)

minus40

minus20

0

20

40

60

80

Icm

(A)

Novel T-typeT-type







4 Conclusions




Data Availability




Acknowledgments


References























RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia




Data Availability




Acknowledgments


References























RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia




RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia


a novel hybrid t-type three-level inverter based on svpwm for...

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