a new built in self test pattern generator
DESCRIPTION
BIST Pattern Generator ppt for DFT concepts..TRANSCRIPT
Prepared By:PARTH SHAH
131060752026GTU PG SCHOOL
Low Power Dissipation & High Fault Coverage
BIST Pattern Generator
AGENDA
Introduction> BIST (Built In Self Test)> Types of Faults> TPG (Test Pattern Generator)
Architecture of Different TPG> LT-RTPG (Low Transition Random TPG)> A-3WRTPG (Arithmetic 3-Weighted Random TPG)
Comparison of> Fault Covered> Power Consumption> Gate Count
Conclusion References
• What is BIST?– Built In Self Test– Concept of Buit In Test + Self Test
• Why BIST– Today’s Test Requirement for SoC Complexity– Detect un-modeled Faults– Provide Remote Diagnosis
INTRODUCTION
BIST WORKING
Hardware Pattern
GeneratorInputMux
Circuit Under Test(CUT)
With optional modification
Test Controller
Output Response
Comparator
Primary Input Primary
OutputSignatu
re
Test
Figure 1: BIST Block Diagram
FAULT TYPESFAULT TYPES
Easy To DetectLFSRMore
Transition
LT-RTPGConventional
LFSR
2x1 MUX
Random Pattern Resistance A-3WRTPG
Modified form of Weighted TPG
Figure 2 : Fault Types
TEST PATTERN GENRATOR
• Techniques available for TPG– Ad-Hoc Circuitry
• Large Circuit should be partitioned into smaller sub-circuits.• Manual Test Access Point still Required.• Asynchronous logic feedback must be avoided.
– LFSR• Reduce Correlation between successive test vectors • Most popular due to compact and simple structure
– Cellular Automata• The CA are very similar to the LFSRs except that the
registers in CA have a logical relationship with their neighbors only.
– BILBO• Selection of TPG based on Fault Types
TEST PATTERN GERATOR
Different Methods for LT-RTPG
1. Running Test at slower Frequency.• Easy to Implement.• Increase Test Application Time.• Fails to reduce peak power.
2. Scain Chain Ordering• Reduce average power consumption during scan in and scan out• Fails to reduce peak capture power during testing
3. X-filling Technique• Assign values to the don’t care bits of a deterministic set of test
vectors.
LT-RTPG
Figure 3: Architecture Of Low Transition Random Test Pattern Generator
Less Hardware T FF holds Previous Value until Input is 1 Output of AND Gate will be 1 for every 15 pattern generated by BS-LFSR The Adjacent scan flip flops are assigned identical values in most test patterns so scan input have fewer transition during scan shift operation.
BS-LFSR
Figure 4: Architecture of Bit Swapping Linear Feedback Shift Register
Generates same no of 1’s and 0’s at multiplexers after swapping of two adjacent cells. Output of Mux depends on three different cells of LFSR.
A 3-WRTPG
Weights are altered in range of 0 to 1.3 weights are assigned.Utilization of adder modules reduce Hardware overhead. Values can be based on three different condition of Set and Reset.
Figure 5: Architecture of Arithmetic 3-Weighted Random Test Pattern Generator
FULL ADDER TRUTH TABLE
Configuration 1: Set[i] = 1 & Reset[i] = 0 henceA[i] = 1 & B[i] = 0 Cout = 1 = Cin
Configuration 2: Set[i] = 0 & Reset[i] = 1 henceA[i] = 0 & B[i] = 1 Cout = 0 = Cin
Configuration 3: Set[i] = 0 & Reset[i] = 0 henceA[i] = ‘-‘ & B[i] = 1/0 Depending on value that will be added to the accumulator input in order to produce suitable random pattern to input of CUT.
# Cin A[i] B[i] S[i] Cout Comment
1 0 0 0 0 0
2 0 0 1 1 0 Cout = Cin
3 0 1 0 1 0 Cout = Cin
4 0 1 1 0 1
5 1 0 0 1 0
6 1 0 1 0 1 Cout = Cin
7 1 1 0 0 1 Cout = Cin
8 1 1 1 1 1
PROPOSED ARCHITECTURE
RESULT COMPARISON
• We will compare Simulation Result, Power Analysis and Synthesis result of all the Architecture.
• Simulation Result were obtained from modelsim 6.5 by setting clock frequency 10MHz. • Synthesis Result were obtained from Xilinx 8.2 version.
• 10 Faults: 4 Easy to Detect & 6 Random Pattern Resistance
PATTERN GENERATED
EASY TO DETECT FAULT
LT-RTPG USING LFSR
LT-RTPG USING BS-LFSR
Only 3 Faults Detected by simple LFSR
4 Easy to Detect Faults Detected by BS-LFSR
Fault Coverage is Improved to 15%
TOTAL FAULTS COVERED
Using Simple BIST TPG total 6 Faults are Detected
SIMPLE BIST TPG
PROPOSED BIST TPG
With Proposed BIST we can detect all 9 Faults are Detected
Fault Coverage is Improved to 25%
POWER ANALYSIS
LT-RTPG Using LFSR
LT-RTPG Using
BS-LFSR
Arithmetic BIST
BIST TPG[1]
Proposed BIST TPG
Total Quiescent
Power0.025 0.025 0.025 0.025 0.025
Total Dynamic
Power0.062 0.039 0.050 0.159 0.123
Total Power 0.086 0.063 0.074 0.183 0.148
As seen from above table there is a reduction in power consumption when used BS-LFSR instead of LFSR
BIST TPG Proposed BIST TPG
Number of GCLKs 1 1
Number of GCLKIOBs 1 1
Total Equivalent Gate Count for Design
324 300
Additional JTAG gate count for IOBs
912 528
GATE COUNT ESTIMATION
So we can say that Proposed BIST occupied considerably less area than that of BIST TPG.
CONCLUSION
• With Proposed BIST TPG– Power Consumption is 15% reduced – Fault Coverage almost 100%– Area Occupied is 40% reduced
REFERENCES
1) Seongmoon Wang, “A BIST TPG for low power dissipation and high fault coverage”, IEEE transaction on VLSI systems vol.15, no.7, july 2007
2) Abdallatif S abu-issa and Steven F. Quigley, “Bit-Swapping and scan chain ordering: A Novel technique for peak and average power reduction in scan based BIST”, IEEE transactions on computer aided design of integrated circuits and systems, Vol.28, No.5, May 2009
3) Chand SR, Srinivas.V, Sai T.V., Sailaja.M, and Madhu.J., “Fault diagnosis using TPG low power dissipation and fault coverage ”,Published in Computational intelligence and computing research (ICCIC), 2010 IEEE international conference.
4) M. Chatterjee and D. K. Pradhan, “A new pattern biasing technique for BIST,” in Proc. VLSITS, 1995, pp. 417–425.