a multi technology gate array layout system

10
CGAL - A MULTI TECHNOLOGY GATE ARRAY LAYOUT SYSTEM L. F. Todd, J. M. Hansen, S. V. Pantulu J. L. Barron, D. J. Gilbert, R. J. Anderson, A. K. Biyani Computer Aided Design, Roseville, MN ABSTRACT This paper describes the Computerized Gate Array Lay- out system (CGAL), a general purpose tool developed at Sperry Univac to provide efficient and reliable auto- mated layouts for a variety of master slice arrays. The system contains algorithms for the construction of initial placement, placement improvement c glDbal routing, channel routing and planar routing. The system also provides for user interaction through a design language and graphical output. A wide range of device types encompassing significantly different cell topologies and complexity are presently in production use. Some of the problems encountered are discussed and results are presented for different technologies. INTRODUCTION The advantages of low cost, fast turnaround devices referred to as master slices, uncommitted logic arrays or gate arrays are well known and documented (TANSl, RAMSO, HIGHSO). Several gate arrays ranging from in size 360 to 1400 array cells and in cell complexity from 3 to 13 tran- sistors were being designed at different chip design centers within Sperry Univac when the CGAL development was begun. It was apparent that an automated layout system was required which: I) Interfaced with the existing CAD systems 2) Could accomodate different chip technologies and cell topologies (initial designs using CMOS, Schottky TTL and IOK ECL were in progress) 3) Permitted both high and low volume applications 4) Offered possible extensions to larger applications 5) Provided flexibility in the logic design interface area to accomodate the varying design practices in use at Sperry. The CGAL system was developed to interface cleanly with the Sperry Univac Computer Aided Design (UCAD) System, thus assuring access to logic simulation, test list generation, timing analysis, higher level logical and physical design tools, hierarchical data base and documentation aids. Calma and Applicon systems were already in use for gate array cell design and custom IC design on a limited basis. These systems offered a straightforward pattern mask gener- ation capability and an interactive graphic tool for manual completion of routes or engineering changes should they be necessary. CGAL was therefore provided with an output in CALMA GDSII stream format which could be translated to Applicon Apple format where necessary. General purpose systems with flexibility toward tech- nology requirements and growth potential have been reported on throughout the last decade (CHEN77, PER76j HIGH80). The general approach has consisted first of a constructive initial placement~ followed by an item- ative interchange technique typically using net length as the cost criteria. Some specific consideration to wire congestion (KH081) may also be done at this point. A global routing step is next which explores alternate netting configurations to eliminate local wiring density problems. The ordering of nets for consider- ation and the modeling of vertical constraints offer the opportunity for considerable variation in this area. Both single pass (TANSl) and multipass approaches (HIGHS0, CHEN77) are used. An assignment of net segments to routing channels precedes the detailed routing stage. Detailed routing is normally done with a channel router (HASH71, DEU76) employing a constraint breaking procedure either prior to or during the routing process. Again a variety of methods for handling vertical constraints have been suggested (WAD81, YOUSl). Our problem was to put together a system which util- ized these basic Components to handle a wide variety of applications. Examination of these applications indicated that pin accessability, routing constraints and electrical rule constraints would become major obstacles. In addition to the basic Components of placement and routing, an effective language for describing the design was essential to a general purpose system. Two areas for design description existed: I) the physical characteristics of the chip; 2) the logic design of the function(s) to be imple- mented on the chip. Typically the first of these is done by a chip designer and defines the character- istics and design rules common to all utilizations of the chip. The second consists of the circuits and their interrelationships along with some application specific design constraints (e.g.~ clocking rules, critical paths, preplaced circuits). We found it useful to define two types of interrelationships to exist between circuits, one of connectivity~ the second of hierarchy. Both of these can be constrained and valued by the logic designer. DEFINITION AND MODEL A circuit is an electrical device which performs a logical function. A cell represents the design primitive used in CGAL. It consists of a defined set of electrical components which may be interconnected to form a circuit. The options available in inter- connections are termed metal options. Cell complexity Paper 44.3 7 9 2 19th Design Automation Conference 0420-0098/82/0000/0792500.75 © 1982 IEEE

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Page 1: A MULTI TECHNOLOGY GATE ARRAY LAYOUT SYSTEM

8/7/2019 A MULTI TECHNOLOGY GATE ARRAY LAYOUT SYSTEM

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C G A L - A M U L T I T E C H N O L O G Y G A T E A R R A Y L A Y O U T S Y S T E M

L . F . T o d d , J . M . H a n s e n , S . V . P a n t u l u

J . L . B a r r o n , D . J. G i l b e r t , R . J. A n d e r s o n , A . K. B i y a n i

C o m p u t e r A i d e d D e s i g n , R o s e v i l l e , M N

A B S T R A C T

This paper describes the Computeriz ed Gate Array Lay-

out system (CGAL), a general purpose tool develo ped at

Sperry Univac to provide e fficient and reliable auto-

mated layouts for a variet y of master slice arrays.

The system contains algorithm s for the constru ction of

initial placeme nt, placemen t improvement c glDbal

routing, channel routing and planar routing. The

system also provides for user interact ion through a

design language and graphica l output.

A wide range of device types encomp assing sig nifican tly

differen t cell topologies and complex ity are present ly

in product ion use. Some of the problems encoun tered

are discusse d and results are presente d for different

technologies.

I N T R O D U C T I O N

The advantages of low cost, fast turnaround devices

referred to as mast er slices, uncommi tted logic

arrays or gate arrays are well kno wn and document ed

(TANSl, RAMSO, HIGHSO).

Several gate arrays ranging from in size 360 to 1400

array cells and in cell comp lexi ty from 3 to 13 tran-

sistors were being desi gned at different chip design

centers within Sperry Univac when the CGAL development

was begun. It was appare nt that an automated layout

s y s t e m w a s r e q u i r e d w h i c h :

I) Interfaced with the existin g CAD systems

2) Could accomodate diffe rent chip technologies and

cell topologies (initial designs using CMOS,

Schottky TTL and IOK ECL were in progress)

3) Permit ted both high and low volume applications

4) Offered possibl e extensions to larger applications

5) Provid ed fle xibility in the logic design interfa ce

area to accomodate the varyin g design practices in

use at Sperry.

T h e C G A L s y s t e m w a s d e v e l o p e d t o i n t e r f ac e c l e a n l y

with the Sperry Univac Comput er Aided Design (UCAD)

System, thus assuri ng access to logic simulation,

test list generation, tim ing analysis, highe r level

logical and physical de sign tools, hierar chical data

base and documen tation aids. Calma and Applico n

systems were already in use for gate array cell design

and custom IC design on a limited basis. These

s y s t e m s o f f e r e d a s t r a i g h t f o r w a r d p a t t e r n m a s k g e n e r -

ation capabilit y and an interactiv e graphic tool for

m a n u a l c o m p l e t i o n o f r o u t e s o r e n g i n e e r i n g c h a n g e s

should they be necessary . CGAL was therefore provided

with an output in CALMA GDSII stre am format which

c o u l d b e t r a n s l a t e d t o A p p l i c o n A p p l e f o r m at w h e r e

necessary.

General purpose systems with flexibility to ward tech-

n o l o g y r e q u i r e m e n t s a n d g r o w t h p o t e n t i a l h a v e b e e n

reported on throughout the last decade (CHEN77, PER76j

HIGH80). The general approach has consisted first of

a construct ive initial placement ~ followed by an item-

ative interchange techni que typically using net length

as the cost criteria. Some specific conside ration to

wire congestion (KH081) m ay also be done at this point.

A global routing step is next which explores alternate

n e t t i n g c o n f i g u r a t i o n s t o e l i m i n a t e l o c a l w i r i n g

density problems. The order ing of nets for consider-

ation and the modeli ng of vertic al cons traints offer

the opportunity for considerable variatio n in this

area. Both single pass (TANSl) and multipa ssapproaches (HIGHS0, CHEN77) are used. An assignment

of net segments to routing channels precedes the

detailed routing stage.

D e t a i l e d r o u t i n g i s n o r m al l y d o n e w i t h a c h a n n el

router (HASH71, DEU76) emp loying a constra int breaking

procedu re either prior to or during the routing

process. Again a variety of methods for hand ling

v e r t i c a l c o n s t r a i n t s h a v e b e e n s u g g e s t e d ( W A D 8 1,

YOUSl).

Our proble m was to put together a system which util-

ized these basic Com ponents to handle a wide variety

of applications. Examination of these applicati ons

indicated that pin accessabil ity, routi ng constraints

and electrical rule const raints would become majo r

obstacles. In addition to the basic Components of

placemen t and routing, an effective language fordescri bing the design was essential to a general

purpose system. Two areas for design description

existed: I) the physical character istics of the chip;

2) the logic design of the function(s) to be imple-

mented on the chip. Typicall y the first of these is

done by a chip designer and defines the character-

istics and design rules common to all utilizati ons of

the chip. The second consists of the circuits and

t h e i r i n t e r r e l a t i o ns h i p s a l o n g w i t h s o m e a p p l i c a t i o n

specific design constraints (e.g.~ clo cking rules,

critical paths, preplace d circuits). We found it

useful to define two types of interrelationship s to

exist between circuits, one of connectivit y~ the

second of hierarchy. Both of these can be constrained

and valued by the logic designer.

D E F I N I T I O N A N D M O D E L

A circuit is an electrical device which perform s a

logical function. A cell represents the design

primitive used in CGAL. It consists of a defined set

o f e l e c t r i c a l c o m p o n e n t s w h i c h m a y b e i n t e r c o n n e c t e d

to form a circuit. The options available in inter-

connections are termed metal options. Cell complexity

Paper4 4 . 37 9 2

1 9 t h D e s i g n A u t o m a t i o n C o n f e r e n c e

0 4 2 0 - 0 0 9 8 / 8 2 /0 0 0 0 / 0 7 9 2 5 0 0 . 7 5 © 1 9 8 2 I E E E

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c a n v a r y s i g n i f i c a n t l y f r o m c h i p t o c h i p o r w i t h i n

a c h i p r a n g i n g f r o m a b a s i c l o g i c g a t e t o a c o l l e c t i o n

o f c o m p l e x g a t e s . ( F i g u r e I)

KE__SY

= l o c a t i o n s

w h e r e v i a s

are not

~ . a l l o w e d

E l ] = t r a c k s

b l o c k e d i n

L a y e r 1

0 = tracks

b l o c k e d i n

L a y e r 2

!i ~IIl

CA ELL i ]

, ' , , - , , - , i t

T T L C A C E L L C M O S C E L L

F i g u r e 1

I n a g a t e a r r a y s t r u c t u r e , o r C G A L c h i p , t h e c e l l s a r e

p r e l o c a t e d o n t h e c h i p s u r f a c e i n a r e g u l a r a r r a y .

T h e r e a r e t h r e e m a j o r t y p e s o f c e ll s : i n t e r n a l ,

e x t e r n a l , a n d I / O p a d . T h e i n t e r n a l c e l l s c o m p r i s e

t h e i n t e r n a l a r e a o f t h e c h i p a n d a r e u s e d f o r t h e

m a j o r i t y o f t h e l o g i c d e s i g n . E x t e r n a l c e l l s a r e I /0

b u f f e r s w h i c h a r e p r i m a r i l y u s e d f o r i n t e r f a c i n g w i t h

I / O p a d s . I / O p a d s a r e u s e d f o r c o n n e c t i o n s t h a t

l e a v e t h e c h i p . A m o d e l o f t h e c h i p is s h o w n i n

F i g u r e 2 .

SgODDDDDDD/°E X T E R N A L C E L L S O

D I I I l l " [ E i cL S - O

D L coL° - O

I - I - S l l l l l l l I L l O• ,\

0 . , i i i i i i l i l R T _ O

nhooonooo6°

PADS

F i g u r e 2

R o w s a r e n o n - o v e r l a p p i n g h o r i z o n t a l r e g i o n s o f a d j a -

c e n t c e l l s . T h e r e a r e t h r e e t y p e s o f r c ~ s : ( I ) i n t e r -

n a l c e l l t y p e s , ( 2 ) e x t e r n a l c e l l t y p e s , a n d ( 3 ) I / O

p a d c e l l t y p e s .

C o l u m n s a r e n o n - o v e r l a p p i n g v e r t i c a l r e g i o n s o f c e l l s .

T h e r e a r e f o u r t y p e s o f c o l u m n s : ( I ) c o l u m n s o f c e l l s

w h i c h d e f i n e p l a c e m e n t c e l l s i t e s w h e n u s e d w i t h r o w s ,

( 2 ) i n t e r n al p a r t i t i o n s u s e d i n g l o b a l a n d v e r t i c a l

r o u t i n g , ( 3 ) l e f t e x t e r n a l , a n d ( 4 ) r i g h t e x t e r n a l .

E x t e r n a l c o l u m n s a r e s i m i l a r t o r o w s o n l y v e r t i c a l .

C h a n n e l s p a r t i t i o n t h e c h i p i n t o l o c a l r o u t i n g a r e a s .

T h e r e a r e t w o k i n d s o f c h a n n e l s , h o r i z o n t a l a n d v e r t i -

c a l . A h o r i z o n t a l c h a n n e l i s t w o a d j a c e n t r o w s a n d

t h e r e g i o n b e t w e e n t h e m . A n e x t e r n a l v e r t i c a l c h a n n e l

i s t w o a d j a c e n t c o l u m n s , o f w h i c h o n e i s e x t e r n a l , a n d

t h e r e g i o n b e t w e e n t h e c o l u m n s . A n i n t e r n a l v e r t i c a l

c h a n n e l i s a n i n t e r n a l v e r t i c a l c o l u m n o f i n t e r n a l

c e l l t y p e s .

K E Y

X = pin locatio n

* = a l t e r n a t e p i n l o c a t i o n

O = v i a s u s e d i n t h e i m p l e m e n t a t i o n o f b o o k f r o m c el ls

C e l l C o l u m n 1 C e l l C o l u m n 2

CR

e

i o 1

i w

CR

e1 ° 2

i w

C o l u m n 1

C Y E ~ , , ,~, R

~ P C

SIA ,,. R

o

8 - i n p u t n a n dL o g i c R e p r e s e n t a t i o n ( T 2 L G A )

F i g u r e 3 F i g u r e 4

A b o o k i s t h e s p e c i f i c d e f i n i t i o n o f c e l l u t i l i z a t i o n

t o i m p l e m e n t a g i v e n l o g i c a l f u n c t i o n . E a c h l o g i c a l

c i r c u i t h ~ a n e q u i v a l e n t b o o k t y p e. A b o o k d e s c r i p -

t i o n i n d i c a t e s t h e i n t e r c o n n e c t i o n s t o b e a d d e d t o a

c e l l , i . e . , w h i c h t r a n s i s t o r s , r e s i s t o r s , e t c . t o

c o n n e c t f o r t h e c i r c u i t f u n c t i o n . A b o o k m ~ a l s o

r e p r e s e n t a l a r g e r c i r c u i t w h i c h r e q u i r e s m o r e t h a n

o n e c e l l . T h e i n t e r c o n n e c t i o n s m u s t b e d e f i n e d f o r a l l

i n t r a a n d i n t e r c e l l w i r i n g r e q u i r e d t o c o n s t r u c t a

b o o k . M u l t i - c e l l b o o ks m u s t b e r e c t a n g u l a r i n s h a p e,

n o " L " a r r a n g e m e n t s a r e a l l o w e d .

P i n s a re t he c o n t a c t p o i n t s f o r i n t e r c o n n e c t i o n s . A

p i n c a n b e u l t i m a t e l y m a p p e d t o a n i n p u t o r o u t p u t o f

t h e b o o k a n d h a s a p p r o p r i a t e e l e c t r i c a l c h a r a c t e r i s -

Pa p e r 4 4 . 37 9 3

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GATE

ARRAY

TYPIC

T T L

( S c h o t t k y

GA)

CIlIP

SIZE

MILS

2 3 5 X

235

E C L 2 3 6 X

240

C M O S 2 6 0 X

260

TOTAL

NUMBER OF

TRACKS

I[ORZ VERT

578 414

656 465

479 373

N U M B E R N U M B E R O F

NUMBE R OF OF TRANS I -

GA'I'ES TOTAL EQU[ - BAS IC TORS

IN'rER- VALENT CATE PER BASIC

NAL [/C GATES G A T E S T Y P E C E L L

816 204 1020 1020 4 5

INPUT

N A N D

360 60 420 1260 SERIE! 13

G A T E D

1296 80 1376 1376 2 4

I N P U T

N OR

NIJMI',ER

OF

CIIANNELS

VERT: IIORZ

28 37

20 13

38 19

N U M B E R O F

T R A C K S

A V A I L A B L E

F O R R O U T I N G

PER CEL|~

IIORZ' VERT

8 5 1 1 5

9 15

19 1.6

N U M B E R

O F

S I G N A L

'PINS

116

11 6

28O

T O T A L

PINS

137

13 2

84

I . D o e s n o t i n c l u d e b o o k m e t a l w h i c h e x t e n d s i n t o t h e h o r i z o n t a l c h a n n e l o r w h i c h b l o c k s v e r t i c a l

tracks running over the cell.

2. Represen ts average numbe r of feedthroughs availab le per cell.

3. The number of equivalent gates on the ECL and TTL chips can be increa sed through

e m i t t e r / c o l l e c t o r d o t t i n g o f o u t p u t s .

Tab le I

t i c s a s s o c i a t e d w i t h i t . ( e . g , , c a p a c i t a n c e , d r i v e

c a p a b i l i t y , g a t e d e l a y ) . A n e t i s a s e t o f p i n s t o b e

p h y s i c a l l y i n t e r c o n n e c te d .

A m a c r o i s a h i g h l e v e l d e s i g n r e p r e s e n t a t i o n o f a

g r o u p o f l o g i c c i r c u i t s . I t a l l o w s t h e l o g i c d e s i g n e r

t o ta k e a h i e r a r c h i c a l a p p r o a c h t o h i s d e s i g n . A

m a c r o i s p h y s i c a l l y r e a l i z e d a s a s et o f b o o k s p l a c e d

a n d i n t e r c o n n e c t e d b y t h e s o f t w a r e. A c o m m o n e x a m p l e

i s a l a t c h m a d e u p o f 4 i n p u t h a n d g a t e s . T h e u s e r

c a n c o n s t r a i n a m a c r o b y s p e c i f y i n g t h e h a l f p e r i m e t e r

o f a r e c t a n g l e e n c l o s i n g i t s p l a c e d b o o k s .

C H I P D E S C R I P T I O N S A N D D E S I G N C O N S I D E R A T I O N S

T h e C G A L s y s t e m i s c u r r e n t l y u s e d t o l a y o u t g a t e a r r a y s

o f t h r e e d i f f e r e n t t e c h n o l o g i e s - - C M O S , E C L a n d T T L.

T h e s e L S I c h i p s a r e b e i n g u s e d t o p e r f o r m a v a r i e t y

o f f u n c t i o n s i n a ll p h a s e s o f c o m p u t e r s y s t e m s ;

c o n t r o l, m e m o r y , c e n t r a l p r o c e s s i n g , I / O c o n t r o l l e r s ,

a r i t h m e t i c l o g i c u n i t s e t c . T h e t h r e e g a t e a r r a yd e s i g n s v a r y s i g n i f i c a n t l y i n c e ll t o p o l o g y , p i n

a c c e s s a b i l i t y, r o u t i n g a r e a , c e l l c o m p l e x i t y a n d I / O

d e s i g n . A l l t h r e e d e s i g n s u s e t w o m e t a l l e v e l s f o r

s i g n a l r o u t i n g i n t e r c o n n e c t i o n s . P o w e r a n d g r o u n d

b u s s e s r u n i n o n e o r b o t h o f t h e s e l a y e r s . M u l t i -

c e l l b o o k s u s i n g r o u t i n g c h a n n e l s p a c e f o r t h e c u s t o m -

i z a t i o n i n te r c o n n e c t s a r e n o t u n u su a l . L a r g e m u l t i-

c e l l b o o k s ( u p t o 1 2 c e l l s i n s o m e c a s e s ) e x i s t w i t h

c e l ls f o u n d b o t h i n s i n g l e a n d m u l t i p l e r o w / c o l u m n

c o n f i g u r a t i o n s - - F i g u r e s 3 & 4 . T a b l e I s u m m a r i z e s

s o m e o f t h e l a y o u t r e l a t e d a s p e c t s o f t h e t h r e e g a t e

a r r a y d e s i g n s . T h e b o o k s s h o w n i n F i g u r e s 3 - 5 r e v e a l

s o m e o f t h e p r o b l e m s i n p i n a c c e s s a b i l i t y , t r a c k s / c e l l

a v a i l a b l e f o r r o u t i n g a n d b o o k s i z e w h i c h a f f e c t

p l a c e m e n t a n d r o u t i n g . T h e ab i l i t y t o m a n i p u l a t e

b o o k s o f d i f f e r e n t s i z e s a n d t o b i a s t h e l a y o u t i n

f a v or o f h o r i z o n t a l o r v e r t i c a l n e t c o m p o n e n t s i s

e s s e n t i a l t o e f f e c t i v e p l a c e m e n t o f t h e s e d e v i c e s .

T h e d e s i g n o f t h e I / O b u f f e r s v a r i e s r a d i c a l l y f r o m a

c o n v e n t i o n a l l y s i m p l e o n e b u f f e r p e r I / O p a d a r r a n g e -

m e n t i n t h e C M O S c h i p t o a c o m p l e x c o n f i g u r a t i o n o n

t h e T T L c h i p w i t h 2 0 4 I / O b u f f e r s f o r 1 1 6 s i g n a l p i n s .

T h e T T L c h i p c o n t a i n s i n p u t bu f f e r s , o u t p u t b u f f e r s

a n d t r i s t at e b u f f e r s w h i c h o f f e r a f u n c t i o n a l c a p a -

b i l i t y e q u a l t o t h e i n t e r n a l g a t e a n d c a n b e u s e d a s

a n i n t e r n a l g a t e w h e n n e e d e d . I n a d d i t i o n , t h e I / O

p a d s t h e m s e l v e s c a n b e a c c e s s e d o n l y o n s e c o n d l a y e r

w h e n u s e d t o d r i v e o f f c h i p a n d i n a c o m p l e t e l y

d i f f e r e n t r o u t i n g c h a n n e l w h e n u s e d t o d r i v e g a t e s o n

t h e c h i p . A l l o f t h i s a c t i v i t y o n t h e c h i p p e r i p h e r y

w h e n c o u p l e d w i t h c o n s t r a i n e d p i n a c c e s s d u e t o p o w e r

b u s s i n g c o m b i n e s t o c r e a t ~ s i g n i f i c a n t r o u t i n g

p r o b l e m s. B o t h o f t h e b i - p o l a r d e v i c e s h a v e s i n g l e

l a y e r r o u t i n g a r e a s o n t h e c h i p p e r i p h e r y a s a r e s u l t

o f t h e f i x e d p o w e r b u s r o u t i n g .

S c a n / S e t t a b l e J - K F l i p - F l o p

(CMOS CA)

F i g u r e 5

T h e mo s t s i g n i f i c a n t t o p o l o g i c a l p r o b l e m p r e s e n t e d i n

t h e i n t e r n a l a r r a y r o u t i n g w a s t h e v a r i a t i o n i n p i n

a c c e s s b e t w e e n c h i p d e s i g n s . S t a c k e d p in s c r e a t e

s i t u a t i o n s w h e r e a c c e s s t o a p i n f r o m b o t h t h e c h a n n e l

a b o v e a n d t h e c h a n n e l b e l o w i s c o n s t r a i n e d . A n o t h e r

r e l a t e d c o n s e q u e n c e i s c o n n e c t i o n s w h i c h a r e c o n t a i n e d

w i t h i n t h e ce l l ar e a . P o w e r b u s s e s a n d v i a c o n s t r a i n t s

c r e a t e s i t u a ti o n s w h e r e a p i n m a y b e a c c e s s e d o n l y o n

o n e la y er . B o o k i n t e r c o n n e c t i o n m e t a l i n t he ro u t e

c h a n n e l c a n c r e a t e n o t o n l y a l o c a l w i r i n g d e n s i t y

p r o b l e m b u t s e v e r e p i n a c c e s s p r o b l e m s .

A t p r e s e n t s p e c i f i c t e c h n i q u e s t o h a n d l e a l l t h e

p r o b l e m s p r e s e n t e d b y t h e s e c o n s t r a i n t s i n a n o p t i m a l

f a s h i o n h a v e n o t b e e n i m p l e m e n t e d . I n s t e a d e mp h a s i s

h a s b e e n o n t h e a b i l i t y t o s o l v e m o s t o f t h e p r o b l e m s

w i t h o u t b e c o m i n g t e c h n o l o g y or p r o j e c t s p e c i fi c . T h e

s y s t e m o p p o r t u n i t i e s f o r m a n u a l i n t e r v e n t i o n a r e u s e d

t o c i r c u m v e n t s h o r t c o m i n g s .

P a p e r 4 4 . 37 9 4

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F i g u r e 6

S Y S T E M F L O W

F i g u r e 6 d e p i c t s t h e g e n e r a l f l o w o f i n f o r m a t i o n i n t o

a n d o u t o f t h e C G A L s y s t e m . P r i m a r y i n p u t d a t a

s o u r c e s a r e t h e L I B R A R Y F I L E a n d t h e D E S I G N F I L E .

T h e L I B R A R Y F I L E c o n t a i n s d e s c r i p t i o n s o f t h e c e l l s ,

t h e b o o k s , T h e r o u t i n g g r i d , t h e I / O b o n d i n g p a d s , t h e

p l a c e m e n t r e s t r i c t i o n s , b o o k t o c e l l m a pp i n g , r o u t i n g

r e s t r i c t i on s , e l e c t r i c a l r u l e s , a n d b o o k p e r f o r m a n c e

d a t a . T h e D E S I G N F I L E d e s c r i b e s t h e l o g i c d e s i g n i n

t h e f o rm o f c i r c u i t s , n e t s a n d m a c r o s . I t a l l o w s n e t s

t o b e t y p e d a n d w e i g h t e d , c o r r e l a t i n g t h e m t o s p e c i f i c

s e t s o f e l e c t r i c a l r u l e s i n t h e L I B R A R Y F I L E . T h e

D E E I G N F I L E i s n o r m a l l y d e r i v e d t h r o u g h a c o n v e r s i o n

p r o g r a m f r o m t h e U C A D L O G I C E Q U A T I O N F I L E w h i c h l i n ks

C G A L t o t h e f u ll c o m p l e m e n t o f S p e r r y U n i v a c C A D t o o l s .

B e c a u s e o f t h e r e l a t i v e l y s t a t i c c o n d i t i o n o f t h e

L I B R A R Y F I L E , i t i s a d v a n t a g e o u s t o p r o v i d e a s t a n d

a l o n e c o m p i l e r f o r t h i s s e c t i o n o f t h e i n p u t d a t a

b a s e . T h e c o m p i l e r c r e a t e s a c o m p a c t q u i c k l y r e a d

f i l e w h e r e t h e m a j o r i t y o f t h e s y n t a x c h e c k i n g ,

l i n k i n g a n d s o r t i n g p r o c e s s e s h a v e a l r e a d y b e e n a c c o m -

p l i s h e d .

T w o o t h e r i n p u t s o u r c e s a r e t h e u s e r r e q u e s t s a n d t h e

R o u t e S e g m e n t F i l e . T h e u s e r r e q u e s t s a C G A L f u n c t i o n

o r f u n c t i o n s t o b e p e r f o r m e d t h r o u g h a c o m m a n d a n d

p a r a m e t e r l a n g u a ge . T h e R o u te S e g m e n t F i l e p r o vi d e s

a n i n t e r m e d i a t e d a t a s t o r e f o r r o u t i n g r e s u l t s w h i c h

c a n b e e d i t e d b y t h e u se r . B o t h t h e R o u t e S e g m e n t

F i l e a n d t h e D E S I G N F I L E a r e u s e d t o r e t a i n i n t e r -

m e d i a t e l a y o u t a n d r o u t i n g r e s u l t s w h i c h c a n b e e a s i l y

e d i t e d t h r o u g h a t e x t e d i t o r .

T h e u s e r c a n c y c l e t h r o u g h t h e C G A L s y s t e m u s i n gg r a p h i c a l o u t p u t a n d p r i n t e d r e p o r t s t o v e r i f y i n p u t ,

a n a l y z e r e s u l t s , a n d d e t e r m i n e ma n u a l i n t e r v e n t i o n

s t r a t e g i e s. M u l t i p l e v e r si o n s o f i n t e r m e d i a t e p l a c e -

m e n t a n d r o u t i n g r e s u l t s c a n b e s a v e d a n d m a n u a l l y

m o d i f i e d . W h e n a 1 0 0% r o u t e d c h i p h a s b e e n o b t a i n e d

w i t h n o e l e c t r i c a l r u l e s v i o l a t i o n s t h e u s e r r e q u e s t s

t h a t C G A L w r i t e a C a l m a c o m p a t i b l e o u t p u t f i l e .

O n c e i n t h e C A L M A s y st e m , g r a p h i c a l e d i t i n g c a n b e

e x e r c i s e d a n d a p a t t e r n m a s k t y p e c a n b e w r i t t e n .

H o w e v e r , p r i o r t o t h e c r e a t i o n o f a p a t t e r n t a p e a

c h e c k i n g p r o g r a m , L S I C H E C K S , i s r u n . T h i s p r o g r a m

v e r i f i e s t h a t t h e o r i g i n a l d e s i g n i n p u t a s r e p r e s e n t e d

i n t h e l o g i c e q u a t i o n f i l e i s a c c u r a t e l y r e f l e c t e d i n

t h e C A L M A D a t a B a s e . A l s o c h e c k e d a r e d e s i g n r u l e s to

i n s u r e no e r r o r s h a v e b e e n i n t r o d u c e d d u r i n g t h e

l a y o u t / r o u t i n g / e d i t i n g p r o ce s s . A f i n a l o u t p u t of t he

c h e c k i n g p r o g r a m i s u p d a t e s t o t h e l o g i c e q u a t i o n f i l e

c o n t a i n i n g c h i p p i n s a n d n e t m e t a l b y l a y e r. T h i s

d a t a i s u s e d b y P . C . l a y o u t , t i m i n g a n a l y s i s , a n d t e s tl i s t g e n e r a t i o n p r o g r a m s .

O P E R A T I O N A L M O D U L E S

T h e C G A L s y s t e m w a s d e v e l o p e d a s a s e t o f i n d e p e n d e n t

m o d u l e s r u n n i n g o f f a c o m m o n d a t a b a s e u n d e r a n

e n v i r o n m e n t c o n t r o l l e d b y a c o m m o n s u p e r v i s o r . T h e

s i x m o d u l e s a r e d e f i n e d i n t h i s s e c t i o n .

C o n t r o l M o d u l e

T h e c e n t e r o f t h e C G A L s y s t e m i s t h e C o n t r o l ( S u p e r -

v i s o r ) M o d u l e w h o s e r e s p o n s i b i l i t y i s t h e i n i t ia l i -

z a t i o n a n d c o n t r o l o f t h e s y s t e m e n v i r o n m e n t . A l l

s y s t e m r e q u e s t s a r e p r o c e s s e d b y t h e c o n t r o l m o d u l e

v i a s p e c i f i c c o m m a n d s c o n t a i n e d w i t h i n a c o m m a n d

s t a c k . T h e c o n t r o l l e r a c c o m p l i s h e s t h e s e ta s k s b y a

s e t o f i n d e p e n d e n t s e r v i c e r o u t i n e s c o n t a i n e d w i t h i nt h e s y s t e m . T h e s e a r e :

• A n a l y s i s o f s y n t a x a n d s e m a n t i c s o f c o m m a n d /

p a r a m e t e r r e q u e s t s

• A s s i g n m e n t a n d m a i n t e n a n c e o f u s e r f i l e s

• D y n a m i c a s s i g n m e n t a n d c o n t r o l o f v a r i o u s s u b m o d u l e

files

• R e a d / W r i t e o f u s e r a n d p r o g r a m a s s i g n e d f i l es

• B u i l d i n g , p r o c e s s i n g a n d c o n t r o l o f t h e c o m m a n d

s t a c k

• M e s s a g e h a n d l i n g a n d p r o c e s s i n g

• E r r o r r e c o v e r y p r o c e d u r e s

T h e c o m m a n d , p a r a m e t e r a n d m e s s a g e p r o c e s s i n g a r e

t h e m o s t i n t e r e s t i n g o f t h e s e f e a t u r e s .

C G A L c o n t a i n s a g l o b a l c o m m a n d s t a c k t h a t i s u s e d a s

b o t h a q u e u e a n d as a s t a c k . I n i t i a l e n t r y c o m m a n d s

( v i a u s e r p a r a m e t e r s ) a r e e n t e r e d i n t o t h e s y s t e m a sa q u e u e ( f i r s t i n - f i r s t o u t ) w h i l e s y s t e m m o d u l e s

m a y r e q u e s t c o m m a n d e n t r i e s ( d u r i n g p r o c e s s i n g )

w h i c h a r e h a n d l e d a s a s t a c k ( l a s t i n - f i r s t o u t ) .

T h i s f l e x i b i l i t y o f t h e c o m m a n d s t a c k a l l o w s o t h e r

m o d u l e s t o a dd c o m m a n d s o n t o t h e s t a c k c a u s i n g a l t e r -

n a t e e v e n t s t o b e s c h e d u l e d a s a f u n c t i o n o f t h e

a c t i o n t a k e n b y t h e o r i g i n a l m o d u l e . T h e c o m m a n d s

w i t h i n t h e c o m m a n d s t a c k i n i t i a t e a l l m o d u l e s w i t h -

i n t h e s y s t e m ( i . e . , D a t a B a s e B u i l d , P l a c e m e n t ,

R e p o r t s ) v i a a n u m e r i c s e q u e n c e t h a t d e f i n e s t h e

s p e c i f i c m o d u l e t o b e c a l l e d . T h e co um l an d l a n g u a g e

p e r m i t s m a c r o l e v e l c o m m a n d s w h i c h a u t o m a t i c a l l y l o ad

a s e r i e s o f m i c r o m o d u l e c o m m a n d s a s c h a i n e d e v e n t s .

M e s s a g e s i n C G A L a r e c o n t r o l l e d s u c h t h a t a t t h e e n d

o f e a c h f u n c t i o n a l m o d u l e t h e m e s s a g e p r o c e s s o r w i l l

p r o c e s s a l l m e s s a g e s q u e u e d f o r o u t p u t . T h e r e s u l t s

o f t h i s a p p r o a c h a r e t h a t a l l m e s s a g e s a p p e a rt o g e t h e r f o r e a c h m o d u l e ( r a t h e r t h a n b e i n g s c a t t e r e d

t h r o u g h o u t t h e l i s t i n g ) a n d t h a t m e s s a g e f o r m a t s a r e

c o n t r o l l e d b y o n e r o u t i n e t h r o u g h o u t t h e p r o d u c t i o n

s y s t e m .

D a t a B a s e M o d u l e

T h e d a t a b a s e m o d u l e c o n s i s t s o f a s e t o f r o u t i n e s

w h i c h b u i l d t h e d a t a b a s e , h a n d l e a c c e s s i n t e r f a c e s

Paper 4 4 . 3

795

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and maint ain che cking services, as well as provid ing

an off line compiler. The data base refers to a

c o l l e c t i o n o f a l l p r oj e c t i n f o r m a t i o n p e r t a i n i n g t o

the definition of the project hardwar e design. Thus

while each design has its own independe nt data base,

portions of it are shared with o ther designs.

Throughout the CGAL system the common data base is

maintai ned via mass storage devices. The co~muon data

base str ucture has been an essential link to provi-

ding a flexible envir onment for the develo pment of

b o t h a l g o r i t h m i c a n d u s e r i n t e r f a c e m o d u l e s w i t h i n

the CGAL system.

The data base it self consists of tables (define d

global to the system) which are maint ained and

controll ed via load and store service routines.

These routines will upon re quest from a specific

module, load and/or restore selecte d tables in a

designated area.

The data base allows the user to retain numerous

Desig n and Route Segment files withi n the system as

separate elements of the same logic name but diff erent

version names. This allows the user to attempt several

experim ental layouts then select the prefer red layout.

Because the Design and Route Segment files ex ist with -

in the UNIVAC ~ II00 as symbolic elements they can

be easily modified using the standard Ii00 Syst em Edit

processors. The user has the flexibility to shape the

o u t p u t o f h is d e s i g n b y w e i g h t i n g n e t s , m a n u a l l y

p l a c i n g c i r c u i t s, p r e - a s s i g n i n g p i n s , a p p l y i n g d i f f e r -

ent wiri ng rules to nets, pre-gr oupin g circuits for

cluste ring and adding discretes. Similarl y the Route

S e g m e n t F i l e t a n b e m o d i f i e d t o c o m p l e t e o r c h a n g e a

c o n n e c t i o n p at h . T h e CG A L s y s t e m c r e at e s u p d a t e d

versions of these files upon user request.

The source languag es used in CGAL for the Design,

Route Segment and Library files use a common format.

Each file consists of sections which consist of a set

o f st a t e m e n t s . T h e s e s t a t e m e n t s d e s c r i b e t h e d a t a b y

means of fields, sub-fie lds and segments of sub-fields.

The language allows for repeatabl e, as well as multi-

ple expressions of the state ment elements. The co,~mon

language has proven to be very effec tive for user

training.

Placement Module

As in (PAT71) the placeme nt module consist s of four

major activities: (i) Partit ionin g (2) Cluste r

Placemen t (3) Decompo sition (4) Placement Imp rove-

ment.

To satisfy the twin criteria of wirea bili ty and net

length, each of these activities is divided into two

phases. In the first phase, an initial constructi ve

s o l u t i o n i s o b t a i n e d b a s e d o n t h e o b j e c t i v e o f m i n i m u m

length. In the second phase an iterative loop is

entered durin g which an effort is made to achieve a

m o r e u n i f o r m w i r i n g d i s t r i b u t i o n . D u r i n g p ar t i -

tioning, an initial constr uctive solut ion is obtai ned

using the cluster develo pment method (HAN72). The

technique is augmented by the use of macros as pre-

partitio ned cluster seeds. This portion of parti-

tioning is skipped when the input data contains

c o m p l e t e p a r t i t i o n s p r o v i d e d b y t h e l o g ic d e s i g n e r .In the iterative loop, wire abil ity is attacked ind i-

r e c t l y b y a t t e m p t i n g t o a c h i e v e b a l a n c e d c l u s t e r

sizes; removing circuits f rom oversized clusters a nd

r e a s s i g n i n g t h e m w i t h a l i n e a r a s s i g n m e n t t e c h n i q u e

until all the clusters are roughly equal in size.

Circuits which are members of constraine d macros are

not candidates for reassignm ent. Separate linear

assignments of internal gates to clusters and to I/O

b u f f e r s i n s ur e s a u n i f o r m d i s t r i b u t i o n o f i n t e r n a l

gates as well as external signals. The linear

reassignm ent of I/O buffers was found to be parti-

cularly useful for logic designs u sing a low percent age

of the I/O pads provi ded on the gate array.

Cluster placement begins by initially locat ing the

clusters on the gate array by a process similar to

the pair linking approach (HAN72). Analysis of

w i r i n g d e n s i t y a t e ve n l y s p a c e d v e r t i c a l a n d h o r i -

zontal cut lines is done and using an itera tive

procedur e (BREU77) an attempt is made to reduce the

congestion at the most dens e areas.

D e c o m p o s i t i o n f i r s t p e r f o r m s a n i n i t i a l m a p p i n g o f

books to cells. Then the min-cut procedu re is used

on the clusters to distribut e the wiri ng within

cluster boundaries.

T h e p l a c e m e n t i m p r o v e m e n t p h a s e i s b a s e d o n a F o r c e

Direct ed Interchange procedure. Each swap is eval-

uated on the basis of a composite function which

considers the effect on wiri ng length, the electri-

cal rules, and critical net identifications. To

reduce run time, this procedure uses several net ting

m e t h o d s w i t h m o r e p r e c i s e s c h e m e s b e i n g u s e d i n t h e

later passes. Periodic reassignm ent of I/O signals

to pads is done to reflect the changes in the place-

ment of the I/O buffers. The process terminates with

a pass in which all the pins on the internal gates

are reassigned to reduce wire crosso vers in routing.User parameters to bias nets on the basis of numb er

of iterations and the size of target neighborho ods

are available to handle d ifferent des igns and tech-

nologies.

R o u t i n ~ M o d u l e

T h e R o u t e r c o n s i st s o f s u b m o d u le s w h i c h p e r f o r m

global routing, vertical track assignment, horizo ntal

track routing, clean up and maze routing. A router

e n v i r o n m e n t p r o v i d e s a da t a b a s e f o r a l l i n f o r m a t i o n

used by the various routing tasks. This router

e n v i r o n m e n t , c o n s i s t i n g o f n e t t i n g d e s c r i p t i o n s

required for each task and physical bloc kage lists

accessible by rectangu lar area provides a common set

o f r o u t i n e s f o r d e t e r m i n i n g w h e r e r o u t i n g i s p e r m i t t e d

and recording routes once made.

Global Routin~. Global routing is initiated by

dividing the chip into a matrix of global cells which

correspo nd to the grid formed by the rows and columms.

The cell area defines the location of a set of global

points while the cell edges repres ent a set of routing

paths. There fore each cell edge is assigned a value

repres enting the routing supply. This model closely

resembles the model described in (CHEN77). The edge

supply can be discounted by user paramet er to allow

for more accurat e modelling of cell routi ng density.

The supply across horizontal edges is generally set to

100% of the actual supply, howeve r it is set at B0%-

90% of the actual supply across vertical edges. This

is to compensa te for intra cell connections and

h o r i z o n t a l j o g s i n t r o d u c e d i n v e r t ic a l t r a c k a s s i g n -

ment. The global routing will determine the inter-

connectio n path for all global cell to cell routes,

ignoring all internal cell connections. Each signal

set is netted in the form of a Steiner tree (HAN66),ignoring cell e~ge supplies. The cell edge crossings

are now examin ed for overflows where demand exceeds

supply. For each edge contain ing an overflow~ the

transfer of net segments to other edges will occur.

This is done one net at a time, by sc oring and order-

ing the nets ac cording to the number of overflows per

net, length and a measure of net criticalness. The

net is reconst ructed to reduce overflows by moving net

segments. This process continues until no overflows

Pa p e r 4 4 . 37 9 6

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exist or no improvement s can be made. The new global

p o i n t s c r e a t e d d u r i n g n e t t i n g a r e t r a n s l a t e d i n t o

channel points with channel locations, and the net

segments are assigne d to channels a ccordi ng to the

global routing. This creates a set of channels with a

s e t o f p o i n t s t o c o n ne c t p e r m i t t i n g s u b s e q u e n t r o u t i n g

to be done a channel at a time.

R e s u l t s a f t e r g l o b a l r o u t i n g c a n b e u s e d t o e v a l u a t e

a n d p r e d i c t t h e r o u t a b i l i t y o f t h e d e s i g n w i t h o u t

f u r t h e r p r o c e s s i n g . I n c a s e s w h e r e m u l t i p l e p l a c e -

ments have been cr eated the global router is an

e f f e c t i v e t o o l f o r s e l e c t i n g w h i c h o n e s h o u l d b e

routed to completion.

V e r t i c a l T r a c k A s s i g n m e n t . T h i s p h a s e o f r o u t i n g

defines the X coordin ate entry points into the hori-

z o n t a l c h a n n e l s f o r w i r e s e g m e n t s w i t h i n a v e r t i c a l

channel. This includes both pin nodes and vertica l

s e g m e n t s p a s s i n g t h r o ug h a h o r i z o n t a l c h a n n e l . T h e

basic app roach follows the process used in (CHEN77).

A c o s t m a t r i x i s c r e a t e d w i t h e a c h v e r t i c a l s e g m e n t

and node ass igned a cost for assign ment to each

vertica l track in the channel. Munkres (HAN72) linear

assign ment metho d is then applied.

Costs are based on assurin g pin access to the hori-

z o n t a l c h an n e l , m i n i m i z i n g t h e i n t r o d u c t i o n o f n e w

h o r i z o n t a l s e g m e n t s a n d t h e l e n g t h o f e x i s t i n g o n e s .

S p e c i a l p r o b l e m s w e r e e n c o u n t e r e d i n d e a l i n g w i t h

s t a c k e d p i n s i t u a t i o n s w h e r e t w o o r m o r e p i n s s h a r e

a n X c oo r d i n a t e . T h e u s e o f a l t e r n a t e p i n s i s m o d e l e d

into the cost function, howe ver, in some cell pinc o n f i g u r a t i o n s i t is n e c e s s a r y t h a t t w o s i g n a l s b e

a s s i g n e d t h e s a m e X c o o r d i n a t e w i t h a c c e s s o n d i f f e r -

e n t la y e r s. I n a d d i t i o n t h e r e a r e o c c a s i o n s w h e r e

v e r t i c a l c o n n e c t i o n s c a n b e m a d e t o t a l l y w i t h i n t h e

cell area. The acces sabil ity of a pin is consi dered

in the cost fu nction to permit pins on the cell edge

t o b e l e f t f o r a s s i g n m e n t b y a n o v e r f l o w p r o c e s s o r

i n s t a c k e d p in co n f l i c t s . A s s i g n m e n t p r o c e e d s o n a

r o w b y r o w b a si s t h r o u g h a v e r t i c a l c h a n n e l b e g i n n i n g

a t e i t h e r t h e b o t t o m o r t o p o f t h e c h a n n e l .

H o r i z o n t a l T r a c k R o u t e r . T h e h o r i z o n t a l t r a c k r o u t e r

d e t e r m i n e s t h e d e t a i l e d a s s i g n m e n t o f n e t s t o t r a c ks

i n t h e h o r i z o n t a l a n d e x t e r n a l v e r t i c a l c h a n n e l s .

T h e l i n e - p a c k i n g s c h e m e u s e d i s t h e D o g l e g R o u t i n g

t e c h n i q u e ( D E U 7 6 ) . A n e f f o r t i s m a d e t o r e d u c e

c o n s t r a i n ts s o t h a t t h e r o u t i n g c a n b e c o m p l e t e d n e a r

c h a n n e l d e n s i t y . A s h o r t v e r t i c a l s e g m e n t i s i n t r o -

d u c e d a t n o n - c r i t i c a l d e n s i t y p o s i t i o n s t o b r e a k

c y c l i c a n d c h a i n c o n s t r a i n t s . S e g m e n t s r e q u i r i n g

first l ayer access are given priorit y for "the tracks

n e a r e s t t h e c h a n n e l e d g e s.

Maze Router. The maze router is used to comple te

wires left follow ing the track routers. The primar y

set of wires left are those on the chip peri phery in

a r e a s w h e r e o n l y o n e l a y e r o f m e t a l i s a v a i l a b l e f o r

r o u t i n g . H o w e v e r , w i r e s a r e a ls o ro u t e d b y t h e m a z e

r o u t e r i n a r e a s o f p o o r p i n a c c e s s a n d u n r e s o l v e d

c o n s t r a i n t s i n t h e i n t e r n a l a r r a y . T h e m a z e r o u t i n g

t e c h n i q u e i s an i m p l e m e n t a t i o n o f a d i r e c t e d w a v e

f r o n t r o u t e r ( S O U 7 8 ) w i t h m u l t i p l e s t a r t a n d d e s t i n -

a t i o n s a l l o w e d . T w o p a s s e s a r e m a d e w i t h a l a r g e r

r o u t i n g w i n d o w a n d r e l a x e d o r t h o g o n a l i t y c o n s t r a i n t s

on the seco nd pass.

C l e a n u p Ro u t i n ~ . T h e c l e a n u p r o u t i n e r e m o v e s u n n e c-e s s a r y v i a s b y m o v i n g a p o r t i o n o f a r o u t e t o a n o t h e r

layer. This is done following track routing.

F o l l o w i n g m a z e r o u t i n g t h e c l e a n u p r o u t i n e i s a g a i n

i n v o k e d t o r e m o v e e x t r a v i a s a n d m et a l m a d e u n n e c -

essary by the maze router.

R e p o r t M o d u l e

I n a d d i t i o n t o t h e o u t p u t g e n e r a t e d b y t h e v a r i o u s

m o d u l e s o f C G A L , t h e u s e r i s p r o v i d e d w i t h h a r d c o p y

reports of the layout results at various stages of

t h e d e s i g n i m p l e m e n t a t i o n . T w o t y p e s o f p r i n t e r

r e p o r t s a r e g e n e r at e d ; s u m m a r y r e p o r t s w h i c h c o n v e y

c h i p p r o f i l e i n f o r m a t i o n a n d v i o l a t i o n r e p o r t s w h i c h

i d e n t i f y d e s i g n r u l e v i o l a t i o n s a n d pr o v i d e d a t a f o r

d e a l i n g w i t h t h e m.

The repor t modul e runs off the consnon data base an d

h a s t h e f o l l ~ i n g a t t r ib u t e s.

I ) c a n b e i n d i v i d u a l l y r e q u e s t e d b y u s e r .

2 ) c a n b e e a s i l y m o d i f i e d o r a d d e d t o a c c o r d i n g t o

the users needs.

3 ) p r o v i d e s t h e p e r t i n e n t i n f o r m a t i o n i n a s e l f -

s u f f i c i e n t f o r m e l i m i n a t i n g t h e n e e d t o r e f e r t o

o t h e r d o c u m e n t s .

W h e n d e a l i n g w i t h m u l t i p l e p r o j e c t s a n d t e c h n o l og i e s

t h e s u p p o r t p r o b l e m s c a n b e q u i t e e x t e n s i v e e s p e c i a l l y

in the area of project sp ecific rules and constrain ts.

O u r a b i l i t y t o g e n e r a te e f f e c t i v e r e p o r t s o n s h o r t

n o t i c e h a s e n a b l e d t h e u s e r t o m a i n t a i n p r o d u c t i o n

s c h e d u l e s t h r o u g h t h e m a n u a l i n t e r v e n t i o n o p p o r t u -

nities in the CGAL system. It has also kept ill

a d v i s e d p r o je c t s p e c i f i c a l g o r i t h m i c m o d i f i c a t i o n s

to a minimu m.

Summary repo rts incl ude rou ting sunn~ary~ cell utili -

zation, pin usage, net length analysis, p lacem ent

maps, and circuit types used. Examples of error

r e p o r t s i n c l u d e a n a n a l y s i s o f v o l t a g e d r o p i n v o l v i n g

d e t e r m i n a t i o n o f c u r r e n t f l o w i n a l l n e t b r a n c h e s .

A l s o a v a i l a b l e a r e r e p o r ts o n n e t d e l a y v i o l a t i o n s

and for the ~ technology , latch macro delay viola-

t i o n s. V a l u e s w h i c h d e f i n e a v i o l a t i o n a r e c o n t a i n e d

in the CGAL l ibrary file as part of the design rules

o r e l e c t r i c a l c h a r a c t e r i s t i c s o f t h e b o o k .

C G A L a l s o p r o v i d e s o u t p u t r e p o r t s i n t h e f o r m o f

p r e c i s i o n c o l o r g r a p h i c s p l o t s. A X y n e t i e s L a r g e

A r e a F l a t b e d p l o t t e r i s u s e d t o v e r i f y t h e C G A L

l i b r a r y i n pu t d a t a . F o r m a n u a l r o u t e c o m p l e t i o n , a

r o u t e m a s t e r i s g e n e r a t e d a l o n g w i t h a pl o t o f a l l

routing and connecti ons still to be made. This can

be marked up, then used to enter the data in to theRoute Segment file.

A final output rep orting form is to a color graphics

terminal. A Chromat ics termina l is prese ntly being

u s e d a n d t h e o u t p u t a v a i l a b l e i s e s s e n t i a l l y t h e s am e

as is available on the Xynetics . An inter activ e

r e l a t i o n s h i p i s p l a n n e d f o r f u tu r e e x t e n s i o n s .

O u t p u t M o d u l e

T h i s m o d u l e i s r e s p o n s i b l e f o r t r a n s f e r r i n g t h e

r e s u l t s o f l a y o u t a n d r o u t i n g t o t h e C a l m a s y s t e m f o r

m e r g e s w i t h c o m m o n d a t a a n d p a t t e r n m a s k g e n e r a t i o n .

T h e C a l m a G r a p h i c S y s t e m c o n t a i n s t h e b u l k o f t h e

i n f o r m a t i o n r e q u i r e d t o d e s c r i b e t h e m a s k g e n e r a t i o n

d a t a f o r a s p e c i f i c c h i p . T h e g r a p h i c a l d a t a b a s e

o u t p u t ( C G A L ' s c o n t r i b u t i o n t o t h e p a t t e r n g e n e r a t i o n )

is a descr iption of the layout and routi ng result s in

a f o r ma t ( G D S I I S t r e a m f o r m a t ) w h i c h c a n b e r e a d b yt h e C A L M A G r a p h i c s S y s t e m .

C G A L S y s t e m o u t p u t t o C A L M A c o n s i s t s o f f o u r m a j o r

s e c t i o n s . T h e f i r s t s e c t i o n e s t a b l i s h e s t h e C A L M A

e n v i r o n m e n t ( p r o v i d i n g a C A L M A l i b r a r y n a m e , C A L M A

r e f e r e n c e l i b r a r y n a m e s , C A L M A " F O N T " r e f e r e n c e

Pa p e r 4 4 . 37 9 7

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l i b r a r y n a m e s , a n d t h e C A L M A u n i t s d e s c r i p t i o n s ) .

T h e s e c o n d s e c t i o n e s t a b l i s h e s t h e s e l e c t i o n , p l a c e -

m e n t , a n d o r i e n t a t i o n o f a l l t h e C A L M A c e l l r e f e r e n c e

n a m e s ( t h e c e l l s h a v e p r e v i o u s l y b e e n e s t a b l i s h e d

w i t h i n t h e C A L M A d a t a b a s e a n d c o n t a i n a l l p e r t i n e n t

informa tion regard ing the cell such as metal

descript ors, layers, pin numbers, etc.). The third

s e c t i o n c o n t a i n s t h e p l a c e m e n t a n d d a t a f o r t e x t u a l

i n f o r m a t i o n ( e a c h u n i q u e c i r c ui t n a m e d e s c r i b e d

w i t h i n t h e p a r t i c u l a r d e s i g n / la y o u t ) . T h e f o u r t h

s e c t i o n c o n t a i n s t h e a c t u a l r o u t i n g d e s c r i p t o r s a n d

" V I A ' s " a s e s t a b l i s h e d w i t h i n t h e R o u t e d S e g m e n t f i l e( c o n t a i n s l a y e r , d a t a t y p e , p a t h t y p e , m e t a l w i d t h , a n d

c o o r d i n a t e s f o r e a c h s e g m e n t a s w e l l a s " v i a " C A L M A

l i b r a r y r e f e r e n c e s a n d l o c a t i on s ) .

D I S C U S S I O N

T h e C G A L s y s t e m i s p r e s e n t l y i n p r o d u c t i o n u s e . A

s t a f f o f d e s i g n a u t o m a t i o n t e c h n i c i a n s r u n t h e p ro -

g r a m s a n d i n t e r a c t w i t h t h e l o g i c d e si g n e r s i n a

p r o d u c t i o n e n v i r o n m e n t . A t w o w e e k t u r n a r o u n d i s t h e

p r e s e n t a v e r a g e t i m e f r o m l o gi c d e s i g n i n p u t t o

p a t t e r n t a p e . A n i n it i a l c a p a b i l i t y o f t h r e e c h ip s

p e r w e e k w a s e x p e r i e n c e d , s u b s e q u e n t l y i t i m p r o v e d

t o b e t t e r t h a n o n e p e r d a y a s p r o j e ct i n t e r f a c e s a n d

s y s t e m f a m i l i a r i t y i m p ro v e d . T r a i n i n g o n t h e s y s t e m

p r o g r e s s e d s m o o t h l y a n d o n c e a t e c h n o l o g y i s e st a b -

l i s h e d, n e w u s e r s o f t h e s y s t em , w h e t h e r t e c h n i c i a n s

o r l o g i c d e s i g n er s , h a v e b e e n a b l e t o o b t a i n g o o dlayouts in just a few weeks. The manua l effort

i n v o l v es d e a l i n g w i t h u n r o u t e d c o n n e c t i o n s , t i m i n g

c o n s t r a i n t s a n d p h y s i c a l co n s t r a i n t s . D e p e n d i n g o n

t h e s e v e r i t y o f t h e p r o b l e m t h e u s e r r e a c t i o n c a n

r a n g e f r o m w e i g h t i n g e r r o r ne t s a n d r e r u n n i n g a l l or

p o r t i o n s o f p l a c e m e n t t o m a n u a l l y i n s e r t i n g e x t r a

m e t a l o n a n e t t o b a l a n c e c l o c k s k e w o r l o w e r I R d r op .

T E C H N O L O G Y T T L #I T T L #2 C M O S E C L

T O T A L N E T S 7 6 1 5 8 8 4 8 0 4 8 3

I N T E R N A L C E L L S 8 1 6 6 0 0 1 2 9 6 3 6 0

USED CELLS 800 534 1239 347

I/O PADS i16 112 80 116

I/O PADS USED 112 106 80 i01

T O T A L S E G M E N T S 1 8 7 2 1 3 7 9 1 1 1 9 1 3 5 3

R O U T E D S E G M E N T S 1 8 6 4 1 3 6 8 1 0 9 8 1 3 4 7

P E R C E N T R O U T E D 9 9 . 5 7 9 9 . 2 9 8 . 1 2 9 9 . 5 5

Tab le II

Results o n four chips, each a differ ent type, are

d i s p l a y e d i n T A B L E II . T h e s e r e p r e s e n t f a i r l y d e n s e

c h i p s r a n g i n g f r o m 8 9 % t o 9 8 % c e l l o c c u p a n c y .

S e g m e n t s a r e u s e d t o m e a s u r e r o u t e c o m p l e t i o n c o n n e c -

tion and are defined

n

S = Z (Pi-l)

i=l

where S is the numbe r of segments, n is the numbe r of

nets and P. is the number of pins in net i.l

S e v e r a l p o i n t s s h o u l d b e n o t e d a b o u t t h e r e s u l t s .

a . I / O b u f f e r p i n a c c e s s a n d p l a n a r r o u t i n g f a i l u r es

o n t h e t w o T T L a n d t h e E C L c h i p s a c c o u n t f o r 5 0

to 100% of the unroutes.

b . O n l y o n e d e s i g n i s u s i n g t h e C M O S t e c h n o l o g y a t

this time. The logic desi gn was unusual in that

o v e r 7 5 % o f t h e c h i p a r e a w a s o c c u p i e d b y j - k

flip flop books similar to that in Figure 5.

T h e s e l a r g e b o o k s c o m b i n e d a l o w p i n / c e l l d e n s i t y

w i t h a l a r g e n u m b e r o f p r e - r o u t e d i n - c h a n n e l

c o n n e c t i o n s o f b o o k m e t a l. T h e s e f a c t or s d i s -

c o u r a g e s p e c u l a t i o n a b o u t t h e C M O S p e r f o r m a n c e

u n t i l m o r e p a r t s a r e r u n .

c . M a n u e l r o u t e c o m p l e t i o n i s t y p i c a l l y d o n e t h r ou g h

t h e C G A L s y s t e m f i l e s a n d r e q u i r e s ½ d a y t o

m a n u a l l y r o u t e a n d ½ d a y t o e n t e r a n d c h e c k t h e

r e s u l t s w i t h t h e p r o g r am .

d . T h e T T L #2 p a r t d i f f e r s f r o m t h e T T L #I p ar t i n

that the upper ~ of the chip area is devoted to

a s p e c i a l b u s i n t e r f a c e c i r c u i t . T h i s i s m o d e l l e das a set of prepl aced 'super' hooks in the CGAL

f i l e s a n d n o s p e c i a l s o f t w a r e i s r e q u i r e d t o

h a n d l e i t .

Figures 7 & 8 depict routed TTL and ECL arrays.

CGAL has several areas where performance improve-

ments have been identified. From the user view-

point, an expansion of the Chromatie~ interface to

i n c l u d e i n t e r a c t i ve p r o c e s s i n g w o u l d m a k e t h e

s y s t e m m o r e i n d e p e n de n t o f t h e C A L M A w i t h o u t a l o s s

in graphical capability. The algori thm being used

in the placement of the I/0 buffers is bein g

reevaluated in light of the TTL routing results.

The more severe stacked pin situations on the ECL

chip still result in some internal array routin g

failures. The maze router has proven to be a good

final routing tool for both internal array failures

and peripher y problems, bu t a better ord ering is

needed in conjunction with an I/0 PAD swapping to

produce optimal results.

A l t h o u g h 1 0 0 % r o u t i n g h a s n o t b e e n r e g u l a r l y a c h i e v e d ,

t h e a p p l i c a t i o n o f a c o l l e c t i o n o f f a i r l y s t a n d a r d

t e c h n i q u e s i n C G A L t o d i f f e r e n t g a t e ar r a y t e c h n o l ~

o g i e s h a s b e e n a s u c c e s s . T h e C G A L s y s t e m t o o l s h a v e

e n a b l e d u s e r s t o h a n d l e p r o b l e m s i n a c o s t e f f e c t i v e ,

s e m i - a u t o m a t e d m o d e . C G A L w a s d e s i g n e d u s i n g a

m o d u l a r , s t r u c t u r e d a p p r o a c h t o s o f t w a r e d e v e l o p m e n t .

T h i s d e s i g n w i t h i t s c o m m o n d a t a b a s e a n d i n d e p e n d e n t

m o d u l e s h a s a l l o w e d m o d i f i c a t i o n s a n d e n h a n c e m e n t s

t o o c c u r i n a s t a b l e e n v i r o n m e n t . T h e p r o b l e m a r ea s

p r e v i o u s l y n o t e d a n d t h o s e w h i c h w i l l a r i s e i n f u t u r e

g a t e a r r a y t e c h n o l o g i e s c a n b e h a n d l e d b y t h is s y s t e m

u s i n g t h e m a n u a l t o o l s t o p e r m i t p r o d u c t i o n t o c o n -

t i n u e ~ i l e a u t o m a t e d t e c h n i q u e s a r e d e v e l o p e d .

C O N C L U S I O N

A s y s t e m f o r g a t e a r r a y l a y o u t h a s b e e n p r e s e n t e d

w h i c h i s i n u s e o n s e v e r a l d i f f e r e n t t e c h n o l o g i e s .

T h e t e c h n o l o gi e s o f f e r d i v e r s e a p p r o a c h e s t o c e l l

t o p o l o g y , c e l l c o m p l e x i t y , p i n a c c e s s a b i l i t y , I / O

b u f f e r p r o c e d u r e s a n d r o u t i n g c o n s t r a i n t s . T h e

s y s t e m l a n g u a g e s - p e ~ n i t d e s c r i p t i o n s o f c o n s t r a i n t s

u n i q u e t o t h e d i f f e r e n t d e s i g n u s e s a n d t e c h n o l o g i e s .

T h e s y s t e m p e r f o r m a n c e i s a d e q u a t e w i t h r o u t i n g

f a i l u r e s o c c u r r i n g p r i m a r i l y i n th e c h ip p e r i p h e r y

a n d t oo l s f o r m a n u a l c o m p l e t i o n s u f f i c i e n t f o r m e e t i n g

p r o d u c t i o n n e e d s .

A C K N O W L E D G E M E N T S

T h e d e s i g n a n d t h e d e v e l o p m e n t o f t he C G A L s y s t e m

o w e s t h a n k s t o m a n y i n d i v i d u a l s a n d o r g a n i z a t i o n s .

T e r r y A r n t z e n , S h u b h a d a N e r u r k a r a n d J o h n D e l l w o a l l

c o n t r i b u t e d t o s o f t w a r e d e v e l o p m e n t a n d i n s t a l l a t i o n .

T h e R e s e a r c h a n d T e c h n i c a l P l a n n i n g , G e n e r a l S y s t e m s

D i v i s i o n C A D a n d D e f e n s e S y s t e m s D i v i s i o n C A D g r o u p s

a l l c o n t r i b u t e d t o t h e u l t i m a t e p r o d u c t . J e a n M o e n

t y p e d a n d a s s e m b l e d t h e p ap e r .

Paper 44.3798

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The authors would like to extend a special acknow-

ledgment of Mike Pluimer and Dr. Ash Patel for their

efforts in the original d esign and subsequent consul-

tation on the detail desig n of the system.

TAN81

K H O 8 1

WAD'A81

YOU81

RAMSO

HIGHSO 2

HIGH801

SOU78

CHEN77

BREU77

PER76

DEU76

HAN72

PAT71

BIBLIOGRAPHY

Chiyoii Tanaka et alii, "An Integrated

Computer Aided Design System for Gate Array

Masterslices: Part 2 The Layout Design Sys-

tem Mars-M3, Proc 18th Design AutomationConf., pp. 812-819 June 1981

K. H. Khoka ni et alii, "Placeme nt o f

variable size Circuits on LSI Masterslices,"

Proc 18th Design Automation Conf., pp. 426-

434, June 1981

Michi M. Wada, "At Dogleg Optimal Channel

Router with Completion Enhancements," Proc

18th Desig n Auto matio n Conf. , pp. 762-768,

June 1981

Ming Young and Larry Cooke, "A Preprocessor

for Channel Routing~" Proc 18th Design

Automation Conf., pp. 756-761, June 1981

F. R. Ramsay, "Automation of Design for

Uncommitted Logic Arrays," Proc 17th DesignAutomation Conf., pp. 100-107, June 1980

D. W. High tower an d R. L. Boyd, "A General -

ized Channel Router," Proc 17th Design Auto-

mation Confer ence, pp. 12-21, June 1980

D. W. Hi~htow er an d F. G. Alexander , "A

Mature IZL/STL Gate Array Layout System,"

Compcon Spring 1980, pp. 149-155, 1980

Jeri Soukup, "Fast Maze Router," Proc 15th

Design Automation Conference, pp. 100-102,

June 1978

K. A. Chen et alii, "chip Layout Problem--A

Wiring Procedure," Proc 14th Design Automa-

tion Conf., pp. 298-302, 1977

M. A. Breuem, " A Class of Min-C ut Pla cement

Algorithms," Proc 14th Design Automation

Conf., pp. 284-290, 1977

G. Persky et alii, "LTX- -A Syste m for the

Directed Automatic Design of LSl Circuits,"

Proc 13th Design Automation Conf., pp. 399-

407, 1976

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13th Desi gn Automation Conf., pp. 425-433,

1976

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Techniques," Chapter 5 in Design Automation

of Digital System~: Theory and Techniques,

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New Jersey, pp. 213-282, 1972

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Electronic Chips," PHD Thesis State Univer-

sity of NY at Buffalo, May 1971

HASH71

HAN66

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Optimizing Channel Assignment within Large

Apertures," Proc Sth Design Automation

Workshop, pp. 155-169, 1971

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Rectilinear Distance," J. Siam Appl Math

Vol 14 No 2, pp. 255-265, 1966

Paper 4 4 . 3

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E C L G A

F i g u r e 7

Paper 44.3800

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T T L G A

F i g u r e 8

P a p e r 4 4 .38 0 1