a mostly-clean dram cache for effective hit speculation and self-balancing dispatch

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MICRO- 45 December 3, 2012 A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self- Balancing Dispatch Jaewoong Sim Gabriel H. Loh Hyesoon Kim Mike O’Connor Mithuna Thottethodi

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A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch. Jaewoong Sim Gabriel H. Loh Hyesoon Kim Mike O’Connor Mithuna Thottethodi. A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch. - PowerPoint PPT Presentation

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Page 1: A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch

MICRO-45 December 3, 2012

A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch

Jaewoong Sim Gabriel H. Loh Hyesoon KimMike O’Connor Mithuna Thottethodi

Page 2: A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch

MICRO-45 December 3, 2012

A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch

| Problems: Inefficiencies on current DRAM cache approach Multi-MB/High-latency cache line tracking structure (MissMap) Under-utilized aggregate system bandwidth

| Solutions: Use speculative techniques Replace MissMap with a low-cost Hit-Miss Predictor (HMP) Dynamically steer hit requests either to DRAM$ or off-chip DRAM (SBD) Maintain a mostly-clean DRAM cache via Dirty Region Tracker (DiRT)

| Results: Make DRAM cache approach more practical 20.3% faster than no DRAM cache (15.4% over the state-of-the-art) Removed 4MB storage requirement (employable in commercial products)

New Approach: Region-Based Prediction!+ TAGE Predictor-like Structure! = Less than 1KB Storage!!

New Approach: Hybrid Region-Based WT/WB policy for DRAM$!Stacked

DRAM$

Off-chipDRAM

Another Hit Request

Req. Buffer

Req. Buffer

Always send hit requests to DRAM$?

Off-chip BW is under-utilized!

3 tag blocks 29 data blocks

Row

Dec

oder

Sense AmplifierDRAM Bank

…2KB DRAM ROW

MissMap

4MB size for 1GB DRAM$!! 20+ cycles access latency!!

Provide the cache line existence info (hit or miss)

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