a modular strategy for control and voltage balancing of

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A Modular Strategy for Control and Voltage Balancingof Cascaded H-Bridge Rectifiers

Hossein Iman-Eini, Jean-Luc Schanen, Shahrokh Farhangi, James Roudet

To cite this version:Hossein Iman-Eini, Jean-Luc Schanen, Shahrokh Farhangi, James Roudet. A Modular Strategy forControl and Voltage Balancing of Cascaded H-Bridge Rectifiers. IEEE Transactions on Power Elec-tronics, Institute of Electrical and Electronics Engineers, 2008, vol. 23 (5), pp. 2428-2442. �hal-00355421�

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2428 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 5, SEPTEMBER 2008

A Modular Strategy for Control and VoltageBalancing of Cascaded H-Bridge Rectifiers

Hossein Iman-Eini, Jean-Luc Schanen, Senior Member, IEEE, Shahrokh Farhangi, Member, IEEE, andJames Roudet

Abstract—In this paper, a new strategy for voltage balancingof distinct dc buses in cascaded H-bridge rectifiers is presented.This method ensures that the dc bus capacitor voltages convergeto the reference value, even when the loads attached to them areextracting different amounts of power. The proposed method canbe used for an arbitrary number of series H-bridges, differentvoltage levels, and different power levels in unidirectional orbidirectional rectifiers. To reduce the current harmonics anddistortion, the input current is programmed to be sinusoidal andin phase with the input voltage; however, it is possible to adjust theinput power factor to control both the active and reactive powers.In the proposed approach, both the low frequency (stepped mod-ulation) and high frequency [pulse-width modulation (PWM)]switching methods are utilized to improve the performance of therectifier. Using theoretical analysis, the acceptable load powerlimits for a rectifier with N-H-bridge cells are derived. The validityof the proposed method is verified by simulation and experimentalresults.

Index Terms—Active rectifier, cascaded H-bridge, multilevelconverter, power-factor correction, voltage balancing.

I. INTRODUCTION

W ITH THE advancement of power electronics and emer-gence of new multilevel converter topologies, it is pos-

sible to work at voltage levels beyond the classic semiconductorlimits. The multilevel converters achieve high-voltage switchingby means of a series of voltage steps, each of which lies withinthe ratings of the individual power devices [1], [2]. The mul-tilevel topologies are divided into three major categories: neu-tral point clamped (NPC), flying capacitor (FC), and cascadedH-bridge (CHB) converters. Among them, the CHB topologyis particularly attractive in high-voltage applications, because itrequires the least number of components to synthesize the samenumber of voltage levels. Additionally, due to its modular struc-ture, the hardware implementation is rather simple and main-tenance operation easier than alternative multilevel converters.

Manuscript received June 30, 2007; revised March 03, 2008. Current versionpublished November 21, 2008. Recommended by Associate Editor F. Wang.

H. Iman-Eini is with the School of Electrical and Computer Engineering, Uni-versity of Tehran, Tehran 14395-515, Iran, and also with the Grenoble ElectricalEngineering Lab (G2ELab), INPG-UJF-CNRS, UMR 5269 ENSIEG, B.P.46F-38402 St Martin d’Heres Cedex, Grenoble, France (e-mail: [email protected]).

J.-L. Schanen and J. Roudet are with Grenoble Electrical EngineeringLab (G2ELab), INPG-UJF-CNRS, UMR 5269 ENSIEG, B.P.46 F-38402 StMartin d’Heres Cedex, Grenoble, France (e-mail: [email protected];[email protected]).

S. Farhangi is with the School of Electrical and Computer Engineering, Uni-versity of Tehran, Tehran 14395-515, Iran (e-mail: [email protected]).

Digital Object Identifier 10.1109/TPEL.2008.2002055

The CHB converters can be used as inverters in ac motor drives,high power conditioning and active power filters [3]–[5]. Theyalso can be utilized as active front-ends or pulse-width modu-lation (PWM) rectifiers. This kind of application has not beenthoroughly investigated yet [6], [7].

The major drawback of the CHB converter, working as avoltage source inverter, is the need for isolated power supplies.However, when it is used as an active rectifier, the topology iseven more attractive because of the available distinct dc linksfeeding separate loads [8]. In the rectification mode, the CHBconverter aims to establish N equal dc voltages across the ca-pacitors. This can become difficult if the loads attached to thecells are not equal, or the series H-bridges have slightly differentcharacteristics. Thus, a variety of methods have been proposedto maintain the voltage balancing across the capacitors [7]–[18].

In [9], a low frequency predictive current control for asingle-phase CHB rectifier has been proposed. It demonstratesgood controller performance in terms of ac current waveformquality, power factor correction and reduced switching fre-quency. But, it does not provide adequate control strategy toavoid voltage imbalances that could appear across the capaci-tors when the H-bridge cells are slightly different. In [10], dcvoltage balancing control method, based on low frequency mod-ulation techniques, has been proposed. The proposed method,however, does not provide full current control and power factorcorrection. A low frequency selective harmonic-eliminationPWM scheme has been presented in [11] to control energyflow through the CHB topology. Control of power flow in thismethod requires decoupled control of the converter cells. Thebalancing scheme involves the use of a proportional-integral(PI) controller at each cell to regulate power flow into cell.

In [12]–[16], dc bus voltage balancing methods have beenproposed for single-phase static compensator (STATCOM)devices that are based on the CHB multilevel topology. Theyachieve voltage balancing while the reactive power is deliveredto the ac power line. But, these methods are not applicable inCHB rectifiers. In [7], [8], and [17], balancing of capacitorvoltages and power factor correction have been realized fora rectifier with two series H-bridges, while the extension oftheses methods to a higher number of series H-bridges is notstraightforward. In [18], an energy-based approach has beenapplied to the control of an N-H-bridge active rectifier. Theproposed approach is based on the full decoupling of theH-bridges via the proper design of a passivity-based controllerfor each cell.

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Authorized licensed use limited to: Jean-Luc Schanen. Downloaded on January 21, 2009 at 11:06 from IEEE Xplore. Restrictions apply.

IMAN-EINI et al.: MODULAR STRATEGY FOR CONTROL AND VOLTAGE BALANCING 2429

Fig. 1. Unidirectional CHB rectifier with N-H-bridge cells.

In this paper, a simple control method is presented to maintainthe voltage balancing across the capacitors in a CHB rectifier.The proposed controller consists of one analog and one digitalcontrol unit. The analog controller programs the input current tobe sinusoidal and in phase with the input voltage. It can also ad-just the input power factor to control both the active and reactivepowers. The digital controller provides the voltage balancingacross the capacitors, even if the loads connected to the cellsare not equal or the cells do not match perfectly. Using analyt-ical approach, the validity regions and the load power limits fora CHB converter with N-H-bridges are derived. The semicon-ductor loss analysis is also presented to estimate the switchingand conduction losses in the proposed approach.

II. SYSTEM CONFIGURATION

A. Configuration of the Rectifier

The CHB rectifier is the best choice for working inhigh-voltage and high-power applications because of itsextreme modularity, simple physical layout, and reducedlosses. Figs. 1 and 2, respectively, show the configurations ofsingle-phase unidirectional and bidirectional CHB rectifiers.The first structure may be used for feeding the variable-speeddrive in applications such as variable speed fans, pumps, andcompressors [19]. The bidirectional structure may be used infront-end applications, traction, high power electric drives, andelectronic transformers addressed in [6], [7], and [20].

This paper focuses only on the single-phase ac/dc rectifiers.The results, however, can be easily extended to three-phasestructures. Furthermore, the unidirectional rectifier can berealized from bidirectional rectifier by turning off the upperswitches of the H-bridge cells. Therefore, only the bidirectional

Fig. 2. Bidirectional CHB rectifier with N-H-bridge cells.

rectifier is analyzed and its results used for the unidirectionalrectifier as well.

The rectifier in Fig. 2 has N-series-connected H-bridge cells.Each H-bridge consists of four power switches (with anti-par-allel diodes) and a dc bus capacitor. Each capacitor feeds its ownload and the loads may be passive or active converter cells. InFig. 2, the ac terminal voltage of the rectifier, , can be writtenas follows:

(1)

(2)

where , , and are the ac terminal voltage, the capacitorvoltage, and the switching function of the th H-bridge (or cell),respectively. Assuming , where isthe reference voltage of dc buses, each cell can generate threevoltage levels: , , and zero on the ac side. So, usingN-H-bridge cells a maximum of different voltage levelsare obtained to synthesize the ac terminal voltage .

In Fig. 2, applying Kirshhoff’s Voltage Law (KVL) at theinput voltage loop yields

(3)

where is the input voltage, the input current, andthe input inductance, the last used to shape the input current.Applying Kirshhoff’s Current Law (KCL) for each cell leads to

(4)

where is the current of th H-bridge and is a function ofthe input current. is the capacitor current and the loadcurrent. Equations (1)–(4) describe a linear time varying (LTV)



Fig. 3. (a) Basic block diagram of the proposed controller. (b) Drive circuit of an arbitrary H-bridge cell.

TABLE ITRUTH TABLE OF GATE SIGNALS IN PWM MODE

system with one input and states ( to and). The controller should determine the switching functions,to , to achieve the control goals.

B. Configuration of Controller

The basic block diagram of the controller is shown inFig. 3(a). This block consists of analog and digital controllers.The analog controller generates the PWM signal, , andthe digital controller determines the appropriate switchingfunctions to . The necessary feedback signals for thecontroller are the dc bus voltages to , the input voltage

, and the input current . The voltage signals are sensedusing the isolation amplifiers and conditioned to proper mag-nitude to feed the controllers. The input current is measuredusing a Hall-effect sensor, conditioned and used as a feedbackin the current control loop. The digital controller also generatesa synchronized square-wave signal [ in Fig. 3(a)] toadjust the input power factor.

Each switching function correspondsto four operating modes: “0,” “ 1,” “ 1,” and PWM. Theswitching functions are determined by the digital controller andapplied to the H-bridge cells. Then, the corresponding operatingmodes are selected by 4:1 multiplexers [see Fig. 3(b)]. Theoperating mode “0” corresponds to the conduction of bottomswitches . In modes “ 1,” and “ 1,” the diagonalswitches and are turned on, respectively.Mode “ 1” is used if the input voltage is positive; otherwise,mode “ 1” is used. In the PWM mode, the gate signals,to , drive the corresponding cell. These signals are obtainedfrom , output of analog controller, according to Table I.

In Table I, is the sign of input voltage ( is 1 if the inputvoltage is positive; otherwise it is 0). From Table I, one can seethat the PWM gate signals are generated by the following logiccircuits:

(5)

(6)

III. PRINCIPLE OF OPERATION

The main challenges associated with the CHB rectifier con-trol are: 1) shaping the input current and controlling the inputpower factor and 2) maintaining voltage balance across the dcbus capacitors. The first goal will be achieved by the analog con-troller and the second one by the digital controller, as explainedin the following paragraphs.

A. Analog Controller

The functional block diagram of the analog controller isshown in Fig. 4. This controller is intended to shape the inputcurrent and regulate the total voltage of dc buses. The con-troller has two control loops: the inner current loop and theouter voltage loop. The voltage loop contains a PI controllerto regulate the total voltage of dc buses to the reference value

. In the classical methods, the output of PI controller ismultiplied by the sample of input voltage to generate a sinu-soidal reference current, . In this paper, the digital controllergenerates a square-wave synchronized signal, , from theinput voltage. The sync signal has the same frequency as theinput voltage and its phase is adjusted by the digital controller.The square-wave signal is filtered by a forth-order Butterworthfilter (Sallen-Key topology) and the output is multiplied by theoutput of PI controller. Using this method, a pure sinusoidalreference is generated even in the polluted environments withnoise and harmonics. Additionally, the input power factor andthe reactive power flow are controlled, and the gain of voltageloop becomes independent from the input voltage variations.

After generating the reference current , the inner currentloop programs the input current to follow the reference wave-form. Some of the reported current mode control techniques arepeak-current mode, average-current mode, and hysteresis-cur-rent mode controls [21]. In this paper, the hysteresis-currentcontrol is utilized, which has the advantages of simple analogimplementation and fast dynamics, but other fast dynamic cur-rent control methods can also be used.



Fig. 4. Details of the analog controller employed in Fig. 3.

Fig. 5. Definition of voltage regions for � � �� .

In hysteresis controller, the lower limit of current andthe upper limit of current are defined as follows:

(7)

where, represents the hysteresis band. According to this con-trol method, becomes 1 when the input current goes belowthe lower limit and it becomes 0 when the input current goesabove the upper limit.

B. Definition of Voltage Regions

To take advantage of both low frequency (stepped modula-tion) and high frequency (PWM) modulation techniques, hybridmodulation method shown in Fig. 5 is employed. In this method,the input voltage is divided into equal sections with the scaleof ( is the dc bus voltage reference and each cell toler-ates no more than ). Now, the voltage region is defined asfollows:

(8)

Region is where the magnitude of input voltage, , liesbetween and . It is worth noting that the min-imum number of cells to synthesize the multilevel waveform,

, is equal to the closest integer greater than , whereis the peak input voltage. In Fig. 5, is the mains half-

cycle, and corresponds to thechange of voltage region, where , and is equalto . The voltage region can be represented by the time

intervals and as well. Assuming, and are derived as follows:

(9)

for (10)

The following benefits can be achieved by utilizing the hybridmodulation technique:

• considerable reduction in the size and volume of the inputinductance ; because the input inductance tolerates nomore than ;

• reduction in the THD and EMI at the input side;• low switching loss; because at each time only one cell

works in high frequency switching mode.To determine the duty cycle of the PWM signal, the following

method is used. Assuming that the operating voltage region isand the amplitude of input voltage is constant during the

switching period, the change of inductor current can be ap-proximated as follows:

if

if(11)

where is the duration of time during which the powerswitches are on. During , the diagonal switches

or are on and the change of inductor currentis calculated as follows:

if

if(12)

Using (11) and (12), and considering the approximation of, one can conclude that

(13)

where is the switching period, and isthe duty cycle of PWM signal which depends on the value ofvoltage region .

C. Proposed Control Algorithm

The digital controller performs the control algorithm to main-tain voltage balance across the capacitors, while the analog con-



Fig. 6. Flowchart of the control algorithm, the vector �� is a mapping for the voltage of dc buses, sorted in ascending order, i.e., � � � �

� � � � � .

troller regulates the sum of dc bus voltages to . Theproposed control rules, defined hereafter, aim to synthesize thewaveform shown in Fig. 5 and to maintain voltage balancing.

1) If , , and voltage region is , thencells with the lowest dc bus voltage are chosen to be

charged in mode “ 1,” the th cell in PWM mode, andthe rest in mode “0”.

2) If , , and voltage region is , thencells with the highest dc bus voltage are chosen to be

discharged in mode “ 1,” the th cell in PWM mode, andthe rest in mode “0”.

3) If , , and voltage region is , thencells with the highest dc bus voltage are chosen to be

discharged in mode “ 1,” the th cell in PWM mode, andthe rest in mode “0”.

4) If , , and voltage region is , thencells with the lowest dc bus voltage are chosen to be

charged in mode “ 1,” the th cell in PWM mode, andthe rest in mode “0”.

To perform the previous rules, the digital controller employsthe flowchart shown in Fig. 6. In the flowchart, the vector

is a mapping for the dc bus voltages, sortedin the ascending order. The value of : “0,” “ 1,” “ 1,” orPWM, represents the cell operating mode.

In Fig. 6, the digital controller takes voltage and current sam-ples with the sampling frequency . Then, the region of inputvoltage is updated according to (8), the control algorithm isperformed, and the appropriate switching functions to aredetermined. The switching functions are applied to the H-bridgecells and the corresponding operating modes are selected by themultiplexers. This procedure is repeated in the succeeding sam-pling periods. As a result, the voltage of each capacitor is reg-ulated by controlling the power flow to the capacitors. For ex-

ample, the cell feeding a heavy load will operate in the chargingmode, most of the time, and in the PWM mode when is small.But, the cell supplying a light load will operate mostly in “0”mode, and when is close to , in PWM mode. The opera-tional behavior of other cells will be between these two extremes(see Fig. 12).

The following remarks about this method are worth noting.• In the proposed controller, there are two modulation mech-

anisms. One is carried out by the analog controller, termedas PWM mode, and the other performed by the digital con-troller, termed as voltage balancing algorithm.

• The PWM mode is used to control the input current and toregulate the sum of dc bus voltages to the reference value,i.e., . This condition, besides the voltagebalancing condition, leads to for .

• The voltage balancing algorithm is repeated with the sam-pling frequency .

• During the sampling period , the switchingfunctions to do not change.

• The switching period (or PWM period) is lower than thesampling period , and the sampling period is lower than

; on the other hand, during the time interval, the switching functions (or operating modes)

may change due to change in dc bus voltages.As an example, it is assumed that the number of H-bridge

cells is , voltage region is , , , andthe sort of dc bus voltages is at . Accordingto the control rules, the switching functions are determined as

“+1,” “0”, and . For this situation, theconfiguration of power switches is shown in Fig. 7(a) and thecells currents are shown in Fig. 7(b).

In Fig. 7(a), it can be seen that the first cell is completely onand its current is equal to the input current, i.e., . The



Fig. 7. (a) Configuration of power cells when � � �, � � �, and the sort of dc bus voltages is � � � � � at � � � (this configuration is validfor � � � � � � � ). (b) Illustration of cells currents for four sampling periods: � � � � � at � � � , � � � � � at � � � � � ,� � � � � at � � � � �� , and � � � � � at � � � .

second cell does not participate in the modulation and its currentis zero. The third cell works in PWM mode and its current is aPWM function of the input current . The thirdcell is charged but not as much as the first one. This state lasts

seconds and again a new update occurs.In Fig. 7(b), the illustration of cells currents are extended for

the next three sampling periods, where the sorts of dc buses areat , at ,

and at . At the voltage region changesto , and hereafter, two cells are selected to work in mode“ 1” and one in PWM.

IV. ESTABLISHING THE CONTROLLER VALIDITY REGIONS

In this section, the load power limits and the validity regionsfor the proposed control algorithm are derived. The followingassumptions are used in the analysis:

1) all converter components are ideal;2) output capacitors are large enough to be treated as constant

voltage sources during switching periods;3) The input current is sinusoidal, i.e.,

(due to presence of the analog controller).To simplify the representation of equations, the average value

of variable “ ” over the time period “ ” is hereafter denoted by“ ” symbol. Also, the subscript “ ” is used to represent thecell number.

The first assumption implies that the CHB rectifier is a loss-less converter and the average input power over a half-cycle

is equal to the total power of distinct loads, i.e.,

(14)

where is the peak input current, the peak input voltage,the input power factor, and the th H-bridge load.

From (4), the cell current can be rewritten as follows:

ififif

(15)

where is the th cell current, the sign of input voltage, andthe PWM current which is expressed as follows:

(16)

where is an arbitrary time. Equations (15) and (16) show thatthe cell current contains a dc term, a lowfrequency harmonic , and a high frequencyswitching ripple. At steady state, the low and high frequencycomponents flow into the th capacitor and the dc term (cellaverage current over a half-cycle, i.e., ) is equal to theth load current .



Fig. 8. Worst case of charging when � � � and� � �: (a) current waveforms of the cells attached to the heavy loads and (b) current waveforms of the cellsattached to the light load.

As the favored dc bus voltage is , the desired load currentwould be . Setting the cell average current equalto the desired load current yields

(17)

Equation (17) is a sufficient condition for , whereis the th cell voltage. The control goal is that all the dc

bus voltages, to , become equal to . Therefore, (17)should be satisfied for all the cells. In the following section, theload power limits and the boundary conditions that satisfy theprevious relation for , are determined.

A. Unity Power Factor Application

1) Load Power Limits in Steady State: In this part, the accept-able power limits for each dc load, which can still guarantee thevoltage balancing, are determined. Let the loads be dividedinto “heavy” loads and - “light loads” ( is an arbitrarynumber between 1 and ). The goal is to find the maximumpower which can be fed to the -loads when the total poweris equal to , i.e., , and the input current is in phasewith the input voltage. The condition is equivalent tothe condition which is satisfied by the analogcontroller.

In the voltage region , cells must work in mode“ 1” (or “ 1”), one in PWM and the rest in mode “0” so, thetotal current fed to all the cells in the region is as follows:

(18)

According to (18), at the sampling periods of the region ,only cells have the chance of being charged. So, in the worstcase scenario, only the cells attached to the heavy loads are se-lected to take part in the modulation if , and to be com-pletely on if .

As an example, it is assumed that the number of H-bridgecells is and the cells loads and are very heavy

. One case of charging is shown in Fig. 8. It is observedthat in the region , the cells attached to the heavy loadsare chosen to work in PWM mode (one cell at each samplingperiod). Also, in the region , one cell works in mode“ 1” and the other in PWM mode. In the regions and

, the first and second cells are completely on, and the cellsconnected to the light loads are chosen to be charged accordingto their dc bus voltages. This procedure is repeated with themains half-cycle period .

Equation (18) and the previous discussion imply that the max-imum average current fed to the -loads over a half-cycle is asfollows:

(19)

where is the upper limit of average current fed tothe -loads over a half-cycle. represents the re-gion , in time domain. Further, and are theaverage of and over the region .

In (19), the sigma term corresponds to the regions thatand the integral term to the regions that . By using

(16) and considering the fact that , the averagecurrents and are obtained, thus

(20)



(21)

The derivation for (21) is shown in Appendix I. Substituting(20) and (21) into (19) and simplifying the equation results in

(22)

Multiplying by gives the maximum power fedto the -loads

(23)

where is the maximum power that can be fed to the-loads over a half-cycle. The cells loads to must satisfy

the limits of (23) for .Using (23) and (9), the upper limits of the cells loads are

obtained as function of the total power. For example, if ,600 V, 2694 V, and 30 kW, the upper limits

of the power are calculated as 8.42 kW,16.43 kW, 23.47 kW, and 28.72 kW. Itmeans that the cells loads to should satisfy four powerlimits: , , ,and , where . Ifthe upper limits are not satisfied, voltage imbalances will appearat the dc bus voltages.

As the total power fed to the -loads is equal to , the lowerlimit of power fed to the -loads is obtained simply from (23)as follows:

(24)

where is the minimum power that can be fed to theloads over a half-cycle.

2) Power Limits During Load-Increase: It is assumed thateach cell supplies its own load and the loads of cells increaseat ( is an arbitrary number between 1 and ). After thischange, the analog controller increases the peak input current

to inject more active power to the loads. Due to this increasein current, the modulation of the cells feeding constant loadsmust change, so that their average currents remain constant. Inthis case, most of the time, the cells attached to the increasedloads will operate in the charging mode and the rest in “0” mode.The worst case of the charging occurs when the total power ofthe unchanged loads becomes equal to the minimum powerfed to the ( - ) cells, i.e., - . Therefore, from(14) and (24), it is concluded that

(25)

where is the total power of the constant loads, the newupper limit of total power, and the new upper limit of thepeak input current after the load-increase. If the input currentincreases beyond this upper limit, the controller will lose theregulation of dc buses. On the other hand, to maintain voltagebalancing and stability, the total power of all loads must be less

Fig. 9. Calculation of �� and �� when the input current leads thevoltage by an angle �.

than , and (23) must be satisfied for , inthe new condition.

B. Reactive Power Control Application

In this case, the phase of input current is shifted relative tothe input voltage to control both the active and reactive powers.This feature improves the flexibility of the rectifier due to capa-bility of reactive compensation. To correctly calculate the powerlimits and validity regions, the expressions given for and

in (20) and (21) must be modified.We consider the scheme shown in Fig. 9, where the input cur-

rent leads the voltage by an angle . Following a similar ap-proach as the one in Section III, the new expressions forand are derived and shown in (26) and (27)

(26)

(27)

It is to be noted that during computation of the previous equa-tions, and should be replaced by and [definedin (10)] if the time variable “ ” is between and . Whenthe power factor is not unity, one can find different power limitsand validity regions for the controller by using (26) and (27).For example, by solving the following equation, the minimumphase shift is achieved to manage a no-load cell in the bidirec-tional rectifier:

(28)

In contrast, in unidirectional rectifiers, an additional H-bridgeshould be used to manage a no-load cell if

.

V. SEMICONDUCTOR LOSS ANALYSIS

At an early design stage, knowledge of switching behavioris desirable for the designer to estimate the converter switchinglosses. In the proposed method, the analytical derivation of the



operating modes for an arbitrary cell is complex and beyond thescope of this paper. However, it is possible to calculate the con-duction and switching losses by analytical functions, regardlessof the individual cell’s behavior.

It is assumed that the input current is positive and in phasewith the input voltage. In mode “ 1,” the input current is con-ducted by the diagonal diodes, and , and in mode “0,” bythe bottom switch and the diode [see Fig. 7(a)]. In PWMmode, the current is commutated between and with theswitching frequency , and with completely on. Thus, thetotal semiconductor losses for the cells can be expressed asfollows (in simplified form):

(29)

where is the diode voltage drop, the collector-emittervoltage, the collector-emitter threshold voltage, theon-state resistance of the switch, and theinstant that the voltage region changes. The first term in (29)determines the conduction losses in and the second term theconduction losses in (for all cells). The next expression isrelated to the conduction losses in over a half-cycle. The lasttwo terms calculate the conduction losses generated by and

in PWM mode ( , in the last term, can be approximatedby ).

In the proposed method, there are two types of switchinglosses: the high-frequency switching (PWM) loss and theswitching loss due to voltage balancing control. In this paper,a hysteresis current controller has been utilized. To determinethe PWM switching loss, the switching frequency is estimatedapproximately in the hysteresis mode. Using (11), (12), andthe approximation of (sinu-soidal-band hysteresis current controller), it is concluded that

(30)

where is the instantaneous switching frequency, andis calculated from (9). The average of

TABLE IISIMULATION DATA USED IN THE STUDY OF 11-LEVEL CHB RECTIFIER

switching frequency over the region , i.e., , is obtainedfrom (30) as follows:

(31)

From (31), the average switching frequency over the region, for , is calculated. Assuming that the en-

ergy dissipation during the switching is linearly dependent onthe collector current, the average switching loss (over the mainshalf-cycle) can be calculated by

(32)

In (32), the average input current over the region , i.e.,, has been substituted from (20). and are the en-

ergy dissipation during turn-on and turn-off times, respectively.Using the device datasheet, and are determined for thedesired operating point. Also, the average switching frequencyover the region , i.e., , is estimated form (31).

Another component of the switching loss is due to the changeof operating mode with the sampling frequency (changing



Fig. 10. Mains voltage (top), ac terminal voltage � (middle), and input cur-rent (bottom) during voltage sag.

from “0” to “ 1” and vice versa). In the region , cellsmust operate in the mode “ 1” and ( - ) cells in the mode“0” so, the number of transitions from 0 to 1 must be equalto the transitions from 1 to 0. Thus, the maximum number oftransitions in the region is limited to the minimum ofand ( - ), and the maximum switching loss due to voltagebalancing is derived as follows:

(33)

where is the maximum switching loss caused by thevoltage balancing control. It should be noted that the maximumloss is occurred when the cells loads are equal, i.e.

. Otherwise, the switching loss is lower than (33).As an example, it is assumed that , 2694 V,

600 V, 29.5 kW, , 10 mH, and3 kHz. The IGBT module SKM50GB123D is considered

as the main power switch and the device specifications are ex-tracted from the datasheet ( 1.4 V, 1 V,35 m , 600 V,22 A 3.9 mWs and 600 V,22 A2.9 mWs, and etc.). In this case, the conduction and switchinglosses are calculated as 197.2 W, 32.8 W,and 8.3 W, respectively. It is evident that conductionloss is dominant (82.7%) and the maximum switching loss dueto the voltage balancing is only 3.5% of the total losses. The losspartitioning shows that the proposed control method is suitablefor the high power applications.

Fig. 11. DC bus voltage waveforms during voltage sag, � � 8.4 kW, � �

� � � � 6.55 kW, and � � 1.4 kW (� and � are same as � ).

Fig. 12. Input current (top) and cells currents (� , � , and � ) for a line-period. The load of first cell � is close to the upper limit and the load of lastcell � is close to the lower limit of the load power.

VI. SIMULATION RESULTS

The configuration which has been chosen to verify the con-troller behavior is a 30 kW, 11-level, medium voltage converterwith five series-connected H-bridges. Computer simulationshave been carried out using MATLAB/SIMULINK program,with the system parameters given in Table II. The detailedanalysis for deriving the PI controller coefficients can be foundin [22].

The first simulation investigates the general behavior of therectifier, when the H-bridge loads are not equal and a voltagesag ride-through occurs. The load values are 8.4 kW,

6.55 kW, and 1.4 kW, where and have



Fig. 13. Average voltage of dc buses as a function of � (load power of first cell). (a) � � �, � � 2694 V, � � 600 V, � � 30 kW, � � � � � �

� � � � � , and according to (23), � � 1.28 kW, and � � 8.42 kW; (b) � � �, � � 2020 V, � � 600 V, � � 30 kW, � � � � � �

� � � � � , and according to (23), � � �, and � � 11.17 kW.

TABLE IIILOSS PARTITIONING FOR THE INDIVIDUAL CELLS

been chosen close to the upper and lower power limits accordingto (23) ( , 29.5 kW, 2694 V, 600 V,and ). In this simulation, a 50% voltage sag appears inthe primary voltage at 0.3 s and lasts 0.3 s. The simulationresults are shown in Figs. 10–12.

Fig. 10 shows the waveforms of the mains voltage, ac terminalvoltage, and the input current (from top to bottom), respectively.During the voltage sag, the number of voltage regions is auto-matically adjusted to the change of and a seven-level wave-form is synthesized on the ac side. According to (23) and (24),the minimum and maximum load power are 1.3 kWand 8.42 kW, before voltage sag, and and

16.43 kW in sag condition. As a result, the safe op-erating area has increased owing to the two extra cells availablefor synthesizing . It is also observed that the input currentis sinusoidal and in phase with the input voltage. Its amplitudeincreases from 22.3 to 45.5 A, during the sag period.

Fig. 11 shows the dc bus voltages , , and duringvoltage sag compensation. It is seen that all dc buses followthe reference voltage 600 V in both transient and steadystate conditions, although the load values are not equal. Afterthe voltage transitions at 0.3 s and 0.6 s, the capacitorvoltages again approach the reference value and the settling timeis less than 100 ms. The low frequency voltage ripple ,

Fig. 14. Performance of the proposed scheme under load steps: (a) loads cur-rents and (b) corresponding dc bus waveforms.

which is observed at the dc buses, is inherent to the Power FactorCorrection. Increasing the value of smoothing capacitors willreduce the voltage ripple.

In Fig. 12, the input current and the cells current waveformshave been shown. The input current is a sinusoidal waveformwith a high frequency ripple generated by the PWM method. Infact, the plurality of series-connected cells leads to achieve aneffective switching frequency that is many times the switchingfrequency of individual cells.

As already stated, the first cell feeds the maximum load8.4 kW and the last one the minimum load 1.4 kW. It is ob-served that the first cell works in the charging mode, most of thetime, and the last cell in the PWM mode in the region .The conduction and switching losses for these cells are deter-mined by measuring the device voltage and current waveformsand calculating the device losses by the off-line program (IGBTSKM50GB123D is considered as the main power switch). Theresults of the loss partitioning are shown in Table III.

From Table III, it is observed that conduction losses in theH-bridge cells are almost equal, and the switching losses de-pend on the cells loads (switching loss is the sum of PWM



Fig. 15. (a) Prototype of the single-phase seven-level bidirectional CHB rectifier and (b) hardware block diagram of the controller.

TABLE IVSYSTEM PARAMETERS USED IN THE SEVEN-LEVEL CHB RECTIFIER PROTOTYPE

switching loss and the loss due to the voltage balancing con-trol). The cell feeding the heavy load (8.4 kW) has the lowestswitching loss and the cell feeding the light load (1.4 kW) hasthe highest switching loss. The loss distribution among the var-ious cells is approximately even and the cells attached to theequal loads have equal switching losses.

In the first cell, the average switching frequency over a half-cycle, is nearly 3.8 times higher than the last cell (7.2 kHz and 1.9 kHz), but its switching loss is lower.Because, during the PWM mode of the first cell, the currentamplitude is close to zero, and during the PWM mode of thelast cell, it is near to the peak current (see Fig. 12).

To verify the validity of the semiconductor loss analysis, pre-sented in Section V, the conduction and switching losses arecalculated according to (29), (32), and (33). The calculated con-duction and switching losses are 197.2 W and

41.1 W. Comparing the results with the datain Table III shows a good agreement between the simulationand approximate analytical results. Moreover, the calculated av-erage switching frequencies, from (31), for the first and last cells

Fig. 16. DC bus voltage waveforms under voltage sag �� : � (500 V/div),�� : � , � , and � (100 V/div).

are 8.6 kHz and 1.65 kHz, which are close tothe results in Table III.

Fig. 13(a) and (b) verify the analysis of upper and lower limitsof the load power, presented in Section IV. These figures showthe average voltage of and as a function of whilethe total power is 30 kW, 600 V, , and

.As can be seen from Fig. 13, the safe operating area in case

(b) is wider than that in case (a). This is because, in case (b), thepeak input voltage is 2020 V and a maximum of four cellsare needed to synthesize the multilevel waveform, whereas incase (a), five cells are needed to synthesize . In both cases,crossing the power limits will cause instability of dc buses andlose of voltage balancing.

The last simulation verifies the performance of the proposedscheme under load steps. In this simulation, the loads of threecells – , increase simultaneously at 0.2 s. Then, theloads of two cells revert to the initial values at 0.4 s. Thecurrent waveforms and the corresponding dc bus voltages areshown in Fig. 14(a) and (b).



Fig. 17. AC terminal voltage � and input current waveforms; (a) before voltage sag and (b) during 50% voltage sag. (Current scale: 10 A/div; voltage scale:100 V/div).

Based on the analysis presented in Section IV-A, the powerlimits during load-increase are derived as follows: 33 kW,

9.29 kW, 18.1 kW, 25.85 kW,31.64 kW and the simulation data are 27 kW,

7.2 kW, 14.4 kW, 19.8 kW,and 23.4 kW. As the loads satisfy thepower limits, voltage balancing is achieved. The simulation re-sults confirm the validity of analysis.

VII. EXPERIMENTAL RESULTS

The validity of the proposed method is verified using theexperimental results of the laboratory scale prototype. Theprototype is a single-phase, seven-level, bidirectional rectifierwith three series-connected H-bridges. The dc bus voltage ref-erence is 125 V, and the nominal power 1800 W. The nominalac voltage is 230 V and it can vary between 70 and 260 Vrms. Other principal parameters of the prototype are given inTable IV.

Fig. 15(a) and (b), respectively, show the prototype andthe hardware block diagram of the controller employed in theexperimental system. It is to be noted that low voltage powerMOSFETs (MOSFET+Internal Body Diode with the breakdown voltage of 200 V) have been intentionally used in theprototype to demonstrate a scale-down of the real situation.However, in medium voltage levels, the IGBTs would be thebest choice owing to better voltage and current ratings.

First experiment investigates the voltage regulation of dcbuses in steady-state and sag ride-through event. In this exper-iment, the input voltage decreases by 50% from the nominalvalue and regains the initial value after 1200 ms. At all times,the cells loads are constant and the total power is 1000 W. Theresults are shown in Figs. 16 and 17.

In Fig. 16, it can be seen that all dc buses closely follow thereference voltage 125 V and the steady-state errors areless than 1%. The voltage restoration times are less than 200 msand the amplitude of the overshoots (or undershoot) are less than17%.

Fig. 18. Performance of proposed controller under load steps; cells loads (top),and response of dc buses under load steps (bottom).

In Fig. 17, the ac terminal voltage of rectifier and theinput current are shown before voltage sag (left), and duringvoltage sag (right). During sag ride-through, the number ofvoltage regions is automatically adjusted to the change ofand a five-level waveform is generated. The current amplitudealso increases from 4.14 to 8.37 A.

The second experiment evaluates the performance of the pro-posed controller under load steps. In this experiment, the inputvoltage is 230 V, and the cells loads are changed in a step-wisemanner. The power and voltage of each cell is measured, usingthe power analyzer NORMA 5000.

In Fig. 18, initially all loads are equal to 320 W. , , andare increased to 480 W at 30 s, 60 s, and 85 s, re-

spectively. Then, and are reduced to 320 W at 115 s,and returns to the initial value at 140 s. The response ofdifferent dc bus voltages under load steps is depicted in Fig. 18(bottom). It is observed that all dc buses closely follow the ref-erence voltage 125 V, despite sudden load variations. Thesmall steady-state errors observed at dc buses are due to mis-matching of isolation amplifiers utilized in the measurement ofcapacitor voltages.



Fig. 19. Correction of power factor and reactive power compensation capability: (a) �� ; (b) �� 0.8 lead; (c) �� 0.8 lag. (Current scale: 10A/div; voltage scale: 100 V/div).

In the last experiment, the capability of the controller to ad-just the input power factor and to control the reactive power isinvestigated. The input voltage is 230 V, is 1500 W and thecontroller performance is verified for three values of the powerfactor, , 0.8 lead, and 0.8 lag. Thecorresponding waveforms are shown in Fig. 19.

In Fig. 19(a), the current and voltage waveforms have beenshown when the power factor is unity. It is observed that theinput current and the input voltage are in phase and the shape ofinput current is sinusoidal, although the input voltage has somelow order harmonic content. Fig. 19(b) shows a case in whichthe rectifier works in capacitive mode. In this mode, the con-verter injects 1125 VA reactive power to the mains and absorbs1500 W active power from it. In Fig. 19(c), the inductive case isstudied, where the rectifier absorbs 1125 VA reactive power and1500 W active power from the input source. In both inductiveand capacitive modes, the amplitude of input current increasesfrom 6.5 to 8 A rms in order to compensate the input reactivepower.

VIII. CONCLUSION

In this paper, a new control approach for voltage balancing ofdistinct dc buses in CHB rectifiers has been introduced. In theproposed method, the voltage balancing and the current controlare performed even if the load values are not equal or the seriesH-bridges have slightly different characteristics. The suggestedmethod is extremely modular and easy to implement. It is shownthat availability of extra cells for modulation improves the flexi-bility and the safe operating area. The mathematical formulationhas been presented to determine the load power limits and va-lidity regions of the controller. The accuracy of the theoreticalanalysis and control algorithm has been verified using the sim-ulation and experimental results. The experimental prototypeconfirmed the feasibility of working at voltage levels beyond theclassic semiconductor limits using series-connected H-bridges.This structure can be used in traction, high power conditioningand applications where a solid-state transformer is preferred toa heavy and bulky step-down transformer.

APPENDIX ICALCULATION OF AVERAGE PWM CURRENT

OVER THE REGION

To calculate the average of PWM current over the region ,i.e., , we assume that the amplitude of input currentand the input voltage is constant during the switching period

. Considering the definition of in (16), theaverage of PWM current over is approximated as follows:

(A.1)

where is the duty cycle of PWM signal in the region . If foreach , the average of PWM current overthe region can be approximated by the following integral:

(A.2)

Substituting the value of [given in (13)] into (A.2) and sim-plifying the equation results in

(21)

where is the average of PWM current over the region.

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[22] S. Ang and A. Oliva, Power Switching Converters, 2nd ed. BocaRaton, FL: CRC Press, 2005, ch. 6.

Hossein Iman-Eini received the B.Sc. and M.Sc.degrees in electrical engineering from University ofTehran, Tehran, Iran, in 2000 and 2002, respectively,where he is pursuing the Ph.D. degree in electricalengineering, and also from the Institut NationalPolytechnique de Grenoble (INPG), Grenoble,France.

His research interests include multilevel con-verters, control of power converters, and powerelectronics applications in power systems.

Jean-Luc Schanen (SM’04) was born in 1968. Hereceived the Ph.D. degree and electrical engineeringdiploma from Grenoble University, Grenoble,France, in 1994 and 1990, respectively.

He is a Professor with the Grenoble Institute ofTechnology (Grenble INP France), Grenoble, France.He has been within the G2ELab (Grenoble ElectricalEngineering Lab) since 1994, in the field of powerelectronics. His main activities concern the techno-logical design of power converters. His research teamuses (or develops if not available) any kind of mod-

eling tools in order to improve the performances of power electronics converters,including ElectroMagnetic Compatibility and thermal aspects. Converter opti-mization is also in the focus of his research.

Shahrokh Farhangi (M’90) received the B.Sc.,M.Sc., and Ph.D. degrees in electrical engineeringfrom The University of Tehran, Tehran, Iran, withhonors.

He is an Associate Professor with the School ofElectrical and Computer Engineering, University ofTehran. His research interests include design andmodeling of power electronic converters, drives,photovoltaic, and renewable energy systems. Hehas published more than 80 papers in conferenceproceedings and journals. He has managed several

research and industrial projects, which some of them have won national andinternational awards. He has been selected as the distinguished engineer inelectrical engineering by Iran Academy of Sciences, in 2008.

James Roudet was born in 1963. He received thePh.D. degree and electrical engineering diploma fromGrenoble University, Grenoble, France, in 1990 and1986, respectively.

He is a Professor with Grenoble University (Uni-versité Joseph Fourier, France), within the G2ELab(Grenoble Electrical Engineering Lab), in the fieldof power electronics. His first research interest con-cerned resonant converters. Afterwards, he promotedEMC activities in the field of power electronics, anddeveloped a leading activity in the technological de-

sign of power converters. He currently holds the director position of G2ELab,after several years of leading the power electronics team.


a modular strategy for control and voltage balancing of

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