a method of shortening metastable operation duration time by the use of feedback

@stems and Computers in Japan, Vol. 27, No. 10, 1996 Translated from D e ~ h i Joho 'hushin Gakkai Ronbunshi, Vol. J78-D-I, No. 11, November 1995, pp. 886-894

A Method of Shortening Metastable Operation Duration Time by the Use of Feedback

Yoichiro Sato, Takuji Okamoto and Yuji Sugiyama

Faculty of Engineering, Okayama University, Okayama, Japan 700

Masahiro Kawai

Department of Electronics and Computer Engineering, Tsuyama National College of Technology, Tsuyama, Japan 708

Toshifumi Kobayashi

Mitsubishi Electric Semiconductor Software Corporation, Suita, Japan 564

SUMMARY

If metastable operation (MS operation) m u r s in conflict-resolving circuits, propagation delay time of flip-flop (FF) increases by the amount of its duration time and a malfunction may occur. This paper propos- es a method of shortening duration time of MS operation that occurs when two inputs of RSFF consisting of CMOS NAND gates are switched from logic 0 to 1 approximately at the same instant. The MS operation is detected and fed back to inputs so that it is forced to terminate. A configuration of RSFF that has feedback based on this idea is first presented, and then a principle of shortening MS operation duration time follows. Then, considering implementation of RSFF by n-well process, feedback connection and MOSFET parameters are optimized. Although hardware increases slightly by addition of feedback, the result shows the MS operation duration time increase rate against input phase difference (switching time difference of two inputs of RSFF), and the range of input phase difference for MS operation incidence are reduced by ap-

proximately 114 and 113, respectively, compared with conventional methods.

Key words: Metastable operation; feedback; CMOS RS flip-flop.

1. Introduction

In conflict-resolvingcircuits, such as asynchronous arbiters and synchronizers, RS flip-flops (RSFF) are often used in order to compare switching time of two signals 11-31. When switching time difference (called input phase difference) becomes very small, metastable (MS) operation occurs [4], and intermediate voltage between logic 0 and 1 (called intermediate voltage) arises at the output of RSFF temporarily. It may cause a logic error, depending on whether logic elements connected after RSFF, such as gates and flip-flops (called succeeding elements), take intermediatevoltage as logic 0 or 1. Also, if succeeding elements take intermediatevoltage as logic l(0) when the output of RSFF

23 ISSNO882- 1666/96/0010-0023 (B 1996 Scripta Technica, Inc.

Fig. 1. Circuit configuration of RS flip-flop applied to proposed method.

becomes stable from logic l(0) to 0(1) through intermediate voltage, propagation delay time of RSFF increases by the amount of duration time (called MS operation duration time). Thus, if you design succeeding logic circuits under the condition that RSFF’s propagation delay time is below a certain level, malfunctions may arise because of intermediate voltage. Henceforth, such malfunctions are called timing errors. Thus, in reliable systems, it is necessary to prevent or decrease logic mors and timing e m of conflict- resolving circuits.

Several methods are proposed for logic error pre- vention, to add circuits in order to prevent intermediate voltage from propagating to succeeding elements [5-81. In order to decrease timing errors, several methods are proposed to select aspect ratio of gates used in RSFF, so that MS operation duration time increase rate against input phase difference (called MS operation duration time increases rate) is minimized [9-111. However, there is a limitation in reduction of MS operation duration time increase rate by those methods. Furthermore, input phase difference range can hardly be reduced. For instance, when CMOS technology n-well process [ 121 is used, the reduction of MS operation duration time increase rate is at most 1/2.

We propose here a new method that can further reduce MS operation duration time increase rate, and shrink the range of input phase difference for MS operation incidence. This method is based on detecting MS operation, feeding it back to RSFF inputs and forcing it to terminate. Here, we consider MS operation included in RSFF with crossconnected unbuffer- type CMOS NAND gates, when two inputs are switched from logic 0 to 1 almost at the same instance.

In section 2, we present circuit configuration of RSFF that can detect MS operation and has feedback

input voltage -+

Fig. 2. Input-output characteristics of gates.

in order to force it to terminate. Then, we show that the MS operation duration time increase rate is considerably reduced, and input phase difference range for MS operation incidence is considerably shrunk.

In section 3, we discuss optimization of feedback connection to RSFF and MOSFET parameters to mini- mize MS operation duration time increase rate and input phase difference range for MS operation incidence. The result shows that MS operation duration time increase rate and input phase difference range for MS operation incidence are reduced about 1/4 and 1/3, respectively,comparedwith conventionalmethods [lo].

2. Principle of Shortening Metastable Operation Duration Time

As already described, the method of shortening MS operation duration time in this paper is based on detecting MS operation, feeding it back, and forcing it to terminate. The circuit configuration of RS flip-flop, to which this method is applied, is shown in Fig. 1. Inside the dotted line is RS flip-flop consisting of unbuffer-type 3-input CMOS NAND gates, G, and G2. We call it I-RSFF. V, and Voi (i = 1, 2) are input voltage and output voltage, respectively. Inside the chained line is the feedback path consisting of unbuffer-type CMOS inverters, G, and G4, attached in order to shorten MS operation duration time. Vo3 and Vo4 are output voltage of G3 and G,, respectively. We call this feedback path an external feedback, so that it is distinguished from the feedback directly connected from GI(G2)’s output to G2(G1)’s input (called internal feedback). Although V, is put into two inputs of G2 and VOl is put into the remainingone, behavior of Fig.

24

v, /-- VOI u v02

v03

vo4

time - (a) A t > O

time - (b) A t < O

Fig. 3. Timing chart of circuit in Fig. 1 (IAtl >> 0).

1 circuit and the principle of shortening MS operation duration time are the same even if the connection is reversed (Val is put into two inputs, and V,* is put into the remaining one). G,, G, and G4 have the static property shown by the real line in Fig. 2 and G, has the static property shown by the dotted line. Here, the horizontal axis and the vertical axis represent input voltage and output voltage for the gate, respectively. V,, is power source voltage, V, is threshold voltage of G,, G, and G4, and V, is threshold voltage of G,.

In the circuit of Fig. 1, let the initial state be V,, = V,, = O[u, V,, = VO2 = V,,[q. We study the behavior of the circuit when V,l and V, change from O [ q to VDDIVl during time difference (input phase difference) At (positive when V,, changes earlier).

First, we describe the case in which At is suf- ficiently large. As shown in Fig. 3(a), if & > 0, then only V,, decreases from VDD[q toward O[y, and becomes stable at O [ q . Therefore, VO2, VO3, and V04 do

Input phase ( A t ) 4

phase. Fig. 4. Relation between duration time and input

not change at all, and I-RSFF behaves as if there is no external feedback. Figure 3@) shows that, if At < 0, then V,, increases toward VDD[V as Vo2 decreases from VDDIVl toward O [ q . And then, V,, decreases from VDDIVl toward O [ q , but Vol remains VDD[q. Thus, if I&l is large enough, the Fig. 1 circuit behaves in the same manner as one without external feedback.

Next, we describe the case in which IAtl is small. When two inputs are changed from O[Vl to VDD[Y in I-RSFF, let -AtB, 5 At I AtBI be the range of input phase difference where MS operation occurs. (we assume that properties of G, and G2 are the same.) If input in the range of -AtBI 5 At 5 0 is put into Fig. 1 circuit, Vo1 and VO2 begin to decrease. When V02 becomes equal to or below V,M, V,, begins to increase toward VDD[Y, VO3 begins to increase toward V,,[Vj, and V& begins to decrease toward O [ q . As the result, both internal feedback and external feedback function to stabilize V,, = VDD[y and VO2 = O [ q by the same principle. However, internal feedback functions in the opposite direction. Thus a new contention different from input change arises and MS operation occurs. If the former function is more powerful, the circuit becomes stable at Vol = VDD[VJ and V,, = O[Y. Otherwise, the circuit becomes stable at V,, = O [ q and VO2 = VDD[q. If the two functions are at equilibrium, MS operation continues without end theoretically, containing G1-G2 loop and G,- G2-G3-G4 loop.

Figure 4 shows the relationship between input phase difference At and MS operation duration time Tw The horizontal axis and the vertical axis are At and TM, respectively. The real line shows the rela-

25

tionship between At and TM in Fig. 1 circuit. AtL and hR are input phase difference at the boundary of MS operation occurrence in Fig. 1 circuit. Ato is input phase difference where MS operation duration time becomes infinite. For comparison, relationship between At and T, for RS flip-flop (called O-RSFF), consisting of I-RSFF and two-input NAND gates of the same MOSFET property, is shown by the chained line and the dotted line, respectively. -AtBo and Ateo are input phase difference at the boundary of MS operation OC- currence. As shown in the figure, MS operation duration time increase rate gets smaller and input difference range for MS operation incidence gets narrower by applying the shortening method of this paper.

First, we described the reason why MS operation duration time increase rate gets smaller. Generally speaking, positive feedback closed loop (called closed loop) is formed in the circuit when MS operation occurs. And, MS operation duration time increase rate can be approximatedby geometrical mean (called G-C mean) of the ratio of output capacitance and transmission conductance for all gates in the closed loop [9]. In the Circuit of Fig. 1, there exist two closed loops, G1-G2 and G1-G2-G3-G4‘ The latter has a greater ratio of output capacitanceand transmission conductance and dominates the increase rate. Therefore, G-C mean A of Fig. 1 circuit is given by Q. (1). Also, G-C mean A’ of O-RSFF is given by Eq. (2).

I 9) A z - C‘

Here, g and C are transmission conductance and output capacitanceof G, and G2, respectively. g3(g4) and C3(C4) are transmission conductance and output capacitance of G3(G4), respectively. g‘ and C’ are transmission conductance and output capacitance of NAND gates on O-RSFF. From Eqs. (1) and (2), the ratio of G-C means is given by:

1. Furthermore, transmission conductance of CMOS gate is independent of the number of inputs, and is approximately equal to the inverse of current ampli- fication rate of MOSFET that functions at the over- saturation domain [9]. So, g = g3 = g4 - g’, and (gg3g4)/g’4 in the right-hand side is approximately equal to 1. Therefore,A/A’ gets larger than 1, and the MS operation duration time increase rate in Fig. 1 circuit is reduced compared with that of O-RSFF.

Next, we describe why input phase difference range for MS operation grows narrower. The propagation delay time of CMOS gates produced by the same technology is approximately proportional to the number of inputs, if MOSFETs in it are of the same property [12]. Also, if RS flip-flop is configured by cross connection of CMOS gates, input phase difference range for MS operation incidence is approximately proportional to propagation delay time of the gate [13]. Thus, AtBo = %AzBI holds. Therefore, in 0- RSFF, input phase difference range for MS operation incidence is about 4/3 AtB,. On the other hand, the range of input phase difference for MS operation incidence is AtR - AtL, as seen from the figure. AtL is positive, because there is no MS operation if At S 0. Also, AtR S AZBI, because MS operation does not occur in Fig. 1 circuit as long as there is no MS operation in I-RSFF. Therefore, input phase difference range for MS operation incidence in Fig. 1 circuit is equal to or below AtB,. That is, input phase difference range for MS operation incidence in Fig. 1 circuit is narrower than that for O-RSFF.

3. Optimization of Parameters

With the method of shortening MS operation duration time in this paper, MS operation duration time increase rate and input phase difference range for MS operation incidence can be reduced, as described in section 2. However, in Fig. 1 circuit, even if all the M O S F E m are of the same technology and same property, output wave form may have oscillation component in MS operation, depending upon which external input, internal feedback input, or external feedback input (internal feedback, external input) is connected to each input of G1(G2) (called conkchon configuration). The incidence of oscillatory MS operation may cause that noise margin decrease, or intermediate voltage propagation may be difficult to control. There- fore, it is important to reduce oscillation component of MS operation, even if MS operation duration time increase rate and input phase difference range for MS operation incidence are somewhat affected.

Output capacitance of CMOS gates produced by the same technology is approximately proportional to the number of inputs to gate + 1, when the output is in the neighborhood of intermediate voltage [ 101. Thus, let Cw., be output capacitance per input, then C = K-,, C3 = C4 - C-,, C’ = 3Ckp and C’4/(C2C3C4) in the right-hand side of Eq. (3) becomes larger than

26

drain terminal

input output

input terminal 2

gate

source terminal

Fig. 5. MOSFET model.

terminal

So, we first select a set of connection configurations (called optimum connection configuration set) that makes an oscillation component as small as possible without grave impact on reduction of MS operation duration time increase rate and input phase difference range for MS operation incidence. Then, under that configuration, we optimize MOSFET parameters in each gate of Fig. 1, so that MS operation time increase rate and input phase difference range for MS operation incidence become as small as possible.

3.1. Narrowing down parameters for optimization

Optimization described in sections 3.2 and 3.3 is performed by computer simulation after modeling each gate in MOSFET level. We show a MOSFET model in Fig. 5 [14]. R, Cd, C,, and Cg are drain-source re- sistance, drain-substrate capacitance, source-substrate capacitance, and gate-substrate capacitance, respectively. These values are given b$

(4)

Fig. 6. Configuration of NAND gates.

d,, d,, and d4 are parameters (constant). f Takes + for n-type MOSFET, and - for p-type MOSFET.

From the standpoint of strict optimization, it is preferable that parameters are independently variable for each MOSFET in each gate. However, from the standpoint of LSI production, MOSFET parameters in one circuit should be as constant as possible. Here, we take the latter standpoint and we assume that parameter values are the same for all MOSFETs, except threshold voltage of G4' So, parameters are ul, a' 1, u2, a,, a,,, d,, d,, d,, d4, and k, where k is the parameter for threshold voltage of G3, k is the ratio of nMOS- FETs u2 for G3 and the other MOSFETs a,.

3.2. Optimization of connection configuration

We assume that MOSFET level configuration of Fig. 1 NAND gate (G1, G,) is given by Fig. 6. There are six connection configurations of GI according to the connection of external input (I",l), internal feedback (Gis output), and external feedback (G4)s output) with input terminals (input terminal 1 - 3) (refer to Table 1). Also, there are six connection configurations of G, according to the connection of external input (I"'), internal feedback (Gl's output) with input terminals (refer to Table 2).

As an example of optimum connection configuration, we consider MOSFET implemented by n-well process. Parameter value ranges for n-well process are given by Table 3 [ 141. The maximum value of k is de- termined as the ratio of maximum and minimum of a2 in the table. To realize the optimum connection configuration, we selected three values (maximum, standard, minimum) for each parameter within the ranges in Table 3, and performed computer simulation for all the

c d = di vjb -t divdb -k d3

C, = dlVA + dzVsb + ds

(5 )

(6)

Cg = d4 (7)

V', Vds, Vsb, and I", are gate-source voltage, drain- source voltage, source-substrate voltage, and drain- substrate voltage, respectiveiy. a,, a'l, a,, a3, u4, d,,

27

Table 1. Connection configurations at G,

Connection confipration

I I I Input terminal Input terminal Input terminal

1 . 2 3

1-3

1-4

1-5

1-6

1-1 internal feedback I external input I external feedback

internal feedback external feedback external input

external input external feedback internal feedback

external feedback external input internal feedback

external feedback internal feedback external input

1-2 external input internal feedback external feedback I

Connection c o d p a t i o n

Input terminal Input terminal Input terminal 1 2 3

Table 2. Connection configurations at G2

2-2

2-3

2-4

internal feedback internal feedback external input

internal feedback external input internal feedback

external input external input internal feedback

2- 1 external input internal feedback internal feedback

2-5

2-6

external input internal feedback external input

internal feedback external input external input

combinations of connection configurations in Tables 1 and 2 (36 combinations in all) for each combination of these values. The result shows that after entering MS operation, oscillation does not occur in the outputs (V&, VO2) for the combination of connection configurations 1-6 and 2-6 for any combination of parameters. However, for the other combinations of connection configurations, oscillation occurs with vaned oscillation amplitude. On the other hand, when a combination of parameters is fixed, reduction of MS operation duration time increase rate and input phase difference range for MS operation incidence are almost the same, irrelevant of combination of connection configurations.

Reduction of MS operation duration time increase rate and input phase difference range for MS

operation incidence are almost the same when combination of parameters is fixed, irrelevant of combination of connection configuration because the output capacitance and transmission conductance of Gl and G, do not vary very much. The reason why oscillation does not occur in the combination of connection configurations 1-6 and 2-6 can be explained as follows.

According to our analysis, each gate has the fol- lowing transmission function (transmission function from each input to output) within ranges of parameters described above for small signal operation in frequency domain below the oscillation component. The transmission functions of G3 and G4 are always linear. The transmission function of G, is three-dimensional, strictly speaking, but it is approximately linear in connection configuration 1-6, and approximately two-

28

Table 3. Ranges of values of parameters

a; a2

a3

a4

dl d2

Parameter I Range I units

0.01 - 0.06 2.5 x lo3 - 2.7 x lo5 RV

0.1 - 0.3 V 100 - 440 R

2.24 x - 1.38 x p ~ / ~ 2

-1.02 x - -3.51 x p ~ / ~

0 1 I 0.5 - 1.5 I v

d3 I 0.1 N 25.4 I pF 0.5 - 5.2 I PF c, I

dimensional in the other configurations. Likewise, the transmission function of G2 is three-dimensional(strictly speaking), but is approximately linear for any connection configuration and the proximity is the highest in connection configuration 2-6. On the other hand, if we assume that the transmission function of each gate (GI - G4) is linear, their outputs (V,,, VO2) have no oscillation. And if we assume that there is one or more than one gate with two-dimensional transmission function, oscillation occurs. From this argument, transmission functions of G, and G2 become approximately linear, and oscillation does not occur in the combination of connection configurations 1-6 and 2-6.

From this reasoning, we selected connection configurations 1-6 and 2-6 as the optimum set of connection configurations.

33. Optimization of parameters

We performed simulation for all combinations of parameters described in section 3.2, using the set of the optimum connection configurations of G, and G,. The result shows that, for both MS operation duration time increase rate and input phase difference range for MS operation incidence, u,, u2, and k are dominant, but all, u3, (1,’ d, , d,, d3, d, have little influence. Thus, we selected standard values for parameters other than u,, u2, and k (u’ , = 0.039, u3 = 0.23[q, u4 = 250[n], d , = 6.87 x 10-4bF/V2], d2 = -13.61 x 10-3~F/VJ, d3 = 6.l[pFj, and d, = 1.2[pt;I), and we performed detailed study for (I,, u2, and k. Figure 7 shows the result for

k = 2. The vertical axis represents input phase difference range for MS operation incidence AtMs, and MS operation duration time increase rate KR and KL (KR and KL correspond to the right-hand side and the left- hand side of real line in Fig. 3, respectively). The horizontal axes represent u2, and the parameter is u,. The figure shows that AtMs, KR, and K’ are minimum when u1 and u2 are both minimum. This tendency is the same for the case k is not equal to 2. Figure 8 shows AtMs, KR, and, KL, when u1 and u2 are fixed to minimum values (O.S(VJ, 2.5 x lo3 [a . q and k is variable. This figure shows that AtMs KR, and k take the minimum value in a wide range where k is greater than 2. Thus, we selected k = 2 as the optimum value in order to make noise margin as large as possible, and u2 similar to other MOSFETs’ u2.

Figure 9 shows the result of phase plain analysis for optimum parameters. The horizontal axis and the vertical axis are V,, and V,, respectively. The real line represents phase plain trajectory, and the numbers correspond to input phase difference. The initialstable point is V,, = V,, = 5 [ q , and stable points are V,, = O [ q , Vo2 = 5 [ q , and V,, = Vo2 = O [ q . V,, = 2.5[q, Vo2 = 3.8[V) is a saddle point. If inputs vaxy, an operation point moves in the direction of arrows along the phase plain trajectory starting from the initial stable point. And it reaches one of the stable points

There is no oscillation component in any phase plain trajectory. The values of AtMs, K‘, and KR are 5.88[ns], -2.59, and -2.39, respectively. On the other hand, when optimized by Kacprzak’s method [lo], their

V,, = qq, V,2 = 5 [ q or V,, = qq, v,, = o[q.

29

- - ai= O . ~ [ V ] + ai= 0.7[v]

- -ai= 1.2[vl

n

-15

t -10

0 5 10 a2 [ x i04n VI -

(a) AtMS

/& - a i = 0.51~1 + a i = 0.7ivj - * a ai= i = 1 1.2[v] .o[v) - ai= 1.5[v] r / y

I . . . . . . . . . . ' 0 5 10

a2 [ x 1040 - v] - (b) KL

Fig. 7. Evaluation results of AtMs, KL, and KR (k = 2).

0- 1 2 3 4

k- (a) AtMS

t t7 Zk 4 d m O 1 E 2 3 4

k+ (b) KL and h

Fig. 8. Influences of k to evaluation measures.

stable point initial point 5

4

3 t z 8 2 ?

VOI [V] 4

Fig. 9. Phase plains.

values are 17.08[ns], -10.21, and -10.21, respectively. Thus, with the shortening method of this paper, MS operation duration time increase rate and input phase difference range for MS operation incidence are reduced by about 114 and 1/3 respectively, compared with Kacprzak's method.

4. Conclusions

We have proposed here a method than can considerably reduce MS operation duration time increase rate and input phase difference range for MS operation

30

incidence, by using feedback to MS operation of RSFF that consists of CMOS NAND gates. This method can be easily applied to RSFF with cross-connection of two CMOS NOR gates. As for master-slave-typeand edge- trigger-type DF and JKFF, further study is required, and it is a future task.

REFERENCES

1. W. W. Plummer. Asynchronous arbiter. IEEE Trans. Comput., C-21, 1, pp. 37-42 (Jan. 1972).

2. H. Masuyama and N. Toshida. Ring arbiter by asynchronous control cell. Trans. I.E.I.C.E., JU-D, 2, pp. 197-199 (Feb. 1980).

3. J. Calvo, J. I. Acha and M. Valencia. Asynchron- ous modular arbiter. IEEE Trans. Comput., C-35, 1, pp. 67-70 (Jan. 1986).

4. T. J. Chaney and C. E. Molnar. Anomalous behavior of synchronizer and arbiter circuits. IEEE Trans. Comput., C-22,4, pp. 421-422 (April 1973).

5. P. Corsini. n-User asynchronous arbiter. Electron. Lett., 11, 1, pp. 1-2 (Jan. 1975).

6. A. S. Cowan and D. G. Whitehead. Asynchronous polling arbiter. Electron. Lett., 12, 2, pp. 43-44 (Jan. 1976).

7. T. Okamoto and M. Fujiwara. A design method for asynchronous ring arbiter. Trans. I.E.I.C.E.,

8. Y. Matsubara and S. Noguchi. A method for con- figuring asynchronous arbiter with O(1og n) time complexity. Trans. I.E.I.C.E., JM-D, 9, pp. 1039- 1045 (Sept. 1983).

9. S. T. Flannagan. Synchronization realizability in CMOS technology. IEEE J. Solid-Stage Circuits,

10. T. Kacprzak and A, Albicki. Analysis of metastable operation in RS CMOS flip-flops. IEEE J. Solid- State Circuits, SC-22, 1, pp. 57-64 (Feb. 1987).

11. T. Sakurai. Optimization of CMOS arbiter and synchronizer circuits with submicrometer MOS FETs. IEEE J. Solid-state Circuits, SC-23, 4, pp.

12. N. H. E. Weste and K. Eshraghian. Principle of CMOS VLSI Design-A System Perspective. Ad- dison-Wesley, 1985.

Flip-flop resolving time test circuit. IEEE J. Solid-state Circuits, SC-17,4, pp. 731-738 (Aug. 1982).

14. Y. Sato, T. Okamoto and Y. Sugiyama. CMOS NOR gate model for simulation of metastable operation. Trans. I.E.I.C.E., J75-D-I, 10, pp. 900- 908 ( a t . 1992).

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SC-20, 4, pp. 880-882 (Aug. 1985).

901-906 (Aug. 1988).

13. F. Rosenberger and T. J. Chaney.

AUTHORS (from left to right)

Yoicbiro Sato received his B.E., M.E. in 1982 and 1984, respectively, and Dr. of Eng. degrees in Electronics Engineering from Okayama University and he affdiated with Toshiba in 1984. He became a Research Associate at Okayama University in 1989 and a Lecturer in 1990. He received his Ph.D. from Osaka University in 1990. He is engaged in the research of computer system hardware. He is a member of Information Messing Society.

Masahin, Kawai graduated from Tsuyama Engineering Institute in 1975. He affiliated with Olympus in 1983. He because a Research Associate at Tsuyama Engineering Institute in 1968 and a Lecturer in 1993. He is engaged in research on conflict problems in asynchronous circuits.

Takuji O b o t o received his B.E. and Ph.D. degrees in Communication Engineering from Osaka University in 1958 and 1972, respectively. He affiliated with Kawasaki Heavy Industry in 1958, and joined Mitsui Zosen in 1960. In 1967, he joined the Engineering Department of Okayama University, where at present, he is a professor of Information Engineering. He is engaged in research on computer hardware, with a focus on logic circuits. He is a member of Information Processing Society, Electric Society, and IEEE.

31

AUTHORS (continued, from left to right)

Yqji Sugiyama received his B.E. and Ph.D. degrees in Information Science from Osaka University in 1974 and 1983, respectively. He became a Research Associate at Osaka University in 1982. He became a Professor at Okayama University in 1989. He is engaged in research on algebraic specification and its processors. He is a member of Information Processing Society.

Toshifumi Kobayashi received his B.E. and M.E. degrees in Electronic Engineering from Okayama University in 1978 and 1980, respectively. He affiatedwith Mitsubishi Electric in 1980. He is engaged in development of ASIC memory and application of high-level microprocessors in LSI Laboratory of Mitsubishi Electric. He joined Mitsubishi Semiconductor Software in 1992. He is a manager of the Fourth Section of Microcomputer Technology Department. He is a member of IEEE.

I

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a method of shortening metastable operation duration time by the use of feedback

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