a low-power high-speed hybrid cmos full adder for embedded system
DESCRIPTION
A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded System. Reference: Chiou-Kou Tung, “A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded System,” Design and Diagnostics of Electronic Circuits and Systems (DDECS) , Poland, pp. 1-4, April 11-13, 2007. Student: Chien-Nan Lin. - PowerPoint PPT PresentationTRANSCRIPT
A Low-Power High-Speed Hybrid A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded SystemCMOS Full Adder for Embedded System
Student: Chien-Nan Lin
Reference: Reference: Chiou-Kou Tung, “A Low-Power High-Speed Hybrid CMOS Full AddChiou-Kou Tung, “A Low-Power High-Speed Hybrid CMOS Full Add
er for Embedded System,”er for Embedded System,”Design and Diagnostics of Electronic Circuits and Systems (DDECS)Design and Diagnostics of Electronic Circuits and Systems (DDECS),,
Poland, pp. 1-4, April 11-13, 2007Poland, pp. 1-4, April 11-13, 2007
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OutlineOutline
IntroductionIntroduction ReviewReview Proposed Method of Novel Full Adder DesignProposed Method of Novel Full Adder Design ConclusionConclusion
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IntroductionIntroduction
In this paper, a In this paper, a low-powerlow-power high-speedhigh-speed CMOS CMOS full adder core is proposed.full adder core is proposed.The five full adders will be compared with the The five full adders will be compared with the new proposed full adder.new proposed full adder.There are two major methodologies to improve There are two major methodologies to improve adder’s performance.adder’s performance.
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OutlineOutline
IntroductionIntroduction ReviewReview Proposed Method of Novel Full Adder DesignProposed Method of Novel Full Adder Design ConclusionConclusion
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Review (1/5)Review (1/5)
Section review, which reviews the previous Section review, which reviews the previous outstanding full adder designs.outstanding full adder designs.These These five different types of addersfive different types of adders are: are:1.1. Conventional CMOS full adderConventional CMOS full adder2.2. Transmission Function full adderTransmission Function full adder3.3. PTL-based full adderPTL-based full adder4.4. HPSC full adderHPSC full adder5.5. Low-Energy Hybrid full adderLow-Energy Hybrid full adder
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Review (2/5)Review (2/5)ex. Ci=0,A=B=1, S= ,C0= .
Fig. 1. Conventional CMOS full adder
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Defect:This configuration consumes smaller power, but its drawback comes from slower speed.
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Review (3/5)Review (3/5)
Fig. 2. Transmission Function full adder
ex. Ci=0,A=B=1, S= ,C0= .
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Defect:Its disadvantage is slow speed and high power consumption.
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Review (4/5)Review (4/5)
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ex. Ci=0,A=B=1,
S= ,C0= .
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Fig. 3. PTL-based full adder
Defect:
The whole full adder is slower down and consumes more power.
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Review (5/5)Review (5/5)
Fig. 4. HPSC full adder (HPSC) Fig. 5. Low-Energy Hybrid full adder
(LEHPSC)Defect:
Two complementary transistor form the feedback loop to overcome the weak signals caused by pass transistor.
The pass-logic module eliminate the whole propagation speed of the adder.
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OutlineOutline
IntroductionIntroduction ReviewReview Proposed Method of Novel Full Adder DesignProposed Method of Novel Full Adder Design ConclusionConclusion
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Novel Full Adder DesignNovel Full Adder DesignA. New Hybrid Full Adder
S = (A B) C⊕ ⊕ i
C0 = AB+(A+B)Ci
(Conceptual diagram of the new full adder) (Proposed full adder core)
Module 1 implement three-input XOR function to explain in B.
Module 2 implement the function to explain in C.
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Novel Full Adder DesignNovel Full Adder DesignB. Three-input XOR Circuit
(a) Previous 3-XOR (b) New 3-XOR
Although it is merely simple modification, the power consumption and speed are greatly improved.
Normalized resultPd: Power dissipation
Td: Time delay
Power-delay product: Pd ╳ Td
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Novel Full Adder DesignNovel Full Adder DesignC. Carry-Out Module
The PMOS tree mirrors to NMOS tree to simplify the chip layout consideration.
The circuit is adopted as module 2 of the new full adder.
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OutlineOutline
IntroductionIntroduction ReviewReview Proposed Method of Novel Full Adder DesignProposed Method of Novel Full Adder Design ConclusionConclusion
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ConclusionConclusion
A novel hybrid low-power full adder core with output drivingA novel hybrid low-power full adder core with output drivingcapability had been presented in the paper.capability had been presented in the paper.The compared results show that the performance of the proposed The compared results show that the performance of the proposed design is superior to other reference designs.design is superior to other reference designs.
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